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M54/74HC573
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT
HC563 INVERTING - HC573 NON INVERTING
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HIGH SPEED
tPD = 13 ns (TYP.) AT VCC = 5 V
LOW POWER DISSIPATION
ICC = 4 A (MAX.) AT TA = 25 C
HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 6 mA (MIN.)
BALANCED PROPAGATION DELAYS
tPLH = tPHL
WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS563/573
DESCRIPTION
The M54/74HC563 and M54HC573 are high speed
CMOS OCTAL LATCH WITH 3-STATE OUTPUTS
2
fabricated with in silicon gate C MOS technology.
These ICs archive the high speed operation similar
to equivalent LSTTL while maintaning the CMOS
low power dissipation.
These 8 bit D-Type latches are controlled by a latch
enable input (LE) and a output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic level
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R
M74HCXXXM1R
M74HCXXXB1R
M74HCXXXC1R
October 1993
HC573
HC563
HC573
1/13
M54/M74HC563/573
INPUT AND OUTPUT EQUIVALENT CIRCUIT
SYMBOL
OE
2, 3, 4, 5,
6, 7, 8, 9
D0 to D7
Q0 to Q7
11
10
LE
GND
20
V CC
SYMBOL
OE
Data Inputs
2, 3, 4, 5,
6, 7, 8, 9
D0 to D7
Data Inputs
Q0 to Q7
11
10
LE
GND
20
VCC
2/13
HC573
M54/M74HC563/573
TRUTH TABLE
INPUTS
OUTPUTS
OE
H
LE
X
D
X
Q (HC573)
Z
Q (HC563)
Z
L
L
L
L
H
H
X
L
H
NO CHANGE *
L
H
NO CHANGE *
H
L
X: DONT CARE
Z: HIGH IMPEDANCE
*: Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL.
LOGIC DIAGRAMS
HC563
HC573
3/13
M54/M74HC563/573
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC
VI
Supply Voltage
DC Input Voltage
-0.5 to +7
-0.5 to VCC + 0.5
V
V
VO
DC Output Voltage
IIK
IOK
20
20
mA
mA
IO
35
mA
70
mA
500 (*)
mW
ICC or IGND
Parameter
PD
Power Dissipation
Tstg
TL
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
o
o
C
C
Absolute Maximum Ratings are those values beyond which damage tothe device may occur. Functional operation under these conditions is not implied.
(*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
Parameter
Supply Voltage
VI
Input Voltage
VO
Top
Output Voltage
Operating Temperature:
tr, tf
4/13
M54HC Series
M74HC Series
VCC = 2 V
Value
2 to 6
Unit
V
0 to VCC
0 to VCC
-55 to +125
-40 to +85
0 to 1000
V
C
o
C
ns
VCC = 4.5 V
0 to 500
VCC = 6 V
0 to 400
M54/M74HC563/573
DC SPECIFICATIONS
Test Conditions
Symbol
VIH
V IL
Parameter
Value
VCC
(V)
TA = 25 oC
54HC and 74HC
Min. Typ. Max.
2.0
1.5
1.5
1.5
4.5
6.0
3.15
4.2
3.15
4.2
3.15
4.2
High Level
Output Voltage
0.5
0.5
0.5
4.5
1.35
1.35
1.35
2.0
4.5
6.0
4.5
VOL
6.0
2.0
4.5
6.0
4.5
6.0
II
IOZ
ICC
Input Leakage
Current
3 State Output
Off State Current
Quiescent Supply
Current
1.8
1.8
Unit
2.0
6.0
V OH
1.8
1.9
2.0
1.9
1.9
VI =
IO=-20 A
VIH
or
V IL IO=-6.0 mA
4.4
5.9
4.5
6.0
4.4
5.9
4.4
5.9
4.18
4.31
4.13
4.10
IO=-7.8 mA
5.68
5.8
0.0
5.63
5.60
VI =
IO= 20 A
VIH
or
V IL IO= 6.0 mA
0.1
0.1
0.1
0.0
0.1
0.1
0.1
0.0
0.17
0.1
0.26
0.1
0.33
0.1
0.40
IO= 7.8 mA
0.18
0.26
0.33
0.40
VI = VCC or GND
0.1
VI = VIH or VIL
VO = VCC or GND
6.0 VI = VCC or GND
0.5
5.0
10
40
80
6.0
6.0
5/13
M54/M74HC563/573
Symbol
Parameter
VCC
(V)
tTLH
tTHL
Output Transition
Time
2.0
tPLH
tPHL
Propagation
Delay Time
(LE - Q, Q)
tPLH
tPHL
tPZL
tPZH
Propagation
Delay Time
(D - Q, Q)
3 State Output
Enable Time
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
TA = 25 C
54HC and 74HC
Min. Typ. Max.
25
60
CL
(pF)
50
50
150
50
150
50
RL = 1 K
6.0
2.0
tPLZ
tPHZ
3 State Output
Disable Time
tW(L)
tW(H)
Minimum Pulse
Width
ts
th
Minimum Set-up
Time
Minimum Hold
Time
CIN
COUT
Input Capacitance
Output
Capacitance
CPD (*)
Power Dissipation
Capacitance
Value
-40 to 85 oC -55 to 125 oC
74HC
54HC
Min. Max. Min. Max.
75
90
7
6
50
15
13
12
10
115
23
20
15
13
145
29
25
18
15
175
35
30
60
20
17
42
155
31
26
110
195
39
33
140
235
47
40
165
14
12
57
19
16
22
19
150
30
26
28
24
190
38
32
33
28
225
45
38
55
17
140
28
175
35
210
42
14
66
24
180
30
225
36
270
Unit
ns
ns
ns
ns
ns
ns
4.5
6.0
2.0
150
RL = 1 K
22
19
40
36
31
125
45
38
155
54
46
190
ns
4.5
6.0
2.0
4.5
50
RL = 1 K
17
15
40
8
25
21
75
15
31
26
95
19
38
32
110
22
ns
7
16
5
3
13
50
10
9
5
16
65
13
11
5
19
75
15
13
5
5
5
10
5
5
10
5
5
10
6.0
2.0
4.5
6.0
2.0
4.5
6.0
50
50
50
5
10
for HC563
for HC573
49
51
ns
ns
ns
pF
pF
pF
(*) CPD is defined as the value of the ICs internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD VCC fIN + ICC/8 (per Gate)
The CPD when n pcs of FLIP-FLOP operate, can be gained by following equations:
for HC563 CPD (TOTAL) = 33 + 16 x n [pF]; for HC573 CPD (TOTAL) = 33 + 18 x n [pF]
6/13
M54/M74HC563/573
SWITCHING CHARACTERISTICS TEST WAVEFORM
tPLH, tPHL, (D - Q, Q)
tPLZ, tPZL
The 1K load resistors should be connected between
outputs and VCC line and the 50pF load capacitors
should be connected between outputsand GND line.
All inputs except OE input should be connected to VCC
line or GND line such that outputs will be in low logic
level while OE input is held low.
tPHZ, tPZH
The 1K load resistors and the 50pF load capacitors
should be connected between each output and GND
line.
All inputs except OE input should be connected to VCC
or GND line such that output will be in high logic level
while OE input is held low.
VCC
GND
7/13
M54/M74HC563/573
TEST CIRCUIT ICC (Opr.)
8/13
M54/M74HC563/573
DIM.
MIN.
a1
0.254
1.39
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.010
1.65
0.055
0.065
0.45
0.018
b1
0.25
0.010
25.4
1.000
8.5
0.335
2.54
0.100
e3
22.86
0.900
7.1
0.280
3.93
0.155
L
Z
3.3
0.130
1.34
0.053
P001J
9/13
M54/M74HC563/573
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
25
0.984
7.8
0.307
D
E
3.3
0.5
e3
0.130
1.78
0.020
22.86
0.070
0.900
2.29
2.79
0.090
0.110
0.4
0.55
0.016
0.022
1.27
1.52
0.050
0.060
0.22
0.31
0.009
0.012
0.51
1.27
0.020
0.050
N1
P
Q
4 (min.), 15 (max.)
7.9
8.13
5.71
0.311
0.320
0.225
P057H
10/13
M54/M74HC563/573
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
2.65
0.10
0.104
0.20
a2
MAX.
0.004
0.007
2.45
0.096
0.35
0.49
0.013
0.019
b1
0.23
0.32
0.009
0.012
0.50
0.020
c1
45 (typ.)
12.60
13.00
0.496
0.512
10.00
10.65
0.393
0.419
1.27
0.050
e3
11.43
0.450
7.40
7.60
0.291
0.299
0.50
1.27
0.19
0.050
M
S
0.75
0.029
8 (max.)
P013L
11/13
M54/M74HC563/573
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
9.78
10.03
0.385
0.395
8.89
9.04
0.350
0.356
4.2
4.57
0.165
0.180
d1
2.54
0.100
d2
0.56
0.022
7.37
8.38
0.290
0.330
1.27
0.050
e3
5.08
0.200
0.38
0.015
0.101
0.004
1.27
0.050
M1
1.14
0.045
P027A
12/13
M54/M74HC563/573
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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