Beruflich Dokumente
Kultur Dokumente
Key Features
Up to 1200MHz (DDR-2400) operation in DDR4/3
mode in TSMC 28HP and TSMC 28HPM
Supports the highest speed of DDR3, up to 1066MHz
(DDR-2133) operation in TSMC 40G
Supports the highest speed of DDR2, up to 533MHz
(DDR-1066) operation in TSMC 65LP
Complete PHY available with I/Os connected
8-bit datapath macros can be repeated to build PHYs of
any width
Supports DRAM chips with 8 or 16 data bits per chip,
commonly used in soldered-down and unbuffered
DIMM (UDIMM/SoDIMM) applications
Phase_PHY
To Memory Controller (DFI)
phy_param
data_slice_0
data_slice_1
phy_ctrl
io_addr_cntrl
io_control
data_slice_2
data_slice_3
data_slice_ca
To Pads
Technology Support
Hard GDSII implementation for TSMC 65LP, TSMC 40G, TSMC
28HP, or TSMC 28HPM (different Hard PHYs available)
Deliverables
RTL Verilog files for all PHY modules including data slice
Verilog sample testbench with Cadence memory models,
encrypted memory controller, and sample tests
Compatible with Cadence DFI Monitor Verification IP to aid
integration with custom memory controllers
Register configuration files and utilities for programming the
sample simulation testbench, controller, and PHY registers
PHY user guide and implementation guide
Hardened slice
Liberty timing model
Abstract in LEF format
Post-layout Verilog netlist
GDS layout or P&R db (DEF or Cadence Encounter format)
SDF for back-annotated timing verification
Static timing analysis (STA) and signal integrity (SI) reports
LEC report
Physical verification reports (DRC, LVS, ANT)
Synthesis scripts for PHY core level and I/O pad integration
Supported Interfaces
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