Clock Tree Synthesis

Introduction
The goal of Clock Tree Synthesis (CTS) is to buffer clock signals from their root to all the leaf pins, while
meeting your design requirements which may include skew, delay, transition, fanout, power and others.
The clock tree specification file defines these constraints along with other directions to instruct CTS how
to build the clock tree. Once CTS is complete, additional optimization can be performed to improve skew
and latency. Lastly, EDI System provides several clock reporting and analysis tools and commands for
debugging.
Where CTS is used in the flow:

Procedure
Create the CTS Specification File
Create the CTS specification file using the command createClockTreeSpec. The SDCs used to generate the
CTS spec file are:

create_clock - Becomes AutoCTSRootPin in CTS spec file

set_clock_transition - Becomes SinkLeafTran and BufMaxTran (Default: 400 ps)
set_clock_latency value - Becomes MaxDelay (Default: clock period) MinDelay (Default: 0)
set_clock_latency -source value - Becomes SrcLatency value in ns
set_clock_uncertainty - Becomes MaxSkew (Default: 300 ps)
create_generated_clock - Will add necessary ThroughPin statement to the CTS spec file
Additionally, it will define clocks to a clock group if a create_clock statement is applied to multiple
locations.

How to choose buffers for CTS

The libraries contain a range of clock net buffers and inverters that are designed to have nearly matching
rise and fall signal behavior. Such behavior helps the generation of balanced clock circuitry. The cells also
have a much finer step in drive strengths compared to regular buffers and inverters. Additionally, the
clock net buffers are designed such that the input capacitance of each drive strength version is nearly
identical. This offers the possibility to exchange cells in a clock circuit to tune the drive strength without
affecting the loading of the net connected to the input of the cell and affecting the overall clock tree
performance.
clockDesign is unable to automatically determine the buffers to use. The user should specify the buffers
and inverters to use by specifying them during the createClockTreeSpec command. For example:
createClockTreeSpec -file constraints.cts -bufferList {BUFX8 BUFX12 BUFX16 INVX8 INVX12 INVX16}

Understanding of Specification File

Below is the format of the clock tree specification file:

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Copyright 2010, Cadence Design Systems, Inc. All rights reserved.

Clock tree specification file:

#-----------------------------------------------------------# defining the clock shielding
#-----------------------------------------------------------RouteTypeName doublewidth
NonDefaultRule DOUBLEWIDTH_DOUBLESPACE
PreferredExtraSpace 0
TopPreferredLayer 6
BottomPreferredLayer 5
Shielding vss
# shielding will be done from VSS net.
# Non Default Rule "DOUBLEWIDTH_DOUBLESPACE" is used for Shielding.
#-----------------------------------------------------------# Clock Root : clkout # Clock Period: 36.992ns
#-----------------------------------------------------------AutoCTSRootPin clkout
Period 36.992ns
MaxDelay 36.992ns # Define maximum insertion delay
MinDelay 0ns # Define minimum insertion delay
MaxSkew 400ps # Define the maximum skew.
SinkMaxTran 400ps # Define maximum transition at the sink
BufMaxTran 400ps # Define maximum transition at input of clock buffer. Buffer cnivx12 cnivx16 cnivx2
cnivx4 cnivx6
NoGating NO # Auto detects the clock gating and builds the tree through the gating element. If raising it
stops at the first gate.
DetailReport YES
SetIoPinAsSync NO
RouteClkNet YES # Do the clock routing.
PostOpt YES # automatically does the optimization
OptAddBuffer NO
RouteType doublewidth # Specify the routing attributes.
END
In addition, there are other useful (design dependant) constraints, as shown below, which could be part
of the constraints applied to the clock root pin.

To mark the pin as leaf pin:

LeafPin
+ <pinname1>
+ <pinname2>
CTS treats the pins as sinks, stops tracing further, and balances clock skew.
To exclude the pin from the clock tree synthesis:
ExcludedPin
+ <pinname1>
+ <pinname2>
CTS would exclude the pins from the skew analysis.
To preserve the clock tree netlist below the pin:
PreservePin
+ <pinname1>
+ <pinname2>
CTS would preserve the clock structure below the pins specified.
To treat specific cell Pin/Port as non-leaf pin.

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Copyright 2010, Cadence Design Systems, Inc. All rights reserved.

GlobalExcludedPin/GlobalExcludedPort
+ u0/CK CK pin on instances u0 (of DFFRX1) have been declared as excluded pins.
+ DFFRX1/CK This will exclude the CK pin of all DFFRX1 instances from clock tree.
CTS would not to trace or do any skew analysis to this pin specified.

Synthesizing the clock tree

To synthesize the clock tree set the desired mode settings using setCTSMode. Then run clockDesign with
the desired options.
encounter> setCTSMode < >
encounter> clockDesign -specFile <CtsConstraints>
The generated clock tree constraints file may not contain all the necessary constraints. It might require
understanding of clock strategy which might help in defining the root pin. So recommendation is not to
use the auto constraint file blindly but create your own after understanding the clock strategy.
All Clock Group statements must be specified before any clock specification. Clock grouping is done to
ensure that the maximum skew between their sinks does not exceed the max skew time specified in the
clock tree specification file.
Also if there be any overlaps between the buffers added for the different clocks during the synthesis tool
will then calls refinePlace to legalize the placement.
In case any buffer or inverter has to be passing other then specification file we can use the command
createClockTreeSpec.
To prevent CTS from changing a hierarchical module, insert buffers inside or outside of the boundary
ports of the modules and then set PreservePin on those buffers. DontTouchNet/ DontTouchFromToPin
options can be use in the clock tree specification file to preserve a net during CTS.
When net are defined as DontTouchNet then ckSynthesis and ckEco commands will not insert buffers on
those nets. The deleteClockTree command does not delete buffers if their input or output nets have the
DontTouchNet attribute but this is not a physical parameter; so any net specified in this statement can
still be routed.
The DontTouchFromToPin statement will instruct the ckSynthesis and ckEco commands to not insert
buffers for nets that are between the specified start instance pin and end instance pin. Any nets between
these pins are considered to have the DontTouchNet attribute.

Routing the clock tree

The behavior of the clockDesign command can be controlled using setCTSMode command. Clock nets can
be routed in CTS using -routeClkNet option in setCTSMode command or by setting RouteClkNet YES in
clock tree specification file. CTS routes the clock nets by default.
If user wants to use any non default rule/shielding for any particular clock then they have to define the
RouteTypeName along with the rules in the constraint file which later be defined at RouteType in that
particular clock definition.
In case there will be an some routability issues and desire to change the properties of any particular
clock even it already have some property set during CTS then the setAttribute command with -net and preferred_extra_space/-non_default_rule options can be used to attach attributes to the desired nets.

Optimizing the Clock Tree

The optimization of clock tree can be done using the ckECO command to improve the skew of each clock
and clock group, and to resolve minimum phase delay violations.
The ckECO command does not attempt to correct any design rule violations by default. To fix the DRVs
on the clock nets run ckECO -fixDRVOnly separately. However, in trying to improve skew, the ckECO
command does not significantly worsen maximum transition or maximum capacitance violations.
The ckECO command performs resizing and buffer insertion or dummy buffer insertion to improve skew.
In addition, the ckECO command might move gating cells when the ckECO command runs refinePlace.

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Copyright 2010, Cadence Design Systems, Inc. All rights reserved.

The ckECO command also supports local skew optimization (with the -localSkew parameter). Local skew
optimization considers the skew between adjacent flip-flops that have data path connection (from a Q-pin
of one flip-flop to the D-pin of another flipflop).
Below are the options to control the behavior of the ckECO.
-preRoute: Used when there is no license to run NanoRoute; or their flow is to build the clock tree,
optimize clock tree, and then call another router to route the clock net.
-clkRouteOnly: To use immediately after the clock tree is routed.
-postRoute: To use after all signal nets are routed.

Tracing and Analysis of clock tree

The clock tree will trace the clocks before it does the synthesis and dumps the reports in *trace file which
can be used to understand the clock strategy also.
It has been seen that while tracing the clocks if two clocks roots merge to same output pins or there be
some reconvergent points within the same clock or crossover points from one clock to another clock, CTS
fails and won't build the clock tree. So to build the clock tree we have to handle the clock crossover and
reconvergence points.
The below diagram shows the scenarios of crossover and Reconvergence and the command clockDesign
will take care of these scenarios automatically.
If we are using ckSynthesis command then we can use the option forceReconvergent. This option should
be used if the physical partition has muxed clocks and CTS is expected to build a clock tree for every
clock root of the muxed clock. The option will allow CTS to handle (trace through) the muxed clocks and
generate a balanced tree starting from all the clock root branches of the muxed clock.

Examples
Below is an example CTS flow including steps where you would run ckECO. The flow assumes the clock is
routed during CTS.

# Specify the CTS mode settings. For example, specify the preferred layers
# to use and create extra spacing around the clock net to minimize noise:
setCTSMode -bottomPreferredRouteLayer 5 -topPreferredRouteLayer 6
setCTSMode -routePreferredExtraSpace 2
# Instruct CTS to output verbose information for debugging:
setCTSMode -verbose true
# Create the clock tree specification file:
createClockTreeSpec -file constraints.cts -bufferList {CLKBUFX12 CLKBUFX16 CLKBUFX20 CLKINVX12
CLKINVX16 CLKINVX20}
# Run clock tree synthesis using clockDesign.
# - Use the -clk option to only synthesize specified clocks.
# - Use -outDir to specify where to output the report file.
clockDesign -specFile constraints.cts
# Optimize the clock skew of the clock tree after CTS (optional).
setCTSMode -top true
setCTSMode -optAddBuffer true
ckECO -clkRouteOnly
# Perform Post-CTS timing optimization
# Fix clock tree DRVs and Optimize the skew of the clock tree
# after Post-CTS Optimization (optional):
ckECO -fixDRVOnly
ckECO -postCTS
# Perform signal routing

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# Optimize the clock skew after routing (optional):

ckECO -postRoute
# Perform Post-Route optimization and chip finishing

Nov 01, 2010 11:01

Copyright 2010, Cadence Design Systems, Inc. All rights reserved.