VLSI DESIGN

-EEE

Unit-1

MOS Transistor Theory

VLSI DESIGN
UNIT I

Contents:
1.1 Historical Perspective
1.2 What is VLSI? - Introduction
1.3 VLSI Design Flow
1.4

Design Hierarchy

1.5 Basic MOS Transistor

1.6 CMOS Chip Fabrication
1.7 Layout Design Rules
1.8 Lambda Based Rules
1.9 Design Rules - MOSIS Scalable CMOS (SCMOS)

Objective:

* To show the evolution of logic complexity in integrated circuits.

* To understand what is VLSI?
* To illustrate a design flow for logic chips using Y-chart.
* To understand the divide and conquer technique of dividing a module into submodules for the simplicity of design.
* To know the structure, symbol and operation of basic MOS Transistor.
* To know the process flow in chip fabrication and the interaction of various processing
steps.
* To have an overview about Advanced CMOS fabrication technologies.
* To specify the layout design rules in two ways i) Lambda rules ii)micron rules.

1.1 Historical Perspective

The electronics industry has achieved a phenomenal growth over the last two
decades, mainly due to the rapid advances in integration technologies, large-scale systems
design - in short, due to the advent of VLSI. The number of applications of integrated
circuits in high-performance computing, telecommunications, and consumer electronics
has been rising steadily, and at a very fast pace. Typically, the required computational
power (or, in other words, the intelligence) of these applications is the driving force for
the fast development of this field. Figure 1.1 gives an overview of the prominent trends in
information technologies over the next few decades. The current leading-edge
technologies (such as low bit-rate video and cellular communications) already provide the
end-users a certain amount of processing power and portability. This trend is expected to
continue, with very important implications on VLSI and systems design. One of the most
important characteristics of information services is their increasing need for very high
processing power and bandwidth (in order to handle real-time video, for example). The
other important characteristic is that the information services tend to become more and
more personalized (as opposed to collective services such as broadcasting), which means
that the devices must be more intelligent to answer individual demands, and at the same
time they must be portable to allow more flexibility/mobility.
Figure-1.1: Prominent trends in information service technologies.

As more and more complex functions are required in various data processing and
telecommunications devices, the need to integrate these functions in a small
system/package is also increasing. The level of integration as measured by the number of
logic gates in a monolithic chip has been steadily rising for almost three decades, mainly

due to the rapid progress in processing technology and interconnect technology. Table 1.1
shows the evolution of logic complexity in integrated circuits over the last three decades,
and marks the milestones of each era. Here, the numbers for circuit complexity should be
interpreted only as representative examples to show the order-of-magnitude. A logic
block can contain anywhere from 10 to 100 transistors, depending on the function. Stateof-the-art examples of ULSI chips, such as the DEC Alpha or the INTEL Pentium contain 3
to 6 million transistors.

ERA
(number of logic blocks per chip)
Single transistor
Unit logic (one gate)
Multi-function
Complex function
Medium Scale Integration
Large Scale Integration
(LSI)
Very Large Scale Integration
(VLSI)
Ultra Large Scale Integration

DATE

COMPLEXITY

1959
1960
1962
1964
1967
1972

less than 1
1
2-4
5 - 20
20 - 200 (MSI)
200 - 2000

1978

2000 - 20000

1989

20000 - ? (ULSI)

Table-1.1: Evolution of logic complexity in integrated circuits.

The most important message here is that the logic complexity per chip has been (and
still is) increasing exponentially. The monolithic integration of a large number of
functions on a single chip usually provides:

Less area/volume and therefore, compactness

Less power consumption
Less testing requirements at system level
Higher reliability, mainly due to improved on-chip interconnects
Higher speed, due to significantly reduced interconnection length
Significant cost savings

Figure-1.2: Evolution of integration density and minimum feature size, as seen in the
early 1980s.
Therefore, the current trend of integration will also continue in the foreseeable future.
Advances in device manufacturing technology, and especially the steady reduction of
minimum feature size (minimum length of a transistor or an interconnect realizable on
chip) support this trend. Figure 1.2 shows the history and forecast of chip complexity - and
minimum feature size - over time, as seen in the early 1980s. At that time, a minimum
feature size of 0.3 microns was expected around the year 2000. The actual development
of the technology, however, has far exceeded these expectations. A minimum size of 0.25
microns was readily achievable by the year 1995. As a direct result of this, the integration
density has also exceeded previous expectations - the first 64 Mbit DRAM, and the INTEL
Pentium microprocessor chip containing more than 3 million transistors were already
available by 1994, pushing the envelope of integration density.
When comparing the integration density of integrated circuits, a clear distinction must be
made between the memory chips and logic chips. Figure 1.3 shows the level of integration
over time for memory and logic chips, starting in 1970. It can be observed that in terms of
transistor count, logic chips contain significantly fewer transistors in any given year mainly
due to large consumption of chip area for complex interconnects. Memory circuits are
highly regular and thus more cells can be integrated with much less area for interconnects.

Figure-1.3: Level of integration over time, for memory chips and logic chips.
Generally speaking, logic chips such as microprocessor chips and digital signal processing
(DSP) chips contain not only large arrays of memory (SRAM) cells, but also many
different functional units. As a result, their design complexity is considered much higher
than that of memory chips, although advanced memory chips contain some sophisticated
logic functions. The design complexity of logic chips increases almost exponentially with
the number of transistors to be integrated. This is translated into the increase in the design
cycle time, which is the time period from the start of the chip development until the masktape delivery time. However, in order to make the best use of the current technology, the
chip development time has to be short enough to allow the maturing of chip
manufacturing and timely delivery to customers. As a result, the level of actual logic
integration tends to fall short of the integration level achievable with the current
processing technology. Sophisticated computer-aided design (CAD) tools and
methodologies are developed and applied in order to manage the rapidly increasing
design complexity.

1.2 INTRODUCTION
What is VLSI?
VLSI stands for "Very Large Scale Integration". This is the field which involves
packing more and more logic devices into smaller and smaller areas. Thanks to VLSI,
circuits that would have taken boardfuls of space can now be put into a small space few
millimeters across! This has opened up a big opportunity to do things that were not
possible before. VLSI circuits are everywhere ... your computer, your car, your brand new
state-of-the-art digital camera, the cell-phones, and what have you. All this involves a lot
of expertise on many fronts within the same field.
VLSI has been around for a long time, there is nothing new about it ... but as a side effect
of advances in the world of computers, there has been a dramatic proliferation of tools
that can be used to design VLSI circuits. Alongside, obeying Moore's law, the capability of
an IC has increased exponentially over the years, in terms of computation power,
utilization of available area, yield. The combined effect of these two advances is that
people can now put diverse functionality into the IC's, opening up new frontiers.
Examples are embedded systems, where intelligent devices are put inside everyday
objects, and ubiquitous computing where small computing devices proliferate to such an
extent that even the shoes you wear may actually do something useful like monitoring
your heartbeats!
DEALING WITH VLSI CIRCUITS
Digital VLSI circuits are predominantly CMOS based. The way normal blocks like latches
and gates are implemented is different from what students have seen so far, but the
behavior remains the same. All the miniaturization involves new things to consider. A lot
of thought has to go into actual implementations as well as design. Let us look at some of
the factors involved ...
1. Circuit Delays
Large complicated circuits running at very high frequencies have one big problem
to tackle - the problem of delays in propagation of signals through gates and wires ... even
for areas a few micrometers across! The operation speed is so large that as the delays add
up, they can actually become comparable to the clock speeds.
2. Power.
Another effect of high operation frequencies is increased consumption of power.
This has two-fold effect - devices consume batteries faster, and heat dissipation increases.
Coupled with the fact that surface areas have decreased, heat poses a major threat to the
stability of the circuit itself.

3. Layout.
Laying out the circuit components is task common to all branches of electronics.
Whats so special in our case is that there are many possible ways to do this; there can be
multiple layers of different materials on the same silicon, there can be different
arrangements of the smaller parts for the same component and so on.

The power dissipation and speed in a circuit present a trade-off; if we try to optimise on
one, the other is affected. The choice between the two is determined by the way we
chose the layout the circuit components. Layout can also affect the fabrication of VLSI
chips, making it either easy or difficult to implement the components on the silicon.

1.3 VLSI Design Flow

The design process, at various levels, is usually evolutionary in nature. It starts with a
given set of requirements. Initial design is developed and tested against the requirements.
When requirements are not met, the design has to be improved. If such improvement is
either not possible or too costly, then the revision of requirements and its impact analysis
must be considered. The Y-chart (first introduced by D. Gajski) shown in Fig. 1.4
illustrates a design flow for most logic chips, using design activities on three different axes
(domains) which resemble the letter Y.

Figure-1.4: Typical VLSI design flow in three domains (Y-chart representation).

The Y-chart consists of three major domains, namely:

behavioral domain,
structural domain,
geometrical layout domain.

The design flow starts from the algorithm that describes the behavior of the target chip.
The corresponding architecture of the processor is first defined. It is mapped onto the chip
surface by floorplanning. The next design evolution in the behavioral domain defines
finite state machines (FSMs) which are structurally implemented with functional modules
such as registers and arithmetic logic units (ALUs). These modules are then geometrically
placed onto the chip surface using CAD tools for automatic module placement followed
by routing, with a goal of minimizing the interconnects area and signal delays. The third
evolution starts with a behavioral module description. Individual modules are then
implemented with leaf cells. At this stage the chip is described in terms of logic gates (leaf
cells), which can be placed and interconnected by using a cell placement & routing
program. The last evolution involves a detailed Boolean description of leaf cells followed
by a transistor level implementation of leaf cells and mask generation. In standard-cell
based design, leaf cells are already pre-designed and stored in a library for logic design
use.

Figure-1.5: A more simplified view of VLSI design flow.

Figure 1.5 provides a more simplified view of the VLSI design flow, taking into account the
various representations, or abstractions of design - behavioral, logic, circuit and mask
layout. Note that the verification of design plays a very important role in every step during
this process. The failure to properly verify a design in its early phases typically causes
significant and expensive re-design at a later stage, which ultimately increases the timeto-market.
Although the design process has been described in linear fashion for simplicity, in reality
there are many iterations back and forth, especially between any two neighboring steps,
and occasionally even remotely separated pairs. Although top-down design flow provides
an excellent design process control, in reality, there is no truly unidirectional top-down
design flow. Both top-down and bottom-up approaches have to be combined. For
instance, if a chip designer defined an architecture without close estimation of the

corresponding chip area, then it is very likely that the resulting chip layout exceeds the
area limit of the available technology. In such a case, in order to fit the architecture into
the allowable chip area, some functions may have to be removed and the design process
must be repeated. Such changes may require significant modification of the original
requirements. Thus, it is very important to feed forward low-level information to higher
levels (bottom up) as early as possible.
In the following, we will examine design methodologies and structured approaches which
have been developed over the years to deal with both complex hardware and software
projects. Regardless of the actual size of the project, the basic principles of structured
design will improve the prospects of success. Some of the classical techniques for
reducing the complexity of IC design are: Hierarchy, regularity, modularity and locality.

1.4 Design Hierarchy

The use of hierarchy, or divide and conquer technique involves dividing a module into
sub- modules and then repeating this operation on the sub-modules until the complexity
of the smaller parts becomes manageable. This approach is very similar to the software
case where large programs are split into smaller and smaller sections until simple
subroutines, with well-defined functions and interfaces, can be written. In Section 1.2, we
have seen that the design of a VLSI chip can be represented in three domains.
Correspondingly, a hierarchy structure can be described in each domain separately.
However, it is important for the simplicity of design that the hierarchies in different
domains can be mapped into each other easily.
As an example of structural hierarchy, Fig. 1.6 shows the structural decomposition of a
CMOS four-bit adder into its components. The adder can be decomposed progressively
into one- bit adders, separate carry and sum circuits, and finally, into individual logic
gates. At this lower level of the hierarchy, the design of a simple circuit realizing a welldefined Boolean function is much more easier to handle than at the higher levels of the
hierarchy.
In the physical domain, partitioning a complex system into its various functional blocks
will provide a valuable guidance for the actual realization of these blocks on chip.
Obviously, the approximate shape and size (area) of each sub-module should be
estimated in order to provide a useful floor plan. Figure 1.7 shows the hierarchical
decomposition of a four-bit adder in physical description (geometrical layout) domain,
resulting in a simple floor plan. This physical view describes the external geometry of the
adder, the locations of input and output pins, and how pin locations allow some signals (in
this case the carry signals) to be transferred from one sub-block to the other without
external routing. At lower levels of the physical hierarchy, the internal mask

Figure-1.6: Structural decomposition of a four-bit adder circuit, showing the hierarchy

down to gate level.

1.5

Basic MOS Transistor

The most basic element in the design of a large scale integrated circuit is the transistor.
Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) are formed as a
sandwich consisting of a semiconductor layer, usually a slice, or wafer, from a single
crystal of silicon; a layer of silicon dioxide (the oxide) and a layer of metal. These layers
are patterned in a manner which permits transistors to be formed in the semiconductor
material (the substrate); a diagram showing a typical (idealized) MOSFET is shown in
Figure Silicon dioxide is a very good insulator, so a very thin layer, typically only a few
hundred molecules thick, is required. Actually, the transistors which we will use do not
use metal for their gate regions, but instead use polycrystalline silicon (poly). Polysilicon
gate FET's have replaced virtually all of the older devices using metal gates in large scale
integrated circuits. (Both metal and polysilicon FET's are sometimes referred to as
IGFET's --- insulated gate field effect transistors, since the silicon dioxide under the gate
is an insulator.

Figure: MOS transistor

The transistor consists of three regions, labeled the source', the gate and the ``drain''.
The area labeled as the gate region is actually a ``sandwich'' consisting of the underlying
substrate material, which is a single crystal of semiconductor material (usually silicon); a
thin insulating layer (usually silicon dioxide); and an upper metal layer. Electrical charge,
or current, can flow from the source to the drain depending on the charge applied to the
gate region. The semiconductor material in the source and drain region are ``doped''
with a different type of material than in the region under the gate, so an NPN or PNP type
structure exists between the source and drain region of a MOSFET.
An MOS transistor is a majority-carrier device, in which the current in a conducting
channel between the source and the drain is modulated by a voltage applied to the gate.
Symbols

NMOS (n-type MOS transistor)

(1) Majority carrier = electrons
(2) A positive voltage applied on the gate with respect to the substrate enhances the
number of electrons in the channel and hence increases the conductivity of the channel.
(3) If gate voltage is less than a threshold voltage Vt , the channel is cut-off (very low
current between source & drain).
PMOS (p-type MOS transistor)
(1) Majority carrier = holes
(2) Applied voltage is negative with respect to substrate.
Threshold voltage (Vt):
The voltage at which an MOS device begins to conduct ("turn on")
Relationship between Vgs (gate-to-source voltage) and the source-to-drain current
(Ids) , given a fixed drain-to-source voltage (Vds).

MOS Transistor types based on operation:

(1) Devices that are normally cut-off with zero gate bias are classified as "enhancementmode "devices.
(2) Devices that conduct with zero gate bias are called "depletion-mode "devices.
(3) Enhancement-mode devices are more popular in practical use.

1.4.1 NMOS Enhancement Transistor

Consist of
(1) Moderately doped p-type silicon substrate
(2) Two heavily doped n + regions, the source and drain, are diffused.
(3) Channel is covered by a thin insulating layer of silicon dioxide (SiO2) called " Gate
Oxide "
(4) Over the oxide is a polycrystalline silicon (polysilicon) electrode, referred to as the
"Gate".

Features
(1) Since the oxide layer is an insulator, the DC current from the gate to channel is
essentially zero.
(2) No physical distinction between the drain and source regions.
(3) Since SiO2 has low loss and high dielectric strength, the application of high gate fields
is feasible.

In operation
(1) Set Vds > 0 in operation
(2) Vgs =0
no current flow between source and drain. They are insulated by two
reversed-biased PN junctions
(3) When Vg > 0 , the produced E field attracts electrons toward the gate and repels holes.
(4) If Vg is sufficiently large, the region under the gate changes from p-type to ntype(due to accumulation of attracted elections) and provides a conducting path between
source and drain. >The thin layer of p-type silicon is said to be "inverted".
(5) Three modes
a. Accumulation mode (Vgs << Vt)
b. Depletion mode (Vgs =Vt)
c. Inversion mode (Vgs > Vt)

Electrically
(1) An MOS device can be considered as a voltage-controlled switch that conducts when
Vgs >Vt (given Vds>0)
(2) An MOS device can be considered as a voltage-controlled resistor
Effective gate voltage (Vgs-Vt)
At the source end , the full gate voltage is effective in inverting the channel. At the drain
end , only the difference between the gate and drain voltage is effective.

1.4.2 PMOS Enhancement Transistor

(1) Vg < 0
(2) Holes are major carrier
(3) Vd < 0 , which sweeps holes from the source through the channel to the drain .

Current Voltage curves:

1.4.3

Threshold voltage

The threshold voltage of a MOSFET is usually defined as the gate voltage where an
inversion layer forms at the interface between the insulating layer (oxide) and the
substrate (body) of the transistor. The creation of this layer is described next.
In an n-MOSFET the substrate of the transistor is composed of p-type silicon (see doping
(semiconductor)), which has positively charged mobile holes as carriers. When a positive
voltage is applied on the gate, an electric field causes the holes to be repelled from the
interface, creating a depletion region containing immobile negatively charged acceptor
ions. A further increase in the gate voltage eventually causes electrons to appear at the
interface, in what is called an inversion layer, or channel. Historically the gate voltage at
which the electron density at the interface is the same as the hole density in the neutral
bulk material is called the threshold voltage. Practically speaking the threshold voltage is
the voltage at which there are sufficient electrons in the inversion layer to make a low
resistance conducting path between the MOSFET source and drain.
It is a function of
(1) Gate conductor material
(2) Gate insulator material
(3) Gate insulator thickness
(4) Impurity at the silicon-insulator interface
(5) Voltage between the source and the substrate Vsb
(6) Temperature
a. -4 mV/C high substrate doping
b. -2 mV/C low substrate doping

MOS Transistor structure

The basic concept of a MOS Transistor is simple and best understood by looking at its
structure:

It is always an integrated structure, there are practically no single individual MOS

transistors.
A MOS transistor is primarily a switch for digital devices. Ideally, it works as follows:
If the voltage at the gate electrode is "on" , the transistor is "on", too, and current flow
between the source and drain electrodes is possible (almost) without losses. If the
voltage at the gate electrode is "off", the transistor is "off", too, and no current flows
between the source and drain electrode. In reality, this only works for a given polarity of
the gate voltage. Moreover, a MOS transistor needs very thin gate dielectrics (around, or
better below 10 nm), and extreme control of materials and technologies if real MOS
transistors are to behave as they are expected to in "ideal" theory.
Understanding MOS transistor qualitatively is easy. We look at the example from above
and apply some source-drain voltage VSD in either polarity, but no gate voltage yet. What
we have under these conditions is: A n-type Si substrate with a certain equilibrium density
of electrons ne(UG = 0), or ne(0) for short. Its value is entirely determined by doping
(and the temperature, which we will neglect at the present, however) and is the same
everywhere. We also have a much smaller concentration nh(0) of holes.
Two pn-junctions, one of which is polarized in forward direction (the one with the
positive voltage pole), and the other one in reverse. This is true for any polarity; in
particular one junction will always be biased in reverse. Therefore no source-drain
current ISD will flow (or only some small reverse current which we will neglect at
present). There will also be no current in the forwardly biased diode, because the n-Si of
the substrate in the figure is not electrically connected to anything (in reality, we might
simply ground the positive USD pole and the substrate). For a gate voltage UG = 0 V,
there are no currents and everything is in equilibrium. But now apply a negative voltage at
the gate.
The electrons in the substrate below the gate will be electrostatically repelled and driven
into the substrate. Their concentration directly below the gate will go down, ne (U) will
be a function of the depth coordinate z .
Since we still have equilibrium, the mass action law for carriers holds anywhere in
the Si, i.e. .
ne (z) nh (z) = ni2
With ni = intrinsic carrier density in Si
This gives us
nh (z) = ni2 ne (z)
In other words: If the electron concentration below the gate goes down, the hole
concentration goes up.
If we sufficiently decrease the electron concentration under the gate by cranking up the
gate voltage, we will eventually achieve the condition nh (z = 0) = ne (z = 0) right under
the gate, i.e. at z = 0. If we increase the gate voltage even more, we will encounter the

condition nh (z) > ne (z) for small values of z, ie. for zc > z > 0. In other words: Right
under the gate we now have more holes than electrons; this is called a state of inversion
for obvious reasons. Si having more holes than electrons is also called p-type Si. What we
have now is a p-conducting channel (with width zc) connecting the p-conducting source
and drain. There are no more pn-junctions preventing current flow under the gate current can flow freely; only limited by the ohmic resistance of contacts, source/drain and
channel. The resistivity of this channel will be determined by the amount of Si we have
inverted; it will rapidly come down with the voltage as soon as the threshold voltage
necessary for inversion is reached. If we reverse the voltage at the gate, we attract
electrons and their concentration under the gate increases. This is called a state of
accumulation. The pn junctions at source and drain stay intact, and no source - drain
current will flow. Obviously, if we want to switch a MOS transistor "on" with a positive
gate voltage, we must now reverse the doping and use a p-doped substrates and n-doped
source/drain regions. The two basic types we call "n-channel MOS" and "p-channel
MOS" according to the kind of doping in the channel upon inversion (or the source/drain
contacts).

Voltage at the gate

Conditions in
the Si

Voltage drop

Charge
distribution

Nothing
happens. The
band in the
substrate is
perfectly flat
(and so is the
band in the
contact
electrode, but
that is of no
interest).

We only
There are no
would have a
net charges
voltage (or
better
potential)
drop, if the
Fermi energies
of substrate
and gate
electrode
were different

Zero gate voltage.

"Flat band" condition

Positive gate voltage.

Accumulation
With a positive The voltage
voltage at the
drops mostly
gate we attract in the oxide
the electrons
in the
substrate. The
bands must
bend down
somewhat,
and we
increase the
number of
electrons in
the conduction
band
accordingly.
(There is a bit
of a space
charge region
(SCR) in the
contact, but

There is some
positive charge
at the gate
electrode
interface (with
our Si
electrode from
the SCR), and
negative
charge from
the many
electrons in
the (thin)
accumulation
layer on the
other side of
the gate
dielectric.

that is of no
interest).
Small negative gate voltage.
Depletion
With a (small)
negative
voltage at the
gate, we repel
the electrons
in the
substrate.
Their
concentration
decreases, the
hole
concentration
is still low - we
have a layer
depleted of
mobile carriers
and therefore
a SCR.

The voltage
drops mostly
in the oxide,
but also to
some extent in
the SCR.

There is some
negative
charge at the
gate electrode
interface
(accumulated
electrons with
our Si
electrode),
and positive
charge
smeared out in
the the
(extended)
SCR layer on
the other side
of the gate
dielectric.

With a (large)
negative
voltage at the
gate, we repel
the electrons
in the
substrate very
much. The
bands bend so
much, that the
Fermi energy
(red line) is in
the lower half
of the band
close to the
interface. In
this region
holes are the

The voltage
drops mostly
in the oxide,
but also to
some extent in
the SCR and
the inversion
layer.

There is more
negative
charge at the
gate electrode
interface
(accumulated
electrons with
our Si
electrode),
some positive
charge
smeared out in
the the
(extended)
SCR layer on
the other side
of the gate
dielectric, and

Large negagive gate voltage.

Inversion

majority
carriers, we
gave inversion.
We still have a
SCR, too.

a lot of positive
charge from
the holes in
thin inversion
layer.

1.6 CMOS CHIP FABRICATION

Contents :
1.5.1

Introduction

1.5.2

Fabrication Process Flow - Basic Steps

1.5.3 The CMOS n-Well Process

1.5.4 Advanced CMOS Fabrication Technologies

1.5.1 Introduction
In this topic, the emphasis will be on the general outline of the process flow and on the
interaction of various processing steps, which ultimately determine the device and the
circuit performance characteristics. The following chapters show that there are very
strong links between the fabrication process, the circuit design process and the
performance of the resulting chip. Hence, circuit designers must have a working
knowledge of chip fabrication to create effective designs and in order to optimize the
circuits with respect to various manufacturing parameters. Also, the circuit designer must
have a clear understanding of the roles of various masks used in the fabrication process,
and how the masks are used to define various features of the devices on-chip.

The following discussion will concentrate on the well-established CMOS fabrication

technology, which requires that both n-channel (nMOS) and p-channel (pMOS)
transistors be built on the same chip substrate. To accommodate both nMOS and pMOS
devices, special regions must be created in which the semiconductor type is opposite to
the substrate type. These regions are called wells or tubs. A p-well is created in an n-type
substrate or, alternatively, an n- well is created in a p-type substrate. In the simple n-well
CMOS fabrication technology presented, the nMOS transistor is created in the p-type
substrate, and the pMOS transistor is created in the n-well, which is built-in into the ptype substrate. In the twin-tub CMOS technology, additional tubs of the same type as the
substrate can also be created for device optimization.
The simplified process sequence for the fabrication of CMOS integrated circuits on a ptype silicon substrate is shown in Fig. 2.1. The process starts with the creation of the nwell regions for pMOS transistors, by impurity implantation into the substrate. Then, a
thick oxide is grown in the regions surrounding the nMOS and pMOS active regions. The
thin gate oxide is subsequently grown on the surface through thermal oxidation. These
steps are followed by the creation of n+ and p+ regions (source, drain and channel-stop
implants) and by final metallization (creation of metal interconnects).

Figure-2.1: Simplified process sequence for fabrication of the n-well CMOS integrated
circuit with a single polysilicon layer, showing only major fabrication steps.

The process flow sequence pictured in Fig. 2.1 may at first seem to be too abstract, since
detailed fabrication steps are not shown. To obtain a better understanding of the issues
involved in the semiconductor fabrication process, we first have to consider some of the
basic steps in more detail.

1.5.2 Fabrication Process Flow - Basic Steps

Note that each processing step requires that certain areas are defined on chip by
appropriate masks. Consequently, the integrated circuit may be viewed as a set of
patterned layers of doped silicon, polysilicon, metal and insulating silicon dioxide. In
general, a layer must be patterned before the next layer of material is applied on chip. The
process used to transfer a pattern to a layer on the chip is called lithography. Since each
layer has its own distinct patterning requirements, the lithographic sequence must be
repeated for every layer, using a different mask.
To illustrate the fabrication steps involved in patterning silicon dioxide through optical
lithography, let us first examine the process flow shown in Fig. 2.2. The sequence starts
with the thermal oxidation of the silicon surface, by which an oxide layer of about 1
micrometer thickness, for example, is created on the substrate (Fig. 2.2(b)). The entire
oxide surface is then covered with a layer of photoresist, which is essentially a lightsensitive, acid-resistant organic polymer, initially insoluble in the developing solution
(Fig. 2.2(c)). If the photoresist material is exposed to ultraviolet (UV) light, the exposed
areas become soluble so that the they are no longer resistant to etching solvents. To
selectively expose the photoresist, we have to cover some of the areas on the surface with
a mask during exposure. Thus, when the structure with the mask on top is exposed to UV
light, areas which are covered by the opaque features on the mask are shielded. In the
areas where the UV light can pass through, on the other hand, the photoresist is exposed
and becomes soluble (Fig. 2.2(d)).

Figure-2.2: Process steps required for patterning of silicon dioxide.

The type of photoresist which is initially insoluble and becomes soluble after exposure to
UV light is called positive photoresist. The process sequence shown in Fig. 2.2 uses
positive photoresist. There is another type of photoresist which is initially soluble and
becomes insoluble (hardened) after exposure to UV light, called negative photoresist. If
negative photoresist is used in the photolithography process, the areas which are not
shielded from the UV light by the opaque mask features become insoluble, whereas the
shielded areas can subsequently be etched away by a developing solution. Negative
photoresists are more sensitive to light, but their photolithographic resolution is not as
high as that of the positive photoresists. Therefore, negative photoresists are used less
commonly in the manufacturing of high-density integrated circuits.
Following the UV exposure step, the unexposed portions of the photoresist can be
removed by a solvent. Now, the silicon dioxide regions which are not covered by
hardened photoresist can be etched away either by using a chemical solvent (HF acid) or
by using a dry etch (plasma etch) process (Fig. 2.2(e)). Note that at the end of this step,
we obtain an oxide window that reaches down to the silicon surface (Fig. 2.2(f)). The
remaining photoresist can now be stripped from the silicon dioxide surface by using

another solvent, leaving the patterned silicon dioxide feature on the surface as shown in
Fig. 2.2(g).
The sequence of process steps illustrated in detail in Fig. 2.2 actually accomplishes a single
pattern transfer onto the silicon dioxide surface, as shown in Fig. 2.3. The fabrication of
semiconductor devices requires several such pattern transfers to be performed on silicon
dioxide, polysilicon, and metal. The basic patterning process used in all fabrication steps,
however, is quite similar to the one shown in Fig. 2.2. Also note that for accurate
generation of high-density patterns required in sub-micron devices, electron beam (Ebeam) lithography is used instead of optical lithography. In the following, the main
processing steps involved in the fabrication of an n-channel MOS transistor on p-type
silicon substrate will be examined.

Figure-2.3: The result of a single lithographic patterning sequence on silicon dioxide,

without showing the intermediate steps. Compare the unpatterned structure (top) and
the patterned structure (bottom) with Fig. 2.2(b) and Fig. 2.2(g), respectively.
The process starts with the oxidation of the silicon substrate (Fig. 2.4(a)), in which a
relatively thick silicon dioxide layer, also called field oxide, is created on the surface (Fig.
2.4(b)). Then, the field oxide is selectively etched to expose the silicon surface on which
the MOS transistor will be created (Fig. 2.4(c)). Following this step, the surface is
covered with a thin, high-quality oxide layer, which will eventually form the gate oxide of
the MOS transistor (Fig. 2.4(d)). On top of the thin oxide, a layer of polysilicon
(polycrystalline silicon) is deposited (Fig. 2.4(e)). Polysilicon is used both as gate
electrode material for MOS transistors and also as an interconnect medium in silicon
integrated circuits. Undoped polysilicon has relatively high resistivity. The resistivity of
polysilicon can be reduced, however, by doping it with impurity atoms.

After deposition, the polysilicon layer is patterned and etched to form the interconnects
and the MOS transistor gates (Fig. 2.4(f)). The thin gate oxide not covered by polysilicon
is also etched away, which exposes the bare silicon surface on which the source and drain
junctions are to be formed (Fig. 2.4(g)). The entire silicon surface is then doped with a
high concentration of impurities, either through diffusion or ion implantation (in this case
with donor atoms to produce n-type doping). Figure 2.4(h) shows that the doping
penetrates the exposed areas on the silicon surface, ultimately creating two n-type
regions (source and drain junctions) in the p-type substrate. The impurity doping also
penetrates the polysilicon on the surface, reducing its resistivity. Note that the polysilicon
gate, which is patterned before doping actually defines the precise location of the channel
region and, hence, the location of the source and the drain regions. Since this procedure
allows very precise positioning of the two regions relative to the gate, it is also called the
self-aligned process.

Figure-2.4: Process flow for the fabrication of an n-type MOSFET on p-type silicon.

Once the source and drain regions are completed, the entire surface is again covered with
an insulating layer of silicon dioxide (Fig. 2.4(i)). The insulating oxide layer is then
patterned in order to provide contact windows for the drain and source junctions (Fig.
2.4(j)). The surface is covered with evaporated aluminum which will form the
interconnects (Fig. 2.4(k)). Finally, the metal layer is patterned and etched, completing
the interconnection of the MOS transistors on the surface (Fig. 2.4(l)). Usually, a second
(and third) layer of metallic interconnect can also be added on top of this structure by
creating another insulating oxide layer, cutting contact (via) holes, depositing, and
patterning the metal.

1.5.3 The CMOS n-Well Process

Having examined the basic process steps for pattern transfer through lithography, and
having gone through the fabrication procedure of a single n-type MOS transistor, we can
now return to the generalized fabrication sequence of n-well CMOS integrated circuits,
as shown in Fig. 2.1. In the following figures, some of the important process steps
involved in the fabrication of a CMOS inverter will be shown by a top view of the
lithographic masks and a cross-sectional view of the relevant areas.
The n-well CMOS process starts with a moderately doped (with impurity concentration
typically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layer is grown
on the entire surface. The first lithographic mask defines the n-well region. Donor atoms,
usually phosphorus, are implanted through this window in the oxide. Once the n-well is
created, the active areas of the nMOS and pMOS transistors can be defined. Figures 2.5
through 2.10 illustrate the significant milestones that occur during the fabrication process
of a CMOS inverter.

Figure-2.5: Following the creation of the n-well region, a thick field oxide is grown in the
areas surrounding the transistor active regions, and a thin gate oxide is grown on top of
the active regions. The thickness and the quality of the gate oxide are two of the most
critical fabrication parameters, since they strongly affect the operational characteristics of
the MOS transistor, as well as its long-term reliability.

Figure-2.6: The polysilicon layer is deposited using chemical vapor deposition (CVD) and
patterned by dry (plasma) etching. The created polysilicon lines will function as the gate
electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the
polysilicon gates act as self-aligned masks for the source and drain implantations that
follow this step.

Figure-2.7: Using a set of two masks, the n+ and p+ regions are implanted into the
substrate and into the n- well, respectively. Also, the ohmic contacts to the substrate and
to the n-well are implanted in this process step.

Figure-2.8: An insulating silicon dioxide layer is deposited over the entire wafer using
CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon
contact windows. These contact windows are necessary to complete the circuit
interconnections using the metal layer, which is patterned in the next step.

Figure-2.9: Metal (aluminum) is deposited over the entire chip surface using metal
evaporation, and the metal lines are patterned through etching. Since the wafer surface is
non-planar, the quality and the integrity of the metal lines created in this step are very
critical and are ultimately essential for circuit reliability.

Figure-2.10: The composite layout and the resulting cross-sectional view of the chip,
showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal
interconnections. The final step is to deposit the passivation layer (for protection) over
the chip, except for wire-bonding pad areas.
The patterning process by the use of a succession of masks and process steps is
conceptually summarized in Fig. 2.11. It is seen that a series of masking steps must be
sequentially performed for the desired patterns to be created on the wafer surface. An
example of the end result of this sequence is shown as a cross-section on the right.

1.5.4

Advanced CMOS Fabrication Technologies

In this section, two examples will be given for advanced CMOS processes which offer
additional benefits in terms of device performance and integration density. These
processes, namely, the twin-tub CMOS process and the silicon-on-insulator (SOI)
process, are becoming especially more popular for sub-micron geometries where device
performance and density must be pushed beyond the limits of the conventional n-well
CMOS process.
Twin-Tub (Twin-Well) CMOS Process
This technology provides the basis for separate optimization of the nMOS and pMOS
transistors, thus making it possible for threshold voltage, body effect and the channel
transconductance of both types of transistors to be tuned independently. Generally, the
starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer on top. This
epitaxial layer provides the actual substrate on which the n-well and the p-well are
formed. Since two independent doping steps are performed for the creation of the well
regions, the dopant concentrations can be carefully optimized to produce the desired
device characteristics.
In the conventional n-well CMOS process, the doping density of the well region is
typically about one order of magnitude higher than the substrate, which, among other
effects, results in unbalanced drain parasitics. The twin-tub process (Fig. 2.12) also avoids
this problem.

Figure-2.12: Cross-section of nMOS and pMOS transistors in twin-tub CMOS process.

Silicon-on-Insulator (SOI) CMOS Process
Rather than using silicon as the substrate material, technologists have sought to use an
insulating substrate to improve process characteristics such as speed and latch-up
susceptibility. The SOI CMOS technology allows the creation of independent, completely
isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate (for
example: sapphire). The main advantages of this technology are the higher integration

density (because of the absence of well regions), complete avoidance of the latch-up
problem, and lower parasitic capacitances compared to the conventional n-well or twintub CMOS processes. A cross-section of nMOS and pMOS devices in created using SOI
process is shown in Fig. 2.13.
The SOI CMOS process is considerably more costly than the standard n-well CMOS
process. Yet the improvements of device performance and the absence of latch-up
problems can justify its use, especially for deep-sub-micron devices.

Figure-2.13: Cross-section of nMOS and pMOS transistors in SOI CMOS process.

1.7 Layout Design Rules

The physical mask layout of any circuit to be manufactured using a particular process must
conform to a set of geometric constraints or rules, which are generally called layout
design rules. These rules usually specify the minimum allowable line widths for physical
objects on-chip such as metal and polysilicon interconnects or diffusion areas, minimum
feature dimensions, and minimum allowable separations between two such features. If a
metal line width is made too small, for example, it is possible for the line to break during
the fabrication process or afterwards, resulting in an open circuit. If two lines are placed
too close to each other in the layout, they may form an unwanted short circuit by merging
during or after the fabrication process. The main objective of design rules is to achieve a
high overall yield and reliability while using the smallest possible silicon area, for any
circuit to be manufactured with a particular process.
Note that there is usually a trade-off between higher yield which is obtained through
conservative geometries, and better area efficiency, which is obtained through
aggressive, high- density placement of various features on the chip. The layout design
rules which are specified for a particular fabrication process normally represent a
reasonable optimum point in terms of yield and density. It must be emphasized, however,
that the design rules do not represent strict boundaries which separate "correct" designs
from "incorrect" ones. A layout which violates some of the specified design rules may still
result in an operational circuit with reasonable yield, whereas another layout observing all
specified design rules may result in a circuit which is not functional and/or has very low
yield. To summarize, we can say, in general, that observing the layout design rules
significantly increases the probability of fabricating a successful product with high yield.

The design rules are usually described in two ways :

Micron rules, in which the layout constraints such as minimum feature sizes and
minimum allowable feature separations, are stated in terms of absolute dimensions
in micrometers, or,
Lambda rules, which specify the layout constraints in terms of a single parameter
(?) and, thus, allow linear, proportional scaling of all geometrical constraints.

1.8 Lambda Based Rules

Lambda-based layout design rules were originally devised to simplify the industrystandard micron-based design rules and to allow scaling capability for various processes. It
must be emphasized, however, that most of the submicron CMOS process design rules do
not lend themselves to straightforward linear scaling. The use of lambda-based design
rules must therefore be handled with caution in sub-micron geometries.

Based on the assumption of:

half of the minimum feature size

0.75 worst case misalignment of a mask
1.5 worst case misalignment mask to mask
Gives the following rules for an NFET:
2
Minimum width of gate
2
Minimum width of contact

Minimum enclosure of contact by diff

2
Minimum extension of poly beyond diff
2
Minimum space of contact to poly
And the following derived rules:
4
Minimum width of diff
5

Minimum length of diff

In the following, we present a sample set of the lambda-based layout design rules devised
for the MOSIS CMOS process and illustrate the implications of these rules on a section a
simple layout which includes two transistors

MOSIS Layout Design Rules (sample set)

Rule number

Description

R1
R2

Minimum active area width

Minimum active area spacing

R3
R4
R5
R6

Minimum poly width

Minimum poly spacing
Minimum gate extension of poly over active
Minimum poly-active edge spacing
(poly outside active area)
Minimum poly-active edge spacing
(poly inside active area)

R7

L-Rule

3L
3L
2L
2L
2L
1L
3L

R8
R9

Minimum metal width

Minimum metal spacing

R10
R11
R12
R13
R14

Poly contact size

Minimum poly contact spacing
Minimum poly contact to poly edge spacing
Minimum poly contact to metal edge spacing
Minimum poly contact to active edge spacing

2L
2L
1L
1L
3L

R15
R16

Active contact size

Minimum active contact spacing
(on the same active region)
Minimum active contact to active edge spacing
Minimum active contact to metal edge spacing
Minimum active contact to poly edge spacing
Minimum active contact spacing
(on different active regions)

2L

R17
R18
R19
R20

3L
3L

2L
1L
1L
3L

6L

Figure-2.14:
Illustration of some of the typical MOSIS layout design rules listed above.

1.9 Design Rules - MOSIS Scalable CMOS (SCMOS)

1.9.1 Introduction
1.9.2
1.9.3
1.9.4

SCMOS Design Rules

Well Type
SCMOS Options

1.9.1 Introduction

MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their design
rules, which provide a nearly process- and metric-independent interface to many CMOS
fabrication processes available through MOSIS. The designer works in the abstract
SCMOS layers and metric unit ("lambda"). He then specifies which process and feature
size he wants the design to be fabricated in. MOSIS maps the SCMOS design onto that
process, generating the true logical layers and absolute dimensions required by the
process vendor. The designer can often submit exactly the same design, but to a different
fabrication process or feature size. MOSIS alone handles the new mapping.
By contrast, using a specific vendor's layers and design rules ("vendor rules") will yield a
design which is less likely to be directly portable to any other process or feature size.
Vendor rules usually need more logical layers than the SCMOS rules, even though both
fabricate onto exactly the same process. More layers means more design rules, a higher
learning curve for that one process, more interactions to worry about, more complex
design support required, and longer layout development times. Porting the design to a
new
process
will
be
burdensome.
SCMOS designers access process-specific features by using MOSIS-provided abstract
layers which implement those features. For example, a designer wishing to use secondpoly would use the MOSIS-provided second-poly abstract layer, but must then submit to
a process providing for two polysilicon layers. In the same way, designers may access
multiple metals, or different types of analog structures such as capacitors and resistors,
without having to learn any new set of design rules for the more standard layers such as
metal-1. SCMOS is there for portability and simplicity. It is NOT there for fine-tuned
layout.
Vendor rules may be more appropriate when seeking maximal use of silicon area, more
direct control over analog circuit parameters, or for very large production runs, where the
added investment in development time and loss of design portability is clearly justified.
However the advantages of using SCMOS rules may far outweigh such concerns, and
should be considered.

1.9.2 SCMOS Design Rules

In the SCMOS rules, circuit geometries are specified in the Mead and Conway's
lambda based methodology. The unit of measurement, lambda, can easily be
scaled to different fabrication processes as semiconductor technology advances.

Each design has a technology-code associated with the layout file. Each
technology-code may have one or more associated options added for the purpose
of specifying either (a) special features for the target process or (b) the presence of
novel devices in the design. At the time of this revision, MOSIS is offering CMOS
processes with feature sizes from 1.5 micron to 0.18 micron.
Standard SCMOS
The standard CMOS technology accessed by MOSIS is a single polysilicon, double
metal, bulk CMOS process with enhancement-mode n-MOSFET and p-MOSFET
devices.

1.9.3 Well Type

The Scalable CMOS (SC) rules support both n-well and p-well processes.
SCN specifies an n-well process, SCP specifies a p-well process, and SCE indicates
that the designer is willing to utilize a process of either n-well or p-well.
An SCE design must provide both a drawn n-well and a drawn p-well; MOSIS will
use the well that corresponds to the selected process and ignore the other well. As
a convenience, SCN and SCP designs may also include the other well (p-well in an
SCN design or n-well in an SCP design), but it will always be ignored.
MOSIS currently offers only n-well processes or foundry-designated twin-well
processes that from the design and process flow standpoints are equivalent to nwell processes. These twin-well processes may have options (deep n-well) that
provide independently isolated p-wells. For all of these processes at this time use
the technology code SCN. SCP is currently not supported, and SCE is treated
exactly as SCN.

1.9.4 SCMOS Options

SCMOS options are used to designate projects that use additional layers beyond
the standard single-poly, double metal CMOS. Each option is called out with a
designator that is appended to the basic technology-code. Please note that not all
possible combinations are available. The current list is shown in Table 1.
Table 1: SCMOS Technology Options

Designation

Long Form

Description

Electrode

Adds a second polysilicon layer (poly2) that can serve either as

the upper electrode of a poly capacitor or (1.5 micron only) as a
gate for transistors

Analog

Adds electrode (as in E option), plus layers for vertical NPN

transistor pbase

3M

3 Metal

Adds second via (via2) and third metal (metal3) layers

4M

4 Metal

Adds 3M plus third via (via3) and fourth metal (metal4) layers

5M

5 Metal

Adds 4M plus fourth via (via4) and fifth metal (metal5) layers

6M

6 Metal

Adds 5M plus fifth via (via5) and sixth metal (metal6) layers

LC

Linear
Capacitor

Adds a cap_well layer for linear capacitors

PC

Poly Cap

Adds poly_cap, a different layer for linear capacitors

SUBM

Sub-Micron Uses revised layout rules for better fit to sub-micron processes
(see section 2.4)

DEEP

Deep

Uses revised layout rules for better fit to deep sub-micron

processes (see section 2.4)
Table 3a: SCMOS and SCMOS Sub-micron Differences

Rule

Description

SCMOS

SCMOS
sub-micron

1.1, 17.1 Well width

10

12

1.2, 17.2 Well space

(different potential)

18

2.3 Well overlap

(space) to transistor

3.2 Poly space

5.3, 6.3 Contact space

5.5b Contact to Poly

space to Poly

7.2 Metal1 space

7.4 Minimum space

(when metal line is wider than 10 lambda)

8.5 Via on flat

Unrestricted

11.1 Poly2 width

11.3 Poly2 overlap

11.5 Space to Poly2 contact

13.2 Poly2 contact space

15.1 Metal3 width

(3 metal process only)

15.2 Metal3 space

(3 metal process only)

15.4 Minimum space

(when metal line is wider than 10 lambda)
(3 metal process only)

17.3 Minimum spacing to external Active

17.4 Minimum overlap of Active

Table 3b: SCMOS Sub-micron and SCMOS Deep Differences

Rule

Description

SCMOS
sub-micron

SCMOS
DEEP

3.2

Poly space
over field

3.2.a

Poly space
over Active

3.3

Minimum
gate extension
of Active

2.5

3.4

Active extension
beyond Poly

4.3

Select overlap
of Contact

1.5

4.4

Select width and space

(p+ to p+ or n+ to n+)

5.3, 6.3

Contact spacing

8.1

Via width

9.2

Metal2 space

9.4

Minimum space
(when metal line is wider than 10 lambda)

14.1

Via2 width

15.2

Metal3 space

15.4

Minimum space
(when metal line is wider than 10 lambda)
(for 4+ metal processes)

21.1

Via3 width

22.2

Metal4 space
(for 5+ metal processes)

22.4

Minimum space
(when metal line is wider than 10 lambda)

25.1

Exact size

2x2

3x3

26.2

Metal5 space

26.3

Minimum overlap of Via4

(for 5 metal process only)

26.4

Via4 overlap

29.1

Exact size

3x3

4x4

30.3

Minimum overlap of Via5

Summary:
Vlsi technology and its growth has been explained briefly in the early part of introduction. This
filed has witnessed tremendous growth in recent times and made a big impact in the human life
and electronics industry last three decades.
MOS transistor is the basic and fundamental unit of VLSI chips. We have covered extensively
about the working function of MOS transistor and the various modes of it.
There are different technologies adopted for chip fabrication (pmos,nmos,cmos,bicmos,twin
tub).