Chris Basso APEC Seminar 2011

The Dark Side of Flyback
Converters
Presented by Christophe Basso
Senior Scientist
IEEE Senior Member
1 Chris Basso APEC 2011
Course Agenda
The Flyback Converter
The Parasitic Elements
How These Parasitics Affect your Design?
Current-Mode is the Most Popular Scheme
Fixed or Variable Frequency?
More Power than Needed
The Frequency Response
Compensating With the TL431
What is the Subject?

There has been numerous seminars on Flyback converters
Seminars are usually highly theoretical link to the market?
Industrial requirements usually not covered
This 3-hour seminar will shed lights on less covered topics:
Why the converter delivers more power than expected? Solutions?
Books talk about compensation with op amps, I have a TL431!
The origin of the Right-Half Plane Zero, how do I deal with it?
Quasi-resonant converters presence increases, how do they work?
In a 3-hour course, we are just scratching the surface!
The Flyback, a Popular Structure

The flyback converter is widely used in consumer products
Ease of design, low-cost, well-known structure
Poor EMI signature, bulky transformer, practical up to 150 W
DVD player
Set-top box
flyback 10 35 W
Charger
flyback 3 5 W
Notebook
Netbook
flyback 40 180 W
An Isolated Buck-Boost
The flyback converter is derived from the buck-boost cell
2
8
11
SW1
drv
Vin
Vin
Vout
Vout
drv
SW1
Vout
12
gnd
buck-boost
input referenced
buck-boost
ground referenced
Vin
5
gnd
drv
SW1
flyback
isolated ground referenced
The addition of a transformer brings:

Vin
Up or down scale Vin
-k.Vin
Isolation
Polarity change
More than 1 output
The Turn-on Event

The power switch turns on: current ramps up in Lp, D is blocked
NVin
Ip
IC
.
Vin
Lp
I p (t )
Vout
I peak
I peak = I valley +
Vin
ton
Lp
I valley
CCM
ton
I sec = 0
Vin
0V
SW
N = Ns N p
PIV = Vin N + Vout

Reverse voltage on the diode
I peak
I peak =
Vin
ton
Lp
DCM
Vin ton
Son =
Lp
The current increases in the inductor in relationship to Vin and Lp

The output capacitor supplies the load on its own
Simplified, no leakage
Applying Volt-Second Balance, CCM

The power switch turns off: D conducts, Vout "flies" back
Vout
Ip N
Vout N
VLp(t)
IC
Vin
Apply volt-second balance
.
Lp
.
Vout/N
Vin
ton = DTsw
VDS ,off = Vin +
Reflected
voltage
Vout
= Vin + Vr
N
Vout Nton
NDTsw
ND
=
=
=
Vin
toff
(1 D ) Tsw 1 D
toff = (1-D)Tsw
dc transfer function in CCM
Applying Volt-Second Balance, DCM

In DCM, when Lp is fully depleted D opens: Vout reflection is lost
I sec = 0
0V
VLp(t)
IC
.
Lp
Apply volt-second balance
Vin
DT
Vin
Vout /N
ton = DTsw
toff = (1-D)Tsw
VDS ,off = Vin
Vout
Rload
=D
Vin
2 Lp Fsw
dc transfer function in DCM
N no longer plays a role

Rload, Lp and Fsw do
Flyback, Typical Waveforms

Below is a simple flyback converter, without parasitics
X2
XFMR
RATIO = -0.1
6
Vout
Lp
2.2m
5
D1
Ls
IIn
Cout
470u
IC = 10
Rload
2
Vds
Vin
100
D
4
V2
X1
PSW1
RON = 10m
ROFF = 1Meg
V2 4 0 PULSE 0 5 0 10n 10n 3u 10u
It will run open loop for simplicity, Vout 8 V

No parasitics
Flyback, Typical Waveforms, CCM

plot1
iin in amperes
1.60
Ipeak
1.20
800m
Iin(t)
Ivalley
plot2
i(lp) in amperes
Input current
400m
1
Epeak
I L
1.15
1.05
Evalley
950m
ILp(t)
850m
Inductor current
2
750m
plot3
vds in volts
250
190
Vout N + Vin
Diode blocks
Vout N
Vin
130
70.0
Drain voltage
VDS(t)
10.0
plot4
vout in volts
8.89
4
8.87
Output cap.
refueling
8.83
8.81
plot5
id(d1) in amperes
Output voltage
8.85
Output capacitor
supplies the load
Vout(t)
16.0
12.0
8.00
Id(t)
Ipeak / N
Diode current
4.00
0
3.002m
3.006m
3.010m
time in seconds
3.014m
3.018m
CCM flyback no parasitics
Flyback, Typical Waveforms, DCM

Plot1
iin in amperes
400m
Iin(t)
Ipeak
300m
200m
Input current
100m
0
Plot2
i(lp) in amperes
400m
I L
300m
DCM (core reset)
200m
Epeak
ILp(t)
Plot3
vds in volts
400
300
Inductor current
Evalley = 0
100m
Vout N + Vin
Diode blocks
200
Vout N
100
VDS(t)
Drain voltage
Vin
Plot4
vout in volts
12.648
12.644
Output voltage
12.640
12.636
Output cap.
refueling
Plot5
id(d1) in amperes
12.632
3.00
2.00
Output capacitor
supplies the load
Vout(t)
Ipeak / N
Id(t)
1.00
0
Diode current
5
-1.00
3.002m
3.006m
3.010m
time in seconds
3.014m
3.018m
DCM flyback no parasitics
Energy Transfer in CCM and DCM

The primary inductance, Lp, stores and releases energy
1
L p I valley 2
Initially stored energy
2
1
ELp , peak = L p I peak 2
Stored energy at ton
2
1
1
1
ELp ,trans = L p I peak 2 L p I valley 2 = L p ( I peak 2 I valley 2 )
2
2
2
ELp ,valley =
Transmitted energy at Tsw
Power (W) is energy (J) averaged over time (s):

Eta, the efficiency
Pout =
1
I peak 2 I valley 2 L p Fsw
2
CCM
Pout =
1
I peak 2 L p Fsw
2
DCM, Ivalley = 0
Course Agenda
Considering Parasitic Elements

The transformer and the MOSFET include parasitics
X2
XFMR
RATIO = -0.1
rLf
250m
9
D1
1n5819
Vout
Lp
{Lp}
Ls
IIn
Cout
470u
IC = 10
7
2
Vin
100
X1
PSW1
RON = 10m
ROFF = 1Meg
4
V2
Resr
150m
Lleak
{Leak}
Rload
2
Vds
8
Dbody
Clump
100p
parameters
Lp=2.2m
k=0.02
Leak=Lp*k
V2 4 0 PULSE 0 5 0 10n 10n 3u 10u
With parasitics
Considering Parasitic Elements, CCM

Ipeak
plot1
iin in amperes
800m
400m
Iin(t)
Input current
-400m
plot2
i(lp) in amperes
-800m
950m
ILp(t)
850m
Inductor current
750m
2
650m
550m
plot3
vds in volts
770
570
370
(Vout + Vf )
Leakage
inductance
contribution
N + Vin + Vleak
VDS(t)
170
Vin
Drain voltage
3
-30.0
plot4
vout in volts
9.60
9.00
8.40
7.80
Vout(t)
7.20
plot5
id(d1) in amperes
Output voltage
16.0
Id(t)
12.0
8.00
Diode current
5
4.00
0
3.002m
3.006m
3.010m
time in seconds
3.014m
3.018m
CCM mode with parasitics
Considering Parasitic Elements, DCM

plot1
iin in amperes
300m
Ipeak
200m
100m
Iin(t)
Input current
1
plot2
i(lp) in amperes
-100m
DCM (core reset)
300m
ILp(t)
200m
-100m
plot3
vds in volts
370
270
170
(Vout + Vf )
Leakage
inductance
contribution
N + Vin + Vleak
70.0
-30.0
plot4
vout in volts
13.0
Vout(t)
Diode blocks here
12.8
Vin
VDS(t)
Drain voltage
Output voltage
12.6
12.4
4
12.2
plot5
id(d1) in amperes
Inductor current
100m
Id(t)
4.00
3.00
Diode current
2.00
1.00
0
5
3.002m
3.007m
3.012m
time in seconds
3.017m
3.022m
DCM mode with parasitics
Who Are the Stray Elements?

The study of the drain node reveals a LC network
Vbulk
.
.
Vbulk
Lp
.
.
lleak
Coss
Lp primary inductor
lleak leakage inductor
Coss output capacitance
Simplified view
The MOSFET COSS is a Non-Linear Device

The capacitor value changes with its bias voltage
COSS (VDS ) =
CD 0
VDS
1 +
V
0
CD0 is the cap. for VDS = V0
Since bias affects the capacitor value:
1
W = COSSVDS 2
2
As the Voltage Decreases, COSS Value Changes

The brutal discharge generates switching losses
IC ( t ) = C
IC
VC
COSS
MOSFET
dVC ( t )
dt
W = I C ( t )VC ( t ) dt
t
VDS
dVDS ( t )
W = C
VDS ( t ) dt = C (VDS )VDS dVDS
0
0
dt
t
COSS (VDS )
CD 0 V0
VDS
2
W = VDS 3 2CD 0 V0
3
At turn-off
The lost energy is smaller than with the non-linear variation!
Using the Raw COSS is an Overkill

Re-compute the capacitor from the MOSFET data-sheet
VD 0
CD 0
The classical equation gives:
1
W = COSSVDS 2 = 0.5 400 p 1002 = 2 J or 200 mW @ 100 kHz
2
The updated equation gives:
2
2
32
W = VDS CD 0 V0 = 1003 2 400 p 10 = 843 nJ
3
3
or 84 mW @ 100 kHz = 58% reduction
Overkill
The Leakage Inductance

The coupling in a transformer is not perfect
Closed path
in the air
Leakage flux
Leakage flux
Closed path
in the air
Some induction lines couple in the air: leakage flux
An Equivalent Transformer Model

For a two-winding transformer, the model is simple:
Two leakage inductors
One magnetizing inductor
lleak1
primary
lleak2
Lp
secondary
1:N
This is commonly known as the "PI" model
The Transformer Scales the Primary Current

In a perfect transformer, we have:
1: N
. .
Ip
I sec =
Primary
Ip
N
Secondary
The turns ratio is usually normalized to the primary

N p : Ns
Divide by Np
N p = 100
N s = 25
Np
Np
Ns
Np
1: N
. .
1: 0.25
250m
The Leakage Term also Stores Energy

At turn-on, the primary current flows in both lleak and Lp
Lp
I p (t )
I p (t )
Wleak =
lleak
Vin
Son =
Vin
L p + lleak
1
lleak I p 2
2
N=1
During the on-time, both Lp and lleak store energy

Where does the Current Flow?

At turn-off, the energy stored in Lp is dumped in the output cap.
I lleak ( t )
Lp
Vout ( t )
I Lp ( t )
Vin
lleak
I Lp ( t ) I lleak ( t )
I lleak ( t )
Clump
The leakage inductor current fills up the drain lump capacitor

Watch out for the Maximum Excursion!

As the diode conducts, Vout reflects over Lp
Flyback
voltage
Vout + V f
N
I lleak ( t )
VDS ,max = Vin
V
(
+
out
+Vf
N
)+I
peak
lleak
Clump
lleak
Vin
I lleak ( t )
Clump
800
600
400
200
0
The voltage on the drain increases dangerously!

Characteristic
impedance
VDS ( t )
We Need to Clamp that Voltage

MOSFETs have a voltage limit they can fly up to: BVDSS
A clamping circuit has been installed to respect a
margin
Vclamp
Vout + V f
Vclamp
Lp
lleak
D
BVDSS = 600 V
Vin + Vclamp
Resetting the Leakage Inductance

Because of the clamp action, a voltage appears across lleak
Vlleak = Vclamp (Vout + V f
Vclamp
I Lp ( t )
I lleak ( t )
Vout ( t )
Lp
reset
lleak
Vlleak
I lleak ( t )
Slleak =
Vclamp (Vout + V f
lleak
This voltage forces a reset of the leakage inductance

Do we Need a Quick Reset?

When current flows in lleak, it is diverted from the secondary
I lleak ( t )
I Lp ( t )
Lp
I lleak ( t )
lleak
I lleak ( t )
At the switch opening:
I Lp ( t ) = I lleak ( t )
I sec ( t ) = 0
The leakage current delays the occurrence of the sec. current

lleak Delays the Secondary Current

The leakage inductor reduces the peak secondary
current
I p I sec
I (t )
I peak
I p (t )
I Lp , I lleak
I valley
I lleak
ton
I sec ( t )
Primary and
secondary
currents.
toff t
The "stolen" energy is dissipated in heat in the clamping

network
Less energy is transmitted to the secondary side efficiency
suffers
A Reduced Secondary-Side Current

We can calculate the leakage inductor reset time
t
Vclamp (Vout + V f )
I ( t ) I sec
Sl =
lleak
I peak
leak
I p (t )
N1
I lleak ( t )
N = 0.25
lleak = 4.8 H
Vclamp = 150 V
Vout = 19 V
I peak = 3 A
t =
I peak
Slleak
t =
lleak I peak
Vclamp (Vout + V f
I peak
Slleak
Nlleak I peak
NVclamp (Vout + V f
I peak
I peak lleak
1
t
Ssec t =
1
I sec =
N
N
Lp NVclamp
1
+
V
V
out
f
0.25 ( 4.8u 3) )
t =
= 205 ns
0.25 150 (19 + 1)
Typical Example Simulation Results

plot1
ilp in amperes
260m
180m
ILp(t)
Ipeak = 236 mA
Ipeak = 210 mA
Primary current
100m
20.0m
Plot3
illeak in amperes
-60.0m
t = 480 ns
260m
Ileak(t)
180m
100m
20.0m
Leakage inductor
current
-60.0m
trr
plot2
id1 in amperes
2.50
1.30
700m
100m
280
Plot4
vds in volts
Id(t)
Id,peak=2.1 A
1.90
200
Sec. current
11% decrease!
4
VDS(t)
Drain voltage
120
1
40.0
-40.0
3.011m
3.015m
3.019m
time in seconds
3.023m
3.027m
A Ringing Appears as the Diode Blocks

V
+Vf
out
As the clamp diode blocks, the drain returns
Vin to
+
N
Vin
Dclamp blocks
Vr
An oscillation
takes place
Vout
1: N
lleak
Dclamp
I lleak ( t ) = 0
Clump
t
Vin + Vclamp + Vr
Vin + Vclamp + Vr
f =
0V
lleak is reset
1
2 lleak Clump
The Clamp Circuit Overshoots

The clamp diode forward transit time delays the clamping action
Vos = 14 V
VDS(t)
This spike can be lethal to the power MOSFET include margin!

The Primary Inductor also Rings in DCM

When Lp is reset, the capacitor voltage returns
to Vin
Vin
D blocks
0V
An oscillation
takes place
.
1: N
Lp is reset
lleak
Dclamp
Vin
Clump
Vin + Vr
f =
1
2
(L
+ lleak ) Clump
Course Agenda
How these Parasitics Affect your Design?

The leakage inductor induces a large spike at turn-off
This voltage excursion must be kept under control
V
BVDSS
Vclamp
15%
Vin
t
The lump capacitor on the drain brings switching losses

Is there a way to switch on again when discharged?
VDS > Vin
Vin
VDS ( t )
Vin
VDS << Vin
VDS ( t )
Asynchronous switching
Fixed frequency
Synchronous switching
Variable frequency
Protecting the Power MOSFET

A vertical MOSFET features a buried parasitic NPN transistor
The collector-base junction of this transistor forms the body-diode
This diode can accept to avalanche in certain conditions
Do NOT use this diode as a Transient Voltage Suppressor!
Adopt a safety coefficient kD when chosing the maximum VDS(t)
15% derating is usually selected
drain
kD = 0.85
BVDSS k D = 600 0.85 = 510 V
gate
Vclamp = BVDSS k D Vos Vin = 115 V

source
Take Vos around 15 20 V
RCD clamp
design entry
Inclusion of a Safety Margin

The voltage on the drain swings up to Vclamp
Vout = nominal
BVDSS = 600 V
I out = max
Vin = max
Safety margin
Vos
Vclamp
100 V /
div
Vr
Vin
Test at start-up
and in short-circuit
VDS(t)
Capture this waveform in worst-case conditions

Do not Reflect too Much Voltage

The reflected voltage affects the power dissipation in the clamp
PVclamp ,avg
kc
1
2
= Fsw Lleak I peak
2
( kc 1)
kc =
Vclamp
Vr
60
50
40
Pclamp ( W )
30
20
10
0
1.5
2.5
kc
If Vclamp is too close to Vr, dissipation occurs kc = 1.3 to 2
Compute the Transformer Turns Ratio

The turns ratio affects the reflected voltage
Vclamp kc
V
(
+Vf
out
kc (Vout + V f
Vclamp
But also the Peak Inverse Voltage of the secondary diode
PIV = Vin N + Vout

ringing
Choose a 100%
derating factor
Vf
If
PIV = 100 V
Then
BV = 200 V
PIV
Vd ( t )
Always check the margins are not violated in any operating modes
Select the Clamp Passive Elements

The clamp resistor depends on the maximum peak current
Rclp
Vout + V f
(
2Vclamp Vclamp
N
=
Fswlleak I peak 2
Cclp =
Vclamp
Cclp
Rclp
Rclp Fsw V
600 V
I peak ,max =
Vsense ,max
Rsense
Vin ,max
Lp
t prop
550 V
Worst-case value
Watch for the peak current overshoot in fault!

The Leakage Inductor Rings

This ringing can be of high frequency and is radiated-EMI rich
.
Cclp
Rclp .
Rdamp
D
VDS(t)
Watch for
added cap.
It can also forward-bias the MOSFET body diode

Damp it!
Fighting Parasitic Ringing part I

The installed resistor reduces the ringing on the drain
V
With Rdamp
Similar
overshoot
Without Rdamp
VDS(t)
Q=
0lleak
Rdamp
=1
Zlleak @ f 0 = Rdamp
VDS(t)
Fighting Parasitic Ringing part II

If the series resistor is not enough, install a damper
.
Rdamp
1. Measure the ringing: f0

2. Evaluate leakage impedance at f0
Zlleak = 2 lleak f 0
Cdamp
3. Make Rdamp = Z lleak

4. Try Cdamp
1
=
2 f 0 R
5. Tweak for power dissipation
Ray Ridley Snubber design procedure

Effects Brought by the Clamping Action

Vpeak = 510 V
plot1
vdrain in volts
520
VDS(t)
400
280
Fleak = 2.08 MHz
160
40.0
3.0325m
3.0335m
3.0345m
time in seconds
No damper zoom
3.0355m
3.0365m
Plot5
vdrain in volts
490
VDS(t)
370
250
130
10.0
Can forward bias

the body diode
Plot4
vdrain#a in volts
3.042m
490
3.050m
time in seconds
3.054m
Vpeak = 452 V
370
2
3.058m
VDS(t)
250
130
10.0
Rdamp = 290 Cdamp = 220 pF
b
3.042m
Plot3
vdrain#a in volts
3.046m
No damper
3.046m
3.050m
time in seconds
3.054m
3.058m
Vpeak = 494 V
490
VDS(t)
370
250
130
10.0
Rdamp = 290 Cdamp = 50 pF
c
3.042m
3.046m
3.050m
time in seconds
3.054m
3
3.058m
What Diode to Select for the Clamp?

A fast diode is a must: MUR160 is good fit
V = 37 V
VDS(t)
No ringing!
Id(t)
Recovery losses
VDS(t)
Can a simple 1N4007 be used in a RCD clamping network?

The answer is yes for low power applications (below 20 W)
The long recovery time naturally damps the leakage inductor
Be Sure the Clamp Level does not Runaway

Watch-out for clamp voltage variations, at start-up or in short-circuit
The main problem comes from the propagation delay!
140
120
100
Vclamp (V) )
80
60
40
Ipeak (A)
Check the Clamp Voltage Variations

No design margin!
plot1
vdrain in volts
600
400
10
200
0
VDS(t)
-200
150u
450u
750u
time in seconds
1.05m
Drain
voltage
1.35m
Plot2
vclamp in volts
300
200
12
100
0
Vclamp(t)
-100
150u
450u
overshoot
750u
time in seconds
1.05m
Plot3
vsense in volts
1.35m
Max Vsense
1.30
900m
Vsense(t)
500m
100m
15
-300m
150u
450u
750u
time in seconds
1.05m
Plot4
vout in volts
16
10.0
6.00
Vout(t)
Worst case
-2.00
150u
450u
750u
time in seconds
1.05m
Sense
voltage
1.35m
14.0
2.00
Clamp
voltage
1.35m
Output
voltage
A Zener or TVS to Hard Clamp the Voltage

TVS do not suffer from voltage runaways in fault conditions
Vout
Vbulk
TVS
Id(t)
t = 200 ns
Dclp
VDS(t)
PTVS =
1
Fswlleak I peak 2
2
Vz
Vz
(Vout + V f
The TVS improves the efficiency in standby but degrades EMI

It costs around 5 cents
Course Agenda
What Control Scheme?

Two control scheme coexist, current-mode and
voltage-mode
Voltage-mode?
Operating
waveforms
are identical
Current-mode?
Voltage-mode?
Current-mode?
Ac -transfer
functions
differ
Voltage-Mode Control
Voltage mode uses a ramp to generate the duty-ratio
The error voltage directly adjusts the duty-ratio
Vbulk
Vout
.
.
vdd
S
Q
Verr ( t )
D (t )
FB
R
Verr
Vsaw ( t )
Vmax
D (t )
Rsense
Voltage-Mode Control
PROs
Does not need the inductor current information
Can go to very small duty-ratio
CCM operation without sub-harmonic instabilities
No need for slope compensation, current limit
unaffected
CONs
No inherent input line feedforward (weak audio
susceptibility)
Cannot use small bulk capacitor, bad ripple rejection
2nd-order system in CCM: mode transition can be a
problem
Limited integrated circuit offer
Peak-Current-Mode Control
Current mode uses the inductor current information as
a ramp
The error voltage adjusts the inductor peak current
The duty-ratio is indirectly controlled Vout
Vbulk
D (t )
S
Q
Q
vdd
I L (t )
FB
Verr ( t )
+
-
Verr
Rsense
Vmax
I L (t )
Peak-Current-Mode Control
PROs
Inherent pulse-by-pulse current limitation
Natural input line rejection
Mode transition DCM to CCM is easy
Converter remains a 1st-order system at low frequency
Widest offer on the market: a really popular technique!
CONs
Leading Edge Blanking limits the minimum duty-ratio
Requires slope compensation against sub-harmonic
oscillations
Additionnal ramp affects the available maximum peak
current
Current sense can sometimes be a problem (floating
sense)
A Dirty Inductor Current Signal

The inductor current is sensed with a resistor, a
transformer
This information is affected by parasitics: false tripping
possible!
700m
Can potentially
false trip the
controller
500m
300m
100m
1
Vsense ( t )
-100m
3.122m
3.126m
3.131m
3.135m
3.139m
The LEB Cleanses the Signal

A circuit blinds the controller at turn-on for a small time
(250 ns)
It conveys the signal afterwards: Leading Edge Blanking
Vbulk
PWM
reset
.
2
Vsense ( t )
DRV
S2
S1
DRV
t LEB
CS
Rsense
Clean
edges
2
It Limits the Minimum Duty-Ratio

During the LEB duration, the controller is completely
blind!
In output winding short-circuits, failures are likely to
4
+ 80%
0.8 R sense
occur
2.6
VCS ( t )
1.2
t LEB
13.0
V sense ( t )
V DRV ( t )
t LEB + t del
9.00
5.00
1.00
-3.00
591u
594u
597u
600u
603u
tLEB + tdel sets the minimum duty-ratio: cannot go lower, ton,min

If the Primary Inductor is too Low

In short-circuit situations, you reflect the diode forward
Vf
drop
I L (t )
Vbulk
p
Vf
N
.
1
Almost
no decrease
Soff
S on
Rsense
V
= in
Lp
S off =
Son
Vf
NL p
ton ,min
Tsw
If you hit the minimum on-time, you cannot limit the

current!
The Primary Current Runs out of Control

The current current climbs cycle by cycle until smoke
appears!
9.00
Maximum theoretical
peak value, 5 A
Plot1
iprim in amperes
7.00
The current climbs-up

to 9 A!!
5.00
3.00
1.00
Demagnetization
too weak
ok
Chris Basso
first design
ILp(t)
Minimum ton
1.60
Vsense(t)
Plot2
vsense in volts
1.20
1V
800m
400m
8
35.0u
70.0u
105u
time in seconds
140u
175u
Sub-Harmonic Oscillations
Ac analysis shows a first-order system at fc << Fsw/2
No LC peaking anymore as in CCM voltage mode
But a subharmonic peaking at Fsw/2 now appears
25.0
H (s)
15.0
5.00
-5.00
-15.0
180
90.0
0
-90.0
-180
H ( s )
10
Flyback power
stage in CCM
100
1k
10k
100k
Instability Depends on Duty-Ratio

The condition for instability is: CCM operation + duty-ratio > 50%
IL
Ipeak
IL(0)
S1
IL(Tsw)
I peak = a + S1t
Verr
Ri
b = I peak S 2 t
S2
Solving
t
I peak a
IL(Tsw)
S1
IL(0)
IL(0)
t
dTsw
dTsw
Tsw
S2
I L (0) I L (Tsw )
=
S1
S2
IL(Tsw)
I peak b
S2 d
=
S1 d '
d
I L ( nTsw ) = I L (0)
d '
Instability Depends on Duty-Ratio

With a duty-ratio below 50%, perturbation naturally dies out
IL
clock
Ipeak
Duty-ratio < 50%
IL(0)
IL(0)
Asymptotically stable
IL
clock
t
Perturbation has gone
d
I L (nTsw ) = I L (0)
d '
Ipeak
Duty clamp
Duty-ratio > 50%
IL(0)
IL(0)
Asymptotically unstable
The Cure is in the Ramp

Injecting a ramp on the feedback signal, damping is obtained
n
IL
Sa
Verr
Ri
b c
Sa
S1
S2
IL(0)
1 S
2
I L ( nTsw ) = I L (0)
d ' + Sa
d S 2
Must stay
below 1
IL(Tsw)
IL(0)
IL(Tsw)
Up to
d = 100%
t
dTsw
n
= I L (0) ( a )
Sa
1
S2
<1
S
0+ a
S2
dTsw
Tsw
Sa > 50% S2
A Model to Simulate a Flyback Converter

A SPICE model can predict subharmonic instabilities
774mV
DC
441mV
duty-cycle
vc
X2x
XFMR
RATIO = -N
-79.0V
19.7V
vout
19.0V
vout
Vin
100
AC = 0
D1A
mbr20200ctp
100V
PWM switch CM
R10
14.4m
0V
X9
PWMCM
L = Lp
Fs = Fsw
Ri = Ri
Se = Se
B1
Voltage
C5
6600u
V(err)/3 > 1 ?
1 : V(err)/3
parameters
Vout=19
Soff=(Vout/(N*Lp))*Ri
R1
66k
X3
AMPSIMP
2.32V
CoL
1kF
0V
2.50V
LoL
1kH
err
13
N=250m
Fsw=65k
Lp=350u
Ri=250m
A=0.5
Se=A*Soff
Rload
4
19.0V
Lp
{Lp}
2.32V
12
2.32V
10
2.50V
9
15
R2
10k
AC = 1
Vstim
V2
2.5
Simulation Results of the CCM Flyback

As ramp is injected, the double-pole Q is damped
Injecting more ramp turns the converter into voltage-mode
24.0
No ramp
12.0
0
-12.0
-24.0
H (s)
S a = 50% S2
180
No ramp
90.0
0
-90.0
-180
H ( s )
S a = 50% S2
10
100
1k
10k
100k
Modern Circuits Include Slope Compensation

A simple resistor in series with current sense resistor does the job
Vbulk
2.5 V
PWM
reset
Rramp
20 k
k
Q2
R18
S2
VFB 4.2
4
0.8 V
S1
PWM
Q
300 ns
delay
C9
R11
R25
Adjust the resistor to set

the ramp to any level
NCP1250
Course Agenda
Modulation Strategies
The most popular modulation strategy is trailing-edge
VGS(t)
feedback
on
Trailing edge
modulation
off
Clock
Leading-edge modulation often appears in postregulators

V (t)
GS
feedback
on
off
Leading edge
modulation
off
Clock
Fixed Frequency Operation

The vast majority of converters use fixed-frequency operation
Switching losses depend on frequency: high frequency, high
losses!
Capacitive losses are a brake to efficiency improvement
CCM operation induces high losses on the secondary diode
Potential shoot-trough hampers synchronous rectification
The Right Half-Plane Zero severely limits the available
bandwidth
Hard blocking
I D (t )
Noise and losses!
VDS ( t )
Id (t )
VDS ( t )
The Right-Half-Plane Zero

In a CCM flyback, Iout is delivered during the off-time:
Id(t)
Id(t)
IL0
IL1
Vin
Lp
IL(t)
Vin
Lp
IL(t)
Id0
Id1
d
D0Tsw
Tsw
D1Tsw
Tsw
If D brutally increases, D' reduces and Iout drops!

What matters is the inductor current slew-rate
d VL ( t )
dt
Processing the Output Power Demand

If IL(t) can rapidly change, Iout increases when D goes up
200 s
d(t)
d = 59%
Vout(t)
d = 58.3%
IL(t)
Iout(t)
100u
300u
500u
700u
900u
Failing to Increase the Current in Time

If IL(t) is limited because of a big Lp, Iout drops when D increases
2
10 s
d = 59%
d(t)
Vout(t)
Vout drops!
d = 58.3%
IL(t)
Iout(t)
Iout drops!
100u
300u
500u
700u
900u
The RHPZ is a Positive Root

Small-signal equations can help us to formalize it
Voltage
mode
Current
mode
The negative sign

indicates a positive root!
s
s
1
1 +
vout ( s )
z1
z2
= G0
2
d ( s )
s
s
+
1+
Q0 0
s
1 +
z1
vout ( s )
= G0
vc ( s )
s
1
z2
D (s)
s
1 +
z3
Rload D '2
z2 = 2
N DL p
Voltage mode or current mode, the RHPZ remains the same

Simulating the RHPZ

To limit the effects of the RHPZ, limit the duty ratio slew-rate
Choose a crossover frequency equal to 20-30% of RHPZ position
A simple RHPZ can be easily simulated:
R1
10k
K1
C1
10n
Vin
Vin(s)
SUM2
2
E1
10k
Vout ( s ) = Vin ( s ) Vin ( s )
Vout(s)
K2
X1
SUM2
K1 = 1
K2 = 1
R1
s
= Vin ( s ) 1
1
0
sC1
A Zero Producing a Phase Lag

With a RHPZ we have a boost in gain but a lag in phase!
40.0
20.0
|Vout(s)|
+1
LHPZ
0
-20.0
G (s) = 1 +
-40.0
180
90.0
0
G (s) = 1
-90
-180
1
10
RHPZ
argVout(s)
-90.0
100
1k
10k
frequency in hertz
100k
1Meg
Is There a RHPZ in DCM?

A RHPZ also exists in DCM boost, buck-boost converters
Id (t)
IL,peak(t)
D3Tsw
D1Tsw
D2Tsw
Tsw
When D1 increases, [D1, D2] stays constant but D3 shrinks

The triangle is simply shifted to the right by d1
Id (t)
IL,peak(t)
D3Tsw
d1
t
D1Tsw
D2Tsw
Tsw
The refueling time of the capacitor is delayed and a drop occurs

7.00
340m
5.00
300m
3.00
1.00
-1.00
vduty in volts
Plot1
i(b2), i(b2)#a in amperes
If D increases, the diode current is delayed by d1

D(t)
Id(t)
260m
220m
d1
180m
2.02m
2.04m
3
2
2.06m
time in seconds
2.09m
2.11m
7.05
Plot3
vout in volts
1
6.95
6.85
6.75
Vout(t)
6.65
1.85m
1.99m
2.13m
time in seconds
2.27m
Plot2
vout in volts
7.05
2.41m
Vout(t)
6.95
6.85
1
6.75
6.65
2.02m
2.04m
2.06m
time in seconds
2.09m
2.11m
A Large-Signal Model is Available

Averaged models can predict the DCM RHPZ
L1
75u
10.0V
11
15.0V
Vin
10V
Vout
PWM switch VM
10.0V
vout
(
(
)
)
1
Cout RESR
s z2 =
1 + s sz1 (1 s sz 2 )
vout ( s )
= Hd
1 + s s p1 (1 + s s p 2 )
d (s)
R10
150m
15.0V
X3
PWMVM
L = 75u
Fs = 100k
R11
150
16
C5
1m
vout
sz1 =
Rload
M 2L
2M 1
1
11 M
s p2 = 2 Fsw
s p1 =
M 1 Cout RESR
D
R1
50k
2.50V
5
LoL
1kH 278mV
278mV
1
Hd =
8
6
CoL
1kF
0V
10
V1x
AC = 1
Verr
X2
AMPSIMP
V2
2.5
R3
10k
2Vout M 1
D 2M 1
Merci
Vatch!
The Model Predicts it!

Averaged models can predict the DCM RHPZ
H d = 28.75 dB
180 40.0
f z1 = 1.06 kHz
28.6 dB
f z2 = 141 kHz
90.0 20.0
f p1 = 4.2 Hz
fp1
0
f p2 = 47.1 kHz
fz2
-45
-90.0-20.0
fz1
fp2
8
-180 -40.0
10
4.2 Hz
100
1 kHz
10k
100k
47 kHz 141 kHz
1Meg
Going to Variable Frequency

More converters are using variable-frequency operation
This is known as Quasi-Square Wave Resonant mode: QR
Valley switching ensures extremely low capacitive losses
DCM operation saves losses on the secondary diode
Easier synchronous rectification
The Right Half-Plane Zero is pushed to high frequencies
Smooth signals
I D (t )
Less noise
VDS ( t )
Low CV losses
Id (t )
VDS ( t )
What is the Principle of Operation?

The drain-source signal is made of peaks and valleys
A valley presence means:
The drain is at a minimum level, capacitors are naturally
discharged
The converter is operating in the discontinuous conduction
V
mode
480
360
Vin
valley
240
120
toff
ton
DT
VDS ( t )
0
2.061m
2.064m
2.066m
2.069m
2.071m
A QR Circuit Does not Need a Clock

The system is a self-oscillating current-mode converter
Vbulk
Np:Ns
Demag
detector
+
- 65 mV
Lp
.
.
.
Q
Q
R
+
Rpullup
FB
GFB
CTR
Cout
Resr
Vdd
Vout
Rsense
Rload
A Winding is Used to Detect Core Reset

When the flux returns to zero, the aux. voltage drops
Discontinuous Mode is always maintained
Vbulk
Core is
reset
800
.
delay
400
200
I Lp ( t )
Vaux
VDS ( t )
600
d
= N
dt
delay
10 400m
0
-10 -400m
-20 -800m
=0
2.251m
2.255m
set
Vaux ( t )
I Lp ( t )
20 800m
2.260m
2.264m
2.269m
The Frequency Linearly Changes

As the peak current and the on-slope vary, Tsw changes
I Lp ( t )
I peak ,max
Son , HL = Vin , HL Lp
Son , LL = Vin, LL L p
P1
P2
I peak ,max
ton, HL
Soff = (Vout + V f
NL p
ton , LL
Tsw, HL
Tsw, LL
Soff = V f NL p
low rms currents in the MOSFET (weak stress)
Tsw
Excellent behavior in short-circuit conditions!

The Excursion Can be Quite Large

In heavy load low-line conditions, Fsw decreases
In light-load and high-line operations, Fsw can go very high
Fsw
( kHz )
80
3.4
70
3.2
I peak
60
(A)
50
40
3
2.8
2.6
30
100
200
300
Vin ( V )
400
2.4
100
200
Vin ( V )
EMI and switching losses are at stake as Fsw goes up

Standby power obviously suffers from this condition
300
400
In a Bounded System Discrete Jumps

As the load gets lighter, the frequency goes to the sky
Modern controllers fold the frequency back with a VCO
Problem, the only places to re-start are valleys: discrete jumps
Output
current
New Controllers Lock in the Valleys
Fsw (Hz)
To prevent the noise, the NCP1380 locks the valley

The current is allowed to move within a certain limit
When it exceeds this limit, the controller selects a new valley
As the load gets lighter, a VCO takes over and reduce Fsw
110
810
610
VCO
mode
rd versus
4th 3Fsw
2ndPout at VINmin 1st
4th
410
3rd
Pout decreases
Pout increases
20
40
Pout
, ,(W)
,
1st
VCO
mode
210
2nd
60
NCP1379/1380
Course Agenda
What is The Problem?

A converter is designed to operate on wide mains 85 to 265 V
rms
It can deliver a maximum power before protection trips
The maximum power delivered at high line is larger than that at
low line
85 V rms to 265 V rms
Increase load
until protection
trip.
What Does the Standard Say?

There is a test called Limited Power Source, LPS
The maximum power the converter can deliver must be
clamped
If clamped, the manufacturer can use inferior fire proofing
materials Output Voltage
Output Current
Apparent Power
Vout ( V)
Iout ( A)
S ( VA)
Vrms
Vdc
20
20 < Vout 30
20
20 < Vout 30
20 < Vout 60
5 Vout
8
150 Vout
100
100
19-V adapter, Iout,max = 5 A

IEC950 safety standard
Why the Power Runs Away in a Flyback?

I peak = I peak ,max +
The inductor
current slope
increases at high
line.
The controller
takes time to react
to an overcurrent
situation.
The inductor
current keeps
growing until the
MOSFET turns off.
The overshoot is
larger at higher
slopes (High Vin)
I peak , HL
I peak ,max
Vin ,max
Lp
t prop
0.8 Rsense
S=
I Lp ( t )
CSout ( t )
Vin
Lp
High
line
I peak , LL
PWM is reset
Low
line
tdel
Depends on
drive capability
and MOSFET
QG
VGS ( t )
t prop
The Effect in a DCM Converter

A flyback converter operated in DCM obeys the formula:
I ( Lp )
1
Pout = L p I peak ,max 2 Fsw
2
Primary Max. peak
inductor current in
fault
I peak ,max
Switching Converter
frequency efficiency
As Lp and Fsw are fixed, Ipeak,max changes with line input

I peak ,max, LL
Low line
I peak
I peak ,max, HL
Vsense Vin , LL
=
+
t prop
Rsense
Lp
Vin, HL Vin, LL
L pVsense
+ Vin, LL
t prop Rsense
I peak ,max, HL
High line
(1.13)
= 1.28
Vsense Vin , HL
=
+
t prop
Rsense
Lp
A 13.5% overshoot translates

in a 28% power increase
( is considered constant over the range)
The Power Increases at High Line

Lp = 250 H, Vsense = 1 V, tprop = 350 ns, Vin,LL= 120, Vin,HL = 370 V, Rsense =
0.33 , Fsw = 65 kHz
65
60
Pout ( W )
63 W
Pout = 17 W
55
50
46 W
45
100
= 85%
= 89%
200
300
400
Vin ( V )
In this example, the converter stays DCM over the whole input
range.
How to Compensate the Runaway?

How do we compensate this excess of power?
we reduce the maximum peak current at high
line
Ithis is called Over Power Protection OPP
I
peak
I peak ,max = f (Vin )
I peak ,max
peak
I peak , LL
I peak , HL
Vin
LL
Vin
HL
LL
HL
How to calculate the compensated high-line current?

Equate low-line power with high-line power and solve
for Ipeak
Pout ,max, HL =
L p I peak ,max, HL Fsw HL

2
Solve for Ipeak

Reducing the Peak Current

The final inductor peak current must equal:
I peak ,max, HL =
2 Pout ,max, LL
L p Fsw HL
You must subtract the prop. delay to obtain the controller

setpoint
Vin , HL
Vsense
= I peak ,max, HL
t prop
Rsense
Lp
The amplitude of the sensed voltage must reduce by:
V = Vsense
Vin , HL
I peak ,max, HL
t prop Rsense
Lp
For What Final Result?

Thanks to the OPP, the power stays under control
70
63 W
60
Pout ( W )
50
46 W
40
100
Pout = 4 W
46 W
42 W
200
300
Vin ( V )
400
The CCM Case is a Different Picture

In DCM, the valley current is zero, the stored energy is:
1
E = L p I peak ,max 2
2
The peak current runaway, alone, affects the transmitted power
In CCM, the valley current changes the formula:
1
E = L p ( I peak ,max 2 I valley 2 )
2
I (L )
p
I peak ,max
I valley
t
The Converter Changes its Operating Mode

In fault mode, the converter operates in deep CCM at low line
As the input voltage increases, the valley current decreases
I Lp ( t )
I p ,max, LL
Maximum current in fault
(V
out
ELL
+ Vf
NLp
Vin ,min
Lp
I p , valley , LL
Low line
ton , LL
I p ,max, HL
Maximum current in fault
(V
out
Vin ,max
EHL
+ Vf
NLp
Lp
High line
I p ,valley , HL
EHL > ELL

ton , HL
Computing the Transmitted Power in CCM

First, we write the ton and toff equations in
CCM
I Lp ( t )
I peak
(V
out
+ Vf
NLp
Vin ,min
Lp
I valley
t
toff
ton
Tsw
I peak = I valley
(1)
V
+ in ton
Lp
I valley = I peak
V
(
(2)
out
+ Vf
NL p
)t
off
Tsw = ton + toff

(3)
Solving for the Valley Current

By combining the 3 equations, we have:
ton =
L p ( I peak I valley )
Vin
toff = Tsw ton = Tsw
L p ( I peak I valley )
Vin
Replace toff in
(2):
V f + Vout )( I valley L p I peak L p + TswVin )
(
I valley = I peak
L p NVin
Solve for Ivalley:
I valley = I peak
TswVin (V f + Vout )
L p (V f + Vout + NVin )
Max fault
current
LL or HL
I peak ,max
I L = I peak I valley
V
V
= sense + in t prop
Rsense L p
I L =
TswVin (V f + Vout )
L p (V f + Vout + NVin )
Inductor ripple
current
Identifying the Operating Mode

Having the ripple on hand, we can confirm the
mode:
N I L
I L
Lp
ton =
L p toff =
I Lp ( t )
Vin
(Vout + V f )
ton + toff = Tsw
I peak
CCM
I valley > 0
ton + toff = Tsw
I valley = 0
ton + toff < Tsw
I valley
I peak
BCM
ton
I peak
DCM
DT
DT = Tsw toff ton
ton
ton
Evaluating the Power in CCM

Lp = 600 H, Vsense = 1 V, tprop = 350 ns, Vin,LL= 120, Vin,HL = 370 V, Rsense = 0.33 , Fsw = 65 kHz
1
L p ( I peak ,max, LL 2 I valley , LL 2 ) Fsw LL 76 W
2
1
= Lp ( I peak ,max, HL 2 I valley , HL 2 ) Fsw HL = 104 W
2
Pmax, LL =
Pmax, HL
110
100
Pout ( W )
Pout = 24 W
90
80
70
100
200
Vin ( V )
300
400
Reducing the Peak Current at High Line

If we lower the peak at high line, the ripple remains the
same
I Lp ( t )
I L
I peak
I LCMP
I peak CMP
I valley
I valleyCMP
t
toff
ton
Tsw
We can re-write the flyback power formula to include the

ripple
2
1
2
Pmax, HL = Lp I peak ,max, HL ( I peak ,max, HL I L , HL ) Fsw HL
2
0 in DCM
We Want to Limit the High-Line Power

We can force the high-line power to match that of low
line
2
1
2
Pmax, LL = L p I peak ,max, HL ( I peak ,max, HL I L , HL ) Fsw HL
2
From there, we can extract the compensated peak current
value
Fsw L p HL I L , HL 2 + 2 Pmax, LL
I peak ,max, HL =
2 Fsw Lp HL I L , HL
As this is the new setpoint, prop. delay contribution must be

removed
Vin , HL
V = Vsense I peak ,max, HL
t prop Rsense
Lp
After compensation, the peak current setpoint at high line

becomes
Vsense V Vin, HL
+
I peak ,max, HL =
t prop
Rsense
Lp
What is the Final Result?

The high line power now respects the LPS limit
110
104 W
100
Pout ( W )
90
80
75 W
76 W
Pout = 6 W
70
70 W
60
100
200
300
Vin ( V )
400
What Practical Solutions?

There are several possibilities to reduce the peak
current
1. Offset the current sense signal in the CS pin:
I ( Lp )
I peak ,max
I L , LL
I L , HL
easy to do
affects the no-load
stand-by power
High line
affects light-load
efficiency
2. Reduce the peak limit as Vin increases

I ( Lp )
I peak ,max, LL
I L , LL
implemented at IC level
I L , HL
I peak ,max, HL
High line
t
does not affect the noload stand-by power

does not affect lightload efficiency
Build an Offset on the CS Pin

This offset must be proportional to the input voltage
Vbulk
Vbulk
ROPP1
.
.
Vcc
.
rotated
Q1
DRV
ROPP 2
C1
.
Q1
DRV
ROPP1
CS
R1
CS
Rsense
C1
R1
Rsense
Both options degrade light-load operation because of the CS

offset
OPP Implementation in the NCP1250

The NCP1250 implement a non-dissipative OPP
circuitry
800 mV
on
600 mV
off
PWM
reset
off
0 300-ns
blank
0
on
-200 mV
OPP
CS
1
ROPPU
Aux.
ROPPL
0.8 V
4
0.8 V
The auxiliary swings to NVin and reduces the setpoint

OPP
Checking the Results

Let us check on a real 19-V adapter built with the
NCP1250
Lp = 600 H, Vsense = 1 V, tprop = 350 ns, Vin,LL= 120, Vin,HL = 370 V
Rsense = 0.33 , Fsw = 65 kHz, Vclamp = 90 V, ll = 2.2 H, N = 0.25
Without any OPP compensation, we have:

I out ,max, LL = 4.1A
I out ,max, HL = 5.7 A
Once OPP has been implemented:

Pout , LL 72 W so I out , LL = 3.8 A
Pout , HL 78 W so I out , HL = 4.1A
Course Agenda
Small-Signal Analysis
Loop instability is a common issue in production
Due to time pressure, designers often use trial and
error
no indication on design margins
offenders are ignored, robustness is at stake
T (s)
G(s)
H(s)
T ( s )
10
100
1k
10k
100k
Understand and counteract their variations when

building G(s)
There are Two Options

Analytical analysis of the power stage:
best to see where the offenders are hidden (ESR, opto pole
etc.)
equations are complex but litterature abounds
transfer function are for DCM or CCM
difficult to predict transient response
SPICE models:
easy-to-implement averaged models
can work in ac or transient mode
easily transition between CCM and DCM
do not explictly disclose the position of poles and zeros
A measurement on the bench is

mandatory, whatever you choose!
Analytical Analysis
You must first characterize the "plant" transfer function
what are your power stage ac characteristics?
Plant
Vref
G(s)
d(s)
vc(s)
H(s)
+
+
Compensator
Vout ( s )
H (s) =
vc ( s )
Current-mode
control
Vout ( s )
H (s) =
d (s)
Voltage-mode
control
Vin ( s ) GVin ( s )
I out ( s ) Z out ( s )
Vout ( s )
How do we Stabilize a Converter?

We need a high gain at dc for a low static error
We want a sufficiently high crossover frequency for response speed
Shape the compensator G(s) to build phase and gain margins!
T (s)
fc = 6.5 kHz
0 - 0 dB
T ( s )
GM = 67 dB
-88
m = 92
-180
10
T ( s ) = 67 dB
100
1k
10k
100k
1Meg
How much phase margin to chose?

a Q factor of 0.5 (critical response) implies a m of 76
a 45 m corresponds to a Q of 1.2: oscillatory response!
1.80
Q < 0.5 over damping

Q = 0.5 critical damping
Q > 0.5 under damping
Q=5
Q=1
1.40
10
7.5
Q = 0.707
Asymptotically stable
1.00
600m
Q = 0.5 Fast response

and no overshoot!
200m
2.5
15.0u
0
25.0u
35.0u
76
Q = 0.5
Q = 0.1
5.00u
45.0u
25
50
75
100
phase margin depends on the needed response: fast, no overshoot

good practice is to shoot for 60and make sure m always > 45
What Compensator Types do we Need?

There are basically 3 compensator types:
type 1, 1 pole at the origin, no phase boost
type 2, 1 pole at the origin, 1 zero, 1 pole. Phase boost up to 90
type 3, 1 pole at the origin, 1 zero pair, 1 pole pair. Boost up to 180
10
20
270
270
G ( s )
50
100 200
500
1k
10
100
1k
10k
100k
10
boost
boost
G ( s ) = 270
1
G (s)
G (s)
G (s)
G ( s )
100
1k
10k
Type 1
Type 2
Type 3
Boost = 0
Boost up to 90
Boost up to 180
100k
Fixed-Frequency Current-Mode
First, check the operating mode, CCM or DCM?
Lp ,crit
Rload Vin
=
2 Fsw N 2 V + Vout
in
N
Lp > Lp,crit ? Yes, CCM else DCM
Assume CCM, compute the dutyratio:

Compute M and L
D=
Vout
Vout + NVin
2 Lp N 2
Vout
: =
M
L =
NVin
Rload Tsw
Evaluate the dc gain and poles/zeros positions:

G0 =
Rload
1
RsenseGFB N (1 D )2
+ 2M + 1
Compute the poles/zeros positions:
f z1 =
1
2 RESR Cout
f z2
(1 D )
=
Rload
2 DL p N 2
f p1 =
(1 D )
+1+ D
L
2 Rload Cout
Check the quality coefficient at Fsw/2

Sn =
Vin
Rsense
Lp
Se = ( M c 1) S n
Qp =
1 = no compensation
1
( M c (1 D ) 0.5 )
Apply to formula to plot the ac response:
s
s
+
1
1
1
z1
z2
H ( s ) G0
s
s2
s
+ 2
1+
1 +
rd
n Q p n
3 order
p1
Mc = 1+
Se
Sn
n =
Tsw
Extract the magnitude and the argument definitions
H(f)
2
2
f
f
1+
1 +
f
f
z1
z2
= 20 log10 G0
1
+
f p
1
1
2
f 2 f
1
+
f n f n Q p
f
f
f
f
1
1
1
arg H ( f ) = tan 1 tan 1
tan
tan
2
fz
fz
fp
fQ
1
2
1
n p 1 f

fn
RHPZ
Plot them with Mathcad for instance.
Extract the information at the selected crossover frequency
20
H (s)
100
10
dB
Sub-harmonic
oscillations
10
H ( s )
100
Damp poles
with Se
20
10
100
H ( 3kHz ) = 16.3dB
10
10
10
Hz
arg H ( 3 kHz ) = 23
Low line, high power
The compensation strategy is the following:
compensate the gain loss at fc so that:
G ( 3kHz ) = +16.3dB
evaluate the boost in phase at fc to get phase 70 margin:
Boost = PM argH ( f c ) 90 = 3.15

Boost = 0 select type 1 origin pole
Boost < 90 select type 2 origin pole, 1 pole, 1 zero
k-factor can be used to place the pole and the zero
boost
k = tan
+ 45 1
2
poles and zeros are coincident
f pk 1 = kf c = 1 3k = 3 kHz
f c 3k
f zk 1 =
=
= 3 kHz
k
1
Plot the compensator transfer function
80
dB
180
G (s)
60
200
40
220
20
0
20
10
240
G ( s )
10 3
100
2
f
1+
f zk 1
G ( f ) = 20 log10 G
2
f
f
1+
f p
f pk 0
k1
260
10 4
10 5
Hz
f
f 180
boost = tan 1
tan 1
f
f zk
pk
1
Plot the loop gain transfer function G(s)H(s) and check the margins
100
T (s)
100
50
fc = 3 kHz
dB
200
T ( s )
360
50
10
100
10 3
m = 70
10 4
300
10 5
Hz
Sweep ESR, Cout, Rload and verify the results

Low line, high power
In case the converter transitions to DCM, update the equation!
20
H (s)
s
50
1 +
z1
H ( s ) = G0
s
0
1 +
p1
10
0
10
20
30
10
50
H ( s )
100
103
s
1
z2
s
1+
p
2
104
105
Yes, analytical analysis is long and tedious.

But, it teaches where the threats are and how to deal with!
Variable-Frequency Current-Mode
Observing the waveforms helps us to derive an average model
Ia (t )
Ic (t )
I peak
I peak
Ic (t )
Tsw
Tsw
dTsw
It gives birth to a large-signal model

2 Ri Pout (Vout + NVin )
Ia
Ic
Vc =
c
a
VinVout
d1.Ic
Vc/(2*Ri)
p
Sense
resistor
Vc Lp 1
N
Tsw =
+
Ri Vin Vout
2P R
d1 = out i
VcVin
I peak
2
Linearization is needed to get a small-signal model
Implement this small-signal model in a flyback configuration
v(c,p).kcp
ic.kic
X5
XFMR
RATIO = N
v(a,c).kac
Vin
Vout
Resr
vc.kc
ic
Rload
Cout
Lp
http://cbasso.pagesperso-orange.fr/Spice.htm
Derive the transfer function and isolate poles and zeros
s
s
1
+
1
vout ( s )
s
s
z1
z2
= G0
vc ( s )
s
1 +
1st order
s
p1
f p1 =
2 Rload Cout
1
f z1 =
2 RESR Cout
Rload Div
G0 =
2V
2 NRi out + 1
NVin
f z2 =
Then plot the function
2M + 1
M +1
Rload
1
2 N 2 Lp M (1 + M )
H ( s )
15
dB
20
40
10
60
5
H (s)
0
1
10
100
Tailor G(s) to get

the desired fc
80
3
10
10
100
5
10
Hz
vc
a
Vout=19
16
116mV
duty-cycle
DC
parameters
340V
Vin
340
AC = 0
-78.4V
D1A
mbr20200ctp
R1
20m
L1
2.2u
vint
19.0V
19.0V
19.6V
19.0V
20
R10
15m
0V
13
X9
PWMCM
L = Lp
Fs = Fs
Ri = Rsense
Se = Se
Lp=600u
Fs=70k
Rsense=0.5
Se=0
18
Ibridge=250u
Rlower=2.5/Ibridge
Rupper=(Vout-2.5)/Ibridge
X2x
XFMR
RATIO = -250m
PWM switch CM
Use a SPICE Model to Stabilize the Converter
470mV
6
27
C5
2m
B1
Voltage
fc=1k
pm=60
Gfc=-21
pfc=-88
Rload
20
19.0V
1
(V(err)-1.2)/3 > 1 ?
1 : (V(err)-1.2)/3
vout
R15
85m
19.0V
Lp
{Lp}
vout
C1
220u
Vdd
5
5.00V
9
G=10^(-Gfc/20)
boost=pm-(pfc)-90
pi=3.14159
K=tan((boost/2+45)*pi/180)
vout
vint
Rled
{RLED}
18.8V
R2
47k
Fzero=fc/k
Fpole=k*fc
2.50V
R3
47k
2.61V
Rpulldown=4.7k
RLED=CTR*Rpulldown/G
Czero=1/(2*pi*Fzero*Rupper)
Cpole=1/(2*pi*Fpole*Rpulldown)
LoL
1kH
2.39V
19
err
Rupper2
{Rupper}
Verr
X3
OP384X1
X7
Optocoupler
Cpole = 1/(6.28*pole*pullup)
CTR = CTR
2.39V
5
UC384X
gnd
2V5
17.6V
2.39V
CTR=0.9
Pole=15k
15
CoL
1kF
0V
Cpole2
{Cpole}
10
2.49V
11
14
Automate the
compensation!
Czero1
{Czero}
X10
TL431_G
Vstim
AC = 1
R4
{Rpulldown}
Rlower2
{Rlower}
Cannot be
beaten for
simplicity
and speed!
Unveil the Transfer Function in a Second

dB
40.0
H ( s )
180
20.0 90.0
0
H (s)
-20.0 -90.0
-40.0 -180
Power stage gain
dB
T (s)
60.0 180
30.0 90.0
0
T ( s )
fc
-30.0 -90.0
-60.0 -180
Loop gain
10
100
1k
10k
100k
Course Agenda
How is regulation performed?

Text books only describe op amps in compensators
Vout
Verr
The market reality is different: the TL431 rules!

Vout
Im the
law!
Verr
TL431
optocoupler
The TL431 Programmable Zener

The TL431 is the most popular choice in nowadays designs
It associates an open-collector op amp and a reference voltage
The internal circuitry is self-supplied from the cathode current
When the R node exceeds 2.5 V, it sinks current from its cathode
K
R
K
R
TL431A
A
2.5V
R
A
K
The TL431 is a shunt regulator

A Rabbit and a (French) Snail

The TL431 lends itself very well to optocoupler control
Vdd
Slow lane
Fast lane
Vout
Vout
R pullup
RLED
RLED
R1
I1
VFB
I bias =
I LED
Rbias
C2
Rbias
Vf 1 V
I1
C1
TL431
Rlower
Vmin = 2.5 V
dc representation
RLED must leave enough headroom over the TL431: upper limit!
1V
Rbias
Understanding the Fast Lane Drawback

This LED resistor is a design limiting factor in low output voltages:
RLED ,max
Vout V f VTL 431,min

Vdd VCE , sat + I bias CTR min R pullup
R pullup CTR min
When the capacitor C1 is a short-circuit, RLED fixes the fast lane gain
Vout ( s )
Vdd
RLED
R1
VFB ( s ) = CTR R pullup I1
I1
I1 =
R pullup
VFB ( s )
Ic
0V
in ac
Rlower
Vout ( s )
RLED
R pullup
VFB ( s )
= CTR
Vout ( s )
RLED
This resistor plays a role in dc too!

The Static Gain Limit

Let us assume the following design:
Vout = 5 V
Vf = 1 V
RLED ,max
5 1 2.5
20k 0.3
4.8 0.3 + 1m 0.3 20k
VTL 431,min = 2.5 V

Vdd = 4.8 V
RLED ,max 857
VCE , sat = 300 mV

I bias = 1 mA
CTR min = 0.3
R pullup = 20 k
G0 > CTR
R pullup
RLED
> 0.3
20
> 7 or 17 dB
0.857
In designs where RLED fixes the gain, G0 cannot be below 17 dB

You cannot amplify by less than 17 dB
Forbidden Compensation Areas

You must identify the areas where compensation is possible
dB
40.0
20.0
90.0
-17 dB
-20.0 -90.0
-40.0
Not ok
180
H (s)
f c > 500 Hz
Requires
less
than 17 dB
of gain
arg H ( s )
ok
-180
10
Requires
17 dB
or more
100
500
1k
10k
100k
Injecting Bias Current

Make sure enough current always biases the TL431
If not, open-loop gain suffers a 10-dB difference can be observed!
> 10-dB difference
Ibias = 1.3 mA
Easy
solution
Ibias
Rbias
Ibias = 300 A
Rbias
1
=
= 1 k
1m
Small-Signal Analysis
The TL431 is an open-collector op amp with a reference voltage
Neglecting the LED dynamic resistance, we have:
Vout ( s )
RLED
I1
R1
C1
I1 ( s ) =
Vout ( s ) Vop ( s )
1
sC1
1
Vop ( s ) = Vout ( s )
= Vout ( s )
Rupper
sRupper C1
I1 ( s )
1 1 + sRupper C1
=
Vout ( s ) RLED sRupper C1
We know that:
Vop ( s )
RLED
Rlower
VFB ( s )
VFB ( s ) = CTR R pullup I1
R pullup CTR 1 + sRupper C1

=
Vout ( s )
RLED
sR
C
upper 1
Creating a High-Frequency Pole

In the previous equation we have:
a static gain G0 = CTR
R pullup
RLED
a 0-dB origin pole frequency p =

o
a zero z =
1
C1 Rupper
Rupper C1
We are missing a pole for the type 2!

Vdd
Type 2 transfer function
R pullup
VFB ( s )
C2
Add a cap. from

collector to ground
VFB ( s )
R pullup CTR
1 + sRupper C1
=
Vout ( s )
RLED
sRupper C1 (1 + sR pullup C2 )
Understanding the Optocoupler Pole

The optocoupler also features a parasitic capacitor
it comes in parallel with C2 and must be accounted for
Vout(s)
Vdd
Rpullup
VFB(s)
FB
C2 = C || Copto
Copto
e
optocoupler
Extracting the Pole

The optocoupler must be characterized to know where its pole is
Cdc
10uF
Ic
Rled
20k
O ( s )
Rpullup
20k
Rbias
VFB
Vdd
5
X1
SFH615A-4
Vbias
Vac
IF
O (s)
-3 dB
4k
Adjust Vbias to have VFB at 2-3 V to be in linear region, then ac-sweep

The pole in this example is found at 4 kHz
Copto =
1
2 R pullup f pole
1
2 nF
6.28 20k 4k
Another design
constraint!
The TL431 in a Type 1 Compensator

To make a type 1 (origin pole only) neutralize the zero and the pole
VFB ( s )
R pullup CTR
1 + sRupper C1
=
Vout ( s )
RLED
sRupper C1 (1 + sR pullup C2 )
sRupper C1 = sR pullup C2
CTR
po =
C2 RLED
C1 =
R pullup
Rupper
substitute
C2
p =
o
1
Rupper RLED
R pullup CTR
CTR
C2 =
2 f po RLED
Once neutralized, you are left with an integrator

1
G (s) =
s
po
| G ( f c ) |=
f po
fc
f po = G fc f c
C2 =
CTR
2 G fc f c RLED
C1
A Type 1 Design Example

We want a 5-dB gain at 5 kHz to stabilize the 5-V converter
Vout = 5 V
Vf = 1 V
VTL 431,min = 2.5 V
Vdd = 4.8 V
VCE , sat = 300 mV
RLED ,max 857
Apply 15%
margin
RLED = 728
I bias = 1 mA
CTR min = 0.3
R pullup = 20 k
G fc = 10
5
20
= 1.77
f c = 5 kHz
C2 =
CTR
0.3
=
7.4 nF
2 G fc f c RLED 6.28 1.77 5k 728
Copto = 2 nF
C = 7.4n 2n = 5.4 nF
C1 =
R pullup
Rupper
C2 14.7 nF
Simulation of the Type 1

SPICE can simulate the design automate elements calculations
parameters
Vout=5
Vf=1
Vref=2.5
VCEsat=300m
Vdd=4.8
Ibias=1m
A=Vout-Vf-Vref
B=Vdd-VCEsat+Ibias*CTR*Rpullup
Rmax=(A/B)*Rpullup*CTR
Vdd
{Vdd}
4.80V
6
Rpullup
{Rpullup}
Rupper=(Vout-2.5)/250u
fc=5k
Gfc=-5
VFB
RLED
{RLED}
3.97V
4
Rpullup=20k
Cpole
{Cpole}
RLED=Rmax*0.85
R2
{Rupper}
2
2.50V
R5
100m
10
C3
1k
R6
1k
C1
{C1}
2.96V
4.99V
err
4.99V
Fpo=G*fc
4.99V
7
2.50V
2.50V
G=10^(-Gfc/20)
pi=3.14159
L1
1k
4.99V
E1
-1k
0V
B1
Voltage
V(err)<0 ?
0 : V(err)
V2
2.5
V3
AC = 1
C1=Cpole1*Rpullup/Rupper
X2
Cpole1=CTR/(2*pi*Fpo*RLED)
Optocoupler
Cpole=Cpole1-Copto
Cpole = Copto
CTR = CTR
Fopto=4k
Copto=1/(2*pi*Fopto*Rpullup)
CTR = 0.3
X1
TL431_G
R3
10k
Automatic bias
point selection
Type 1 Simulation Results

The pullup resistor is 1 k and the target now reaches 5 dB
dB
20.0
G (s)
10.0
5 dB
0
-10.0
-20.0
270
180
arg G ( s )
90.0
0
-90.0
100
200
500
1k
2k
5k
10k
20k
50k
100k
The TL431 in a Type 2 Compensator

Our first equation was already a type-2 definition, we are all set!
Vdd
Vout
R pullup
RLED
R1
VFB
z =
1
Rbias
C2
G0 = CTR
C1
p =
1
TL431
Rlower
R pullup
RLED
1
R1C1
1
R pullup C2
Just make sure the optocoupler contribution is involved

Deriving Component Values for the Type 2

You need to provide a 15-dB gain at 5 kHz with a 50boost
f p = tan ( boost ) + tan 2 ( boost ) + 1 f c = 2.74 5k = 13.7 kHz
f z = fc
f p = 25k 13.7k 1.8 kHz
G0 = CTR
R pullup
RLED
= 1015 20 = 5.62
With a 250-A bridge current, the divider resistor is made of:

Rlower = 2.5 250u = 10 k
R1 = (12 2.5 ) 250u = 38 k
The pole and zero respectively depend on Rpullup and R1:

C2 = 1 2 f p R pullup = 581 pF
C1 = 1 2 f z R1 = 2.3 nF
The LED resistor depends on the needed mid-band gain:

RLED =
R pullup CTR
G0
= 1.06 k
ok
RLED ,max 4.85 k
Checking the Optocoupler Contribution

The optocoupler is still at a 4-kHz frequency:
C pole 2 nF
Already above!
Type 2 pole capacitor calculation requires a 581-pF cap.!

The bandwidth cannot be reached, reduce fc!
For noise purposes, we want a minimum of 100 pF for C
With a total capacitance of 2.1 nF, the highest pole can be:
f pole =
1
1
=
= 3.8 kHz
2 R pullup C 6.28 20k 2.1n
For a 50phase boost and a 3.8-kHz pole, the crosso ver must be:
fc =
fp
tan ( boost ) + tan ( boost ) + 1
1.4 kHz
Placing the Zero in the Transfer Function

The zero is then simply obtained:
fc 2
fz =
= 516 Hz
fp
We can re-derive the component values and check they are ok

C2 = 1 2 f p R pullup = 2.1 nF
C1 = 1 2 f z R1 = 8.1 nF
Given the 2-nF optocoupler capacitor, we just add 100 pF

In this example, RLED,max is 4.85 k
G0 > CTR
R pullup
RLED
> 0.3
20
> 1.2 or 1.8 dB
4.85
You cannot use this type 2 if an attenuation is required at fc!
TL431 type 2 Design Example

The 1-dB gain difference is linked to Rd and the bias current
dB
30.0
G (s)
20.0
10.0
0
14 dB @ 1.4 kHz
-10.0
140
arg G ( s )
130
120
50
110
100
10
100
1k
10k
100k
Design Example 1 a Single-Stage PFC

The single-stage PFC is often used in LED applications
It combines isolation, current-regulation and power factor correction
Here, a constant on-time BCM controler, the NCL30000, is used
141V
X2
XFMR
RATIO = -250m
Vout
Iout = 2.4 A
52.5V
-210V
8.74V
7
vc
154mV
X1
PWMBCMVM
L=L
GAIN
Ip
PWM switch BCM
3.09V
V1
{Vrms*1.414}
Fsw (kHz)
Fsw
Ip
68.4V
Dc
1 V = 1 s
19
duty-cycle
598mV
R1
100m
0V
R2
50m
X5
K = Gpwm
GAIN
D4
1N965
52.5V
R7
65k
26.9V
9
4
11
1.57V
22
L1
{L}
C5
0.1uF
C1
2.2mF
B1
Voltage
V(errac)-0.6
Rsense
1.24V
0.5
Vsense
23
parameters
Vdd
15.1V
{Vdd}
Vrms=100
L=400u
1.25 V
1.24V
ILED
14
R5
{RLED}
5.00V
On-time
selection
VFB
errac
LoL
1k
2.17V
CoL
1k
20
AC = 1
V3
12.2V
17
16
X4
Optocoupler
Cpole = Copto
CTR = CTR
C2
{C2}
Ac out
R6
{Rpullup}
2.17V
29
0V
ac in
2.17V
10
R4
{Rupper}
18
Ct=1.5n
Icharge=270u
Gpwm=(Ct/Icharge)*1Meg
50 V
2 A string
11.1V
13
1.24V
15
X3
TLV431
R9
{R2}
C4
{C1}
28
1.24V
Average simulation

Once the converter elements are known, ac-sweep the circuit
Select a crossover low enough to reject the ripple, e.g. 20 Hz
dB
8.00
4.00
H (s)
-2.5 dB
20 Hz
0
-4.00
-8.00
80.0
40.0
arg H ( s )
-11
0
-40.0
-80.0
1
10
20
50
100
200
500
1k

Given the low phase lag, a type 1 can be chosen
Use the type 2 with fast lane removal where fp and fz are coincident
dB
20.0
Block the
fast lane
10.0
fc = 19 Hz
13
0.5
15 V
-10.0
3
-20.0
5V
10
6.1 k
11
ton
generation
T (s)
10 k
20 k
180
90.0
m = 90
586 nF 13.6 k
395 nF
-90.0
12
G (s)
-180
1
argT ( s )
2
10
20
50 100 200
500 1k

A transient simulation helps to test the system stability
6.00
4.00
2.2 A
2.00
I LED ( t )
0
-2.00
VFB ( t )
5.00
4.60
4.20
3.80
3.40
4.00
2.00
0
I in ( t )
-2.00
-4.00
20.0m
60.0m
100m
140m
180m
Vin = 100 V rms
Design Example 2 a DCM Flyback Converter

We want to stabilize a 20-W DCM adapter
Vin = 85 to 265 V rms, Vout = 12 V/1.7 A
Fsw = 65 kHz, Rpullup = 20 k
Optocoupler is SFH-615A, pole is at 6 kHz
Crossover target is 1 kHz
Selected controller: NCP1216
1.
2.
3.
4.
5.
Obtain a power stage open-loop Bode plot, H(s)

Look for gain and phase values at crossover
Compensate gain and build phase at crossover, G(s)
Run a loop gain analysis to check for margins, T(s)
Test transient responses in various conditions
Design Example 2 a DCM Flyback Converter

Capture a SPICE schematic with an averaged model
DC
vc
a
duty-cycle
389mV
90.0V
X2x
XFMR
RATIO = -166m
3
PWM switch CM
839mV
-76.1V
Vin
90
AC = 0
D1A
mbr20200ctp
12.0V
vout
12.6V
R10
20m
0V
X9
PWMCM
L = Lp
Fs = 65k
Ri = 0.7
Se = Se
13
L1
{Lp}
8
V(errP)/3 > 1 ?
1 : V(errP)/3
B1
Voltage
Coming from FB
Look for the bias points values: Vout = 12 V, ok
vout
12.0V
1
C5
3mF
Rload
7.2
Design Example 2: a DCM Flyback Converter

Observe the open-loop Bode plot and select fc: 1 kHz
H (s)
dB
40.0
180
20.0
90.0
Phase at 1 kHz
-70
0
-20.0 -90.0
-40.0
arg H ( s )
-180
10
Magnitude at 1 kHz
-23 dB
100
1k
10k
100k
Design example 2: a DCM flyback converter

Apply k factor or other method, get fz and fp
fz = 3.5 kHz fp = 4.5 kHz
Vout(s)
Vdd
38 k
2 k
20 k
k factor
gave
C = 3.8 nF
FB
10 nF
2.5 nF
install
C2 = 3.8n 1.3n 2.5 nF
VFB(s)
10 k
Copto = 1.3nF
Design example 2: a DCM Flyback Converter

Check loop gain and watch phase margin at fc
4
dB
180
80.0
90.0
40.0
T (s)
argT ( s )
m = 60
0
-90.0 -40.0
Crossover
1 kHz
-180 -80.0
10
100
1k
10k
100k
Design Example 2: a DCM Flyback Converter

Sweep ESR values and check margins again
12.04
Vout(t)
High
line
12.00
11.96
11.92
100
mV
Low
line
11.88
200 mA to 2 A in 1 A/s
3.00m
9.00m
15.0m
21.0m
27.0m
No Time to Compute? Check EXCEL!

An automated spreadsheet does the calculations for you
Download a version from www.onsemi.com
Conclusion
The flyback converter hides several parasitic elements
Understanding where they hide and how they move is key!
Despite CM presence, QR designs gain in popularity
CM fixed-frequency is a 3rd-order type whereas QR is 1st order
TL431 lends itself well for compensation, watch the optocoupler!
SPICE eases and speed-up the design
Always check theoretical assumptions with bench measurement
Merci !
Thank you!
Xi-xie!

Chris Basso APEC Seminar 2011

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The Dark Side of Flyback

1 Chris Basso APEC 2011

2 Chris Basso APEC 2011

What is the Subject?

The Flyback, a Popular Structure

4 Chris Basso APEC 2011

The addition of a transformer brings:

Up or down scale Vin

5 Chris Basso APEC 2011

The Turn-on Event

PIV = Vin N + Vout

The current increases in the inductor in relationship to Vin and Lp

6 Chris Basso APEC 2011

Applying Volt-Second Balance, CCM

Apply volt-second balance

VDS ,off = Vin +

dc transfer function in CCM

Applying Volt-Second Balance, DCM

Apply volt-second balance

VDS ,off = Vin

8 Chris Basso APEC 2011

N no longer plays a role

Flyback, Typical Waveforms

V2 4 0 PULSE 0 5 0 10n 10n 3u 10u

It will run open loop for simplicity, Vout 8 V

9 Chris Basso APEC 2011

Flyback, Typical Waveforms, CCM

CCM flyback no parasitics

10 Chris Basso APEC 2011

Flyback, Typical Waveforms, DCM

DCM (core reset)

DCM flyback no parasitics

11 Chris Basso APEC 2011

Energy Transfer in CCM and DCM

Transmitted energy at Tsw

Power (W) is energy (J) averaged over time (s):

12 Chris Basso APEC 2011

13 Chris Basso APEC 2011

Considering Parasitic Elements

V2 4 0 PULSE 0 5 0 10n 10n 3u 10u

14 Chris Basso APEC 2011

Considering Parasitic Elements, CCM

CCM mode with parasitics

15 Chris Basso APEC 2011

Considering Parasitic Elements, DCM

DCM (core reset)

Diode blocks here

DCM mode with parasitics

16 Chris Basso APEC 2011

Who Are the Stray Elements?

The MOSFET COSS is a Non-Linear Device

CD0 is the cap. for VDS = V0

Since bias affects the capacitor value:

18 Chris Basso APEC 2011

As the Voltage Decreases, COSS Value Changes

The lost energy is smaller than with the non-linear variation!

19 Chris Basso APEC 2011

Using the Raw COSS is an Overkill

The classical equation gives:

The Leakage Inductance

Some induction lines couple in the air: leakage flux

21 Chris Basso APEC 2011

An Equivalent Transformer Model

22 Chris Basso APEC 2011