MOS analog design

D.K. Sharma
EE Department
IIT Bombay

1 Introduction
Modern IC technology has made it possible to put millions of transistors on a
single integrated circuit. This capability has been used to great effect in digital
circuits such as microprocessors, memories and various Application Specific Inte-
grated Circuits (ASICs). Indeed, such is the complexity of integrated circuits being
designed today, that one often talks of putting complete systems on a chip, rather
than designing a few function blocks. However full systems cannot, in general, be
exclusively digital. Analog function blocks are required at least at the input and
the output stage in order to interface with the world outside the chips. The analog
blocks at the input amplify signals and convert them to digital form. Once these
signals have been converted to digital form, complex digital functions can operate
on these and produce the desired results in digital form. These results then need
to be converted back to the analog form, in order to provide outputs which can be
used directly by the external world.
It is clear, therefore, that analog design has to complement digital IC design
in order to take full advantage of the power made available by semiconductor
technology. However, the skill required in designing analog circuits is much higher
than that needed for digital circuits. The requirements of stability, low noise
and low thermal drift are much more exacting in the case of analog circuits as
compared to digital circuits. Most digital circuits are inherently economic in power
consumption, because a device is either ‘ON’ (zero voltage) or ‘OFF’ (zero current).
This is not so in the case of analog circuits. Therefore, special care needs to be
taken in order to make an analog circuit economical in its use of power.
Analog design is, therefore, a challenging task. Unfortunately, it has not re-
ceived the same attention as digital design over the past few years. This is because
digital products such as microprocessors and memories have driven the Very Large
Scale Integrated Circuits (VLSI) markets up to now. As mixed signal products
such as communication chips come to center stage in the electronic market, the
need for analog and mixed signal design will be acutely felt. This course addresses
this need.
In this particular module, we shall see how simple building blocks used in
analog circuits are analyzed and designed.

1
2 Single Transistor Amplifier
2.1 DC gain
Consider the single transistor amplifier with
a current source load as shown in figure 1. A
I
d small signal input (vi ) is applied to its gate
v and the output is taken from the drain. The
o drain current of the n channel MOSFET is de-
v V
d pendent on its gate voltage (Vg ) as well as on
i Vg
its drain voltage (Vd ). Therefore, the change
in the drain current can be written as
∂Id ∂Id
Figure 1: A Single MOS transis- dId = dVg + dVd (1)
∂Vg ∂Vd
tor Amplifier
∂Id
By definition, ∂V g
= the transconductance (gm )
∂Id
of the transistor and ∂V d
= go , its output con-
ductance. Also, following small signal conventions, we can write differentials of Vg ,
Vd and Id as small case vg , vd , and id . We also notice that vg is the same as the
input signal vi and vd is the output of the amplifier, vo . Also, since the transistor
is fed by a current source, it does not permit any variation in the drain current.
Therefore, dId = 0. So,
0 = g m vi + g o vo (2)
Hence, we can write for the voltage gain (Ao ) of the stage,
vo gm
Ao = =− = −gm ro (3)
vi go
Where ro , the output resistance of the stage is defined to be 1/go .
gm and go depend on the transistor characteristics. Assuming the transistor to
be in saturation, we can use an approximate model and write:
K
 
Id ' (Vg − VTo − αVs )2 (4)
2α
where, K is the conductivity factor given by:
W W
   
K = K0 ≡ µCox (5)
L L
VTo is the threshold voltage without substrate bias, and α is a parameter which
accounts for the effect of substrate bias Vs . α is weakly dependent on Vd and its
value is close to 1. W and L are transistor width and length respectively. Vs is the
substrate bias. We define

VGT ≡ (Vg − VTo − αVs ) (6)

The drain current can then be written as:

K
 
Id = V2 (7)
2α GT
2
We can thus express gm as :
!
∂Id K K0 W
 
gm = = VGT = VGT (8)
∂Vg α α L
From equation(7), we can evaluate VGT to be
s
2αId
VGT = (9)
K
Substituting it in equation(8) gives
s s
2KId 2K 0 W
 
gm = = Id (10)
α α L
Similarly, we can use equation(7) to eliminate K from the expression for gm .
2αId
K= (11)
VGT 2
Substituting in equation(8),
2Id
gm = (12)
VGT
While these three equations for gm are equivalent, they appear quite confusing
at first. In order to get a large value of gm , should we increase VGT (according
to equation 8) or decrease it (according to equation 12)? The transistor size
determines the value of K (equation 5). Is gm linearly dependent on transistor size
(equation 8), dependent on its square root (equation 10) or is it independent of
transistor size (equation 12)?
In fact the confusion arises because the geometry (and hence K), the gate volt-
age (VGT ) and the drain current (Id ) are not independent of each other. These are
constrained by the drain current equation and so, only two of these can be chosen
at a time. (We are assuming that the transistor is in saturation and therefore, Id
is relatively insensitive to Vd .) Which equation should be used for gm (and other
variables) depends on which parameters have been fixed by design and bias condi-
tions. For example, if the geometry and the gate bias is fixed, equation(8) should
be used for gm . If, on the other hand, the transistor is current biased, equation(10)
is appropriate. Finally, if both the gate voltage and drain current have been fixed
by the design, with the assumption that the geometry will be adjusted to provide
the given amount of drain current at the given gate voltage, equation(12) should
be used for evaluating gm .
Evaluation of go is not so obvious from the simple transistor models. However,
the output conductance is set by the slope of the drain characteristics in the
saturation region. Assuming a simple Early effect like model, we can write for go :
go ' λ0 Id /L (13)
where L is the channel length and λ is a technology dependent parameter. In
terms of geometry and VGT , we can write:
λ0 K 0 W 2
go = V (14)
2 L2 GT
3
The voltage gain can then be written in terms of geometry and VGT as:
2L
Ao = (15)
λ0 V GT

We see that when biased at constant VGT , Ao depends on L and is independent of

W. In terms of drain current and geometry,
s
1 2K 0 W L
Ao = 0 (16)
λ α Id
Thus, if the transistor is biased at constant current, the DC gain is determined by
the square root of the gate area.

2.2 AC Behaviour of the simple gain stage

Cgd
G vo
D
vi Cg gm vi ro Co
S S
Figure 2: AC equivalent Circuit

Applying KCL at A gives

vo
sCgd (vi − vo ) − gm vi − − sCo vo = 0 (17)
ro
Separating terms involving vi and vo , we get
1
 
vi (sCgd − gm ) − vo sCgd + + sCo = 0 (18)
ro
from where we can calculate the AC gain A1 as
vo 1 − sCgd /gm
A1 = = −gm ro (19)
vi 1 + sro (cgd + co )
we define
Ctot ≡ Cgd + Co (20)
Then,
1 − sCgd /gm
A1 = A o (21)
1 + sro Ctot
Normally, ωCgd /gm << 1 Therefore,
Ao
A1 '
1 + sro Ctot

4
This describes the frequency response of a system with one dominant pole. The
bandwidth is given by 1/ro Ctot . The Gain Bandwidth product is given by
1 gm
GBW = gm ro · = (22)
ro Ctot Ctot
We see that the gain bandwidth product (or the cutoff frequency) is independent
of ro .

Ao
A - 3db
o Gain (db)

0 db
BW GBW
Frequency

Figure 3: Frequency response of single transistor amplifier

The maximum possible cutoff frequency occurs for an unloaded amplifier, where
the capacitive load is entirely due to the device capacitance itself. we can take the
output node capacitance to be proportional to the device width. Then,

Ctot = χW (23)

where χ is a technological parameter. Substituting this in equation(22),

gm
GBWmax = (24)
χW

using equations(8, 10 and 12) for gm , we can write:

K 0 VGT
GBWmax = (25)
αL
s
1 2K 0 Id
= (26)
χ αL
2Id
= (27)
χW VGT
The relationships derived above have been summarized in the table below.
Using expressions for DC gain and GBW max , we can express their product as:
s s
2L K 0 VGT 1 2K 0 W L 1 2K 0 Id
Ao · GBWmax = 0 · = 0 ·
λ VGT αχL λ αId χ αW L

5
 Free Design Variables:
Parameters W, L, VGT q
W, L, Id L, VGT , Id
0
K W VGT 2K W Id
0 2Id
gm αL αL VGT
2
λ0 K 0 W VGT λ0 I d λ0 I d
go 2L 2
q L L
2L 1 2K 0 W L 2L
Ao λ0 VGT qλ αId λ VGT
0 0

K 0 W VGT 2K 0 W Id 1 2Id
GBW αLCtot αL Ctot VGT Ctot
q
K 0 VGT 1 2K 0 Id K 0 VGT
GBW max αχL χ αW L αχL

Table 1: Relations for circuit parameters in terms of technological, geometrical

and operating point variables.

which can be simplified to

2K 0
Ao · GBWmax = (28)
αλ0 χ
The above relation shows that the product of DC gain and GBW max depends only
on technological parameters and is independent of geometry and the operating
point of the transistor. This represents a technological constraint: for a given
technology, the DC gain and cut-off frequency (Gain Bandwidth product) cannot
be set independently. The product of the two is constrained by the relation (28).
If we require values of Gain and cut-off frequency, such that their product exceeds
the value given by equation(28), we cannot achieve it using the single transistor
amplifier configuration. We must use other configurations such as the cascode or
the gain boosted cascode.

3 Cascode Gain Stage

A cascode stage uses two transistors connected as shown in fig.4. The signal goes

I
d
V
d2 v out
V Vg2
ref M2

V
d1
Vg1
v in M1

Figure 4: A Cascode Amplifier

to the gate of the lower transistor. The gate of the upper transistor is held at

6
a fixed voltage Vref , such that both transistors operate in saturation mode. The
lower transistor acts as a common source amplifier, whereas the upper transistor
works in the common gate configuration. We shall use subscripts 1 and 2 to
denote the lower and upper transistors respectively. To analyze the cascode stage
and its circuit performance, we treat the two series connected transistors as a
single compound transistor with the gate and source of M1 and drain of M2 acting
as the corresponding terminals of the equivalent transistor. We then evaluate
its equivalent gm and go values, so that we can use the expressions for circuit
performance derived in the previous section. Since the two transistors are in series,
their drain currents are equal. We define gmeq and goeq in a fashion analogous to
the single transistor case, so that

dId = gmeq dVg1 + goeq dVd2 (29)

Thus,
∂Id
gmeq = ∂Vg1
with dVd2 = 0 (30)
∂Id
goeq = ∂Vd2
with dVg1 = 0 (31)

3.1 Equivalent gm of the Cascode stage

To evaluate gmeq , we make dVd2 = 0 and evaluate the change of drain current with
change in the gate voltage of M1. Since the drain as well as the gate of M2 are
held at fixed voltages,

dVds2 = 0 − dVs2 = −dVd1 (32)

dVgs2 = 0 − dVs2 = −dVd1 (33)

Making use of these, we can write for the small signal change in drain current

id = gm1 vg1 + go1 vd1 (34)

id = −gm2 vd1 − go2 vd1 (35)

id
so vd1 = −
gm2 + go2
Notice that the source of the upper transistor is not at the substrate potential.
Therefore, as the drain voltage of the lower transistor changes, the drain current
of the upper transistor changes due to two distinct reasons:

1. The gate source voltage of the transistor changes. As the drain voltage of
the lower transistor goes up, the value of the gate-source voltage of the upper
transistor reduces, reducing its current.

2. As the source voltage of the upper transistor changes, its threshold voltage
changes. This changes its effective over-voltage, and hence the current. If
the drain voltage of the lower transistor rises, the threshold voltage of the
upper transistor becomes higher, reducing its current.

7
It is assumed that gm2 is defined so as to account for both of these. We can
eliminate vd1 from equation(34) to obtain
go1
id = gm1 vg1 − id
gm2 + go2
and therefore, !
go1
id 1+ = gm1 vg1
gm2 + go2
So,
id gm2 + go2
gmeq = = gm1 (36)
vg1 go1 + go2 + gm2
Generally gm values are much higher than go values. In this case, we can see that
gmeq ' gm1 . The slight reduction in gm value from gm1 is due to feedback through
the drain voltage variation of the lower transistor.

3.2 Equivalent go of the Cascode stage

As can be seen from equation(42), we must make dVg1 = 0 and evaluate the change
of drain current with respect to change in the drain voltage of M2 to evaluate goeq .
Under these conditions,
dVgs1 = 0 (37)
dVgs2 = 0 − dVs2 = −dVd1 (38)
dVds2 = dVd2 − dVd1 (39)
Making use of these, we can write for the small signal change in drain current
id = 0 + go1 vd1 (40)
id = −gm2 vd1 + go2 (vd2 − vd1 ) (41)
From equation(40),
id
vd1 =
go1
Substituting in equation(41):
gm2 + go2
id = −id + go2 vd2
go1
From where we get
id go1 go2
goeq = = (42)
vd2 go1 + go2 + gm2
If we again make use of the fact that gm values are much higher than go values,
go2
goeq ' go1
gm2
Thus goeq is lower compared to go1 by a factor equal to the voltage gain of the
upper transistor. As we have seen earlier, the equivalent gm is practically the same
as that for a single transistor amplifier. Since the output resistance is higher (goeq is
lower), the DC gain is increased.

8
3.3 DC Gain
Having evaluated gmeq and goeq , we can write for the DC gain of the stage:

gmeq gm1 (gm2 + go2 ) g01 + g02 + gm2

Ao = − =− ·
goeq g01 + g02 + gm2 g01 g02

This simplifies to
gm1 (gm2 + go2 )
Ao = −
g01 g02
We can write this as:
gm1 gm2
Ao = − · (1 + ) (43)
g01 g02
We can define the individual DC gains of the two transistors (in common source
and common gate configurations respectively) as
gm1 gm2
A01 ≡ − and A02 ≡ 1 +
g01 g02
Then,
Ao = −A01 · A02
Thus the DC gain is equal to the product of the DC gain of the two transistors.

3.4 AC behaviour
Since gmeq for the cascode stage is about the same as that for a single transistor
stage, the Gain Bandwidth product also remains unchanged. Because of a higher
output resistance, the bandwidth is reduced and the DC gain is higher for a cascode
stage.
The figure below gives the AC equivalent circuit of the cascode amplifier. As

ro2
Cdg1
G vx vo
vi ro1 gm2 vx Co
Cg1 gm1 vi
S
Figure 5: AC equivalent Circuit of the Cascode Amplifier

we shall see presently, vx is quite small. This permits us to ignore the effect of the
drain capacitance of the lower transistor and the gate capacitance of the upper
one. If we wish, we can always replace ro1 by a parallel combination of ro1 and the

9
capacitance seen at the drain of the lower transistor.

writing the KCL equation at the output we get

vx − v o
gm2 vx + = sCo vo (44)
ro2
which leads to
1 + sro2 Co 1 + sro2 Co
vx = vo = vo (45)
1 + gm2 ro2 A2
Since A2 is quite large, vx is very small compare to vo .

KCL at the drain of the lower transistor is:

vx
sCdg1 (vi − vx ) = gm1 vx + + sCo vo (46)
ro1
which gives
vo (A1 − sro1 Cdg )A2
=− (47)
vi (1 + sro2 Co )(1 + sro1 Cdg ) + A2 sCo ro1
If sro1 Cdg is small, we can simplify the above relation to get
vo A1 A2
Voltage gain = =− (48)
vi 1 + sro1 Co (A2 + ro2 /ro1 )
This shows that the DC gain is multiplied by A2 and the bandwidth is reduced
by roughly the same factor. This keeps the gain-bandwidth product the same as
a single transistor amplifier.

Because the DC gain is higher while the gain-bandwidth product remains un-
changed, it is possible to design amplifiers which go beyond the technological limit
discussed earlier (eq. 28). (The technological limit placed a bound on the product
of DC gain and gain-bandwidth product for a single transistor amplifier). However,
a limitation still exists on the achievable DC gain and gain-bandwidth product from
the cascode configuration. Assuming the two transistors to be identical, the DC
gain is the square of the one transistor DC gain, while the gain-bandwidth product
is unchanged. Thus we can see that for the cascode configuration, the product of
the square root of the DC gain and the gain-bandwidth product is bounded by the
technological constraint.

3.5 Practical Cascode circuits

The circuit we have analyzed up to now has used an ideal current source as the
load. In practice, the load will be implemented using MOS transistors. The output
resistance of the cascode stage will then be in parallel with the output resistance
of this current source load. If we use a single transistor current load, the output
resistance of the load will be ' ro while that of the cascode stage will be ' A × ro .
The final output resistance will thus be dominated by the much lower resistance
of the load and we shall lose the advantages of the cascode stage. It is important,

10
therefore, that the load also should be a current source made from a cascode pair.

This implies that the stage will use four transistors in series as shown in figure
6 below . (This is often called the telescopic cascode). This, however, limits the

Vbiasp1

Vbiasp2
vout
Vbiasn

vin

Figure 6: Telescopic Cascode Amplifier

range of output voltages for which all transistors will operate in their saturation
regions, as required for proper circuit operation.

3.6 Folded Cascode

The cascode configuration uses a common source stage directly coupled to a com-
mon gate stage. The common gate stage need not always be of the same channel
as the common source stage. If we use complementary stages, we get a folded cas-
code. The basic folded cascode configuration is shown in the figure below: Here,

M3
Vbiasp1

M2 Vbiasp2
vin M1
vout
Load

Figure 7: Folded Cascode Amplifier: schematic

the n channel M1 and the p channel M2 form the cascode pair. M3 provides the
necessary bias current. The output resistances of M1 and M3 are in parallel. How-
ever, the node where the drains of M1 and M3 are connected has its voltage swing
reduced by the cascode action provided by M2. Therefore, we can show that the
output resistance in this configuration is:
rout = (1 + gm2 ro2 )(ro1 ||ro3 ) + ro2

11
This is lower than the output resistance of the telescopic cascode stage, because
of the paralleling of ro1 and ro3 . However, it is much higher than the single
transistor output resistance. Fig.7 does not show a load connected to the stage.
Clearly, the load used in this case should be cascoded as well, otherwise, its low
output resistance will come in parallel with the gain-multiplied output resistance
of the stage. The practical folded cascode circuit is shown in the figure below:

M3
Vbiasp1

M2 Vbiasp2
vout

Vbiasn2
M1
vin
Vbiasn1

Figure 8: Folded Cascode Amplifier

3.7 Gain boosted cascode Amplifiers

I
d
V
d2 v out
V +
ref M2
-

Vg1 Vd1
v in M1

Figure 9: Gain boosted Cascode Amplifier

In a telescopic cascode amplifier, the lower transistor acts as a transconduc-

tance element while the upper one multiplies the output impedance. The output
impedance is multiplied because the swing on the drain of the lower transistor is
reduced by the voltage gain of the upper (common gate) transistor. Obviously,
higher the voltage gain of this transistor, higher the output resistance and hence,

12
higher the DC gain of the cascode stage. This basic idea behind the cascode am-
plifier can be carried a step further. The gain of the output resistance amplifier
element can itself be increased by an ancillary amplifier. This is illustrated in
fig.9 The ancillary amplifier could be a cascode stage and we can boost its gain by
the same technique. We could extend this gain boosting to any number of boost
stages. The maximum obtainable DC gain is limited by thermal drift and noise
etc. In practice, the boost amplifier itself is rarely gain boosted further.

4 The difference Amplifier

The amplifiers we have discussed up to now have had a single input measured with
respect to the ground or some other fixed potential. Amplifiers which amplify the
difference of two input voltages (each of which has equal and opposite signal ex-
cursions) have many advantages over single ended amplifiers. It is more convenient
to represent the two input voltages by their mean and difference values. We define
the differential and common mode input voltages by the relations
vid ≡ vi1 − vi2 (49)
vi1 + vi2
vicm ≡ (50)
2

Vdd

vo 1 vo 2

vi 1 vi 2

Figure 10: Possible implementation of a difference amplifier

One (not very good) way of implementing a difference amplifier is to use two
single ended amplifiers as shown in figure10. The difference of the two outputs
would be the output. Analogous to the definition of the common mode and dif-
ferential input voltage, we can define the common mode and differential output
voltages as:
vod ≡ vo1 − vo2 (51)
vo1 + vo2
vocm ≡ (52)
2
The common mode and differential gains can be defined as:
vod
Adif f ≡ (53)
vid
vocm
Acm ≡ (54)
vicm

13
For a good difference amplifier, the differential gain should be high and independent
of input common mode voltage, whereas the common mode gain should be as low
as possible. The common mode rejection ratio is defined as
Adif f
CM RR ≡ 20 log dB (55)
Acm
In the simple suggested circuit, transistor currents, and hence the differential gain,
will depend on the common mode voltage. This is not a desirable feature as we
would like a good difference amplifier to ignore the common mode voltage and to
amplify just the difference signal. A better difference amplifier can be implemented
if we add a current source to keep the total current constant. If the common mode

Vdd

vo 1 vo 2

vi 1 vi 2

Vs
Is

Figure 11: A better implementation of the difference amplifier

voltage appearing at the two inputs changes, it will only change the voltage at the
node where the two sources join (Vs ). However, the current remains unchanged
due to the current source - and therefore, the differential gain is unaffected by the
common mode voltage. This results in a high common mode rejection ratio.

4.1 Differential to single ended conversion

Very often, we need a single output which is proportional to the difference between
the two inputs. Therefore, we need to combine the two outputs. This can be done
by using current mirror loads. This is shown in the circuit below. We have

iout = I(M p2) − I(M n2)

But due to the current mirror action, I(M p2) = I(M p1). Since Mp1 and Mn1 are
in series, I(M p1) = I(M n1). Therefore,

iout = I(M n1) − I(M n2) = gm (vi1 − vi2) = gm vid

Thus we have a single output which is proportional to the difference of inputs.

But by definition,

iout = I(M n1) − I(M n2) ≡ Gm (vi1 − vi2) = Gm vid

14
 Vdd
Mp1 Mp2
i out

vi 1 vi 2
Mn1 Mn2
Vs
Is

Figure 12: A difference amplifier with single-ended output

where Gm is the equivalent transconductance of the differential amplifier stage.

We can see that the effective Gm is just the gm of either of the diff-pair transistors.
Notice that the output here is a current. Therefore, this circuit is also called a dif-
ferential transconductance amplifier. The output voltage is this current multiplied
by the effective output resistance of the stage.

Rout = ro (M n2)||ro (M p2)

Analogous to the single transistor amplifiers we have analyzed before,

voltage gain = gm (ro (M n2)||ro (M p2))

and
gm
GBW =
CL
where CL includes Cdg and Cd for Mn2 and Mp2, as well as the load capacitance.

5 The two stage op-amp

A simple two stage op-amp can be constructed by following the difference amplifier
discussed above by a single transistor amplifier with a current load. The current
source for the differential amplifier is implemented by an n channel MOS transistor
in saturation. The capacitor between the outputs of the differential stage and the
common source output stage is called the compensation capacitor and is required
for making the circuit stable when external negative feedback is used. The equiv-
alent circuit of the op amp (without the compensation capacitor) is given in the
figure below: Each stage of the op amp can be considered a gain stage with a
single pole frequency response.
Notice that the phase of the output of each stage will undergo a phase change of
90o around its pole frequency.

15
 Vdd
Mp3
Mp1 Mp2
i out

vout
vi 1 vi 2
Mn1 Mn2
Vs
Mn3
Vbias Mn4

Figure 13: A simple two stage op-amp

Differential Stage Output Stage

gm11 v1 gm22 v2
v2 v0

R1 C1 R2 C2

Figure 14: Equivalent Circuit of the two stage op-amp

5.1 Stabilization of the Op Amp

Most op amps are used with negative feedback. As we have seen in our earlier
discussion, both stages of the op amp have a single pole frequency response. The
poles for both the stages can be quite close together. As a result, they can con-
tribute a total of 180o phase shift over a relatively narrow frequency range. At
the frequency where this happens, negative feedback will be converted to positive
feedback. If at this frequency the gain is well above one, the circuit will oscillate.
To avoid this, we would like to arrange things such that the gain drops to below
one by the time the total phase shift around the feedback loop becomes 360o - even
if it means that we have to reduce the bandwidth of the amplifier. This is often
achieved by a technique called pole splitting. The lower frequency pole is brought
to a low enough frequency, so that the gain diminishes to below one by the time
the second pole is reached. One way of doing this is to use a Miller capacitor. The
concept is shown in the figure below: The first stage sees a load capacitance =
1
A2 × C because of the Miller effect. This brings its pole to ro 1×A 2 ×C
. The total
DC gain is A1 × A2 . The overall bandwidth is defined by the first stage. Therefore
the gain-bandwidth product is:
A1 × A 2 A1
= (56)
ro 1 × A 2 × C ro 1 × C
This is the same as the gain-bandwidth product of the first stage.

16
 C

A1 A2

Figure 15: Use of Miller capacitance for pole splitting

5.2 Slew Rate

Miller compensation also sets the slew rate of the op amp. For a large differential
input voltage, all the tail current is steered to one of the two differential transistors.
Thus the output current is equal to the total bias current of the differential stage.
Since the effective load capacitance for the first stage is A2 × C,
dV
A2 × C = I(M n4)
dt
Therefore the output of the first stage slews at a rate I(M n4)
A2 ×C
. Because of the gain
of the second stage, the op amp output slews at a rate which is A2 times this value.
(This assumes that the second stage is operated at a high enough bias current, so
that the slew rate is limited by the first stage charging the Miller capacitor and
not by the second stage charging the load capacitor). Hence the slew rate of the
op amp is I(MCn4) .

5.3 Design equations for the op amp

For proper operation of the op amp, all transistors must be kept in their saturation
regions. Mp1 and Mp2 are matched and connected in a current mirror configu-
ration. Therefore I(Mp1) = I(Mp2). Since Mn1 and Mn2 are also matched we
have
I(M n4)
I(M n1) = I(M n2) = (57)
2
I(M n1) = I(M p1) (Series connection) (58)
I(M p1) = I(M P 2) (Mirror) (59)

Because the drain and gate of Mp1 are shorted, it is always in saturation. Mp2
has its source and gate at the same potentials as those of Mp1, and also has the
same drain current. Thus, its drain-source voltage must be equal to that of Mp1.
Therefore it is also always in saturation.

Mp3 has the same gate and drain potentials as Mp1 and Mp2. If we ensure
that it has the same drain potential as Mp1 and Mp2, it will also be guaranteed

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to be in saturation. This can be ensured if
I(M p3) W/L(M p3)
= (60)
I(M p1) W/L(M p1)

Differential Stage Output Stage

Cc
v2 v0

R1 C1 R2 C2

gm11 v1 gm22 v2

Figure 16: Equivalent circuit of op amp with compensation

The voltage gain of the first stage is given by gm (M n2) × (ro (M n2)||ro (M p2)).
The voltage gain of the second stage is gm (M p3)×(ro (M n3)||ro (M p3)). Therefore,
the overall voltage gain is:

A = gm (M n2) × gm (M p3) × (ro (M n2)||ro (M p2)) × (ro (M n3)||ro (M p3)) (61)

In order to design the op amp, we proceed as follows:

• We select a compensation capacitor value to obtain adequate stability. Typ-

ical values are are a few pF.

• We select a ratio of the bias currents of stage 2 and stage 1. Stage 2 would
typically be operated at 5 times the tail current of the differential amplifier.
We should ensure that the slew rate limitation comes from the first stage
charging the Miller capacitor and not by the second stage charging the load
capacitor.

• The slew rate required from the op amp determines I(Mn4), the tail current.
Currents through Mn1, Mn2, Mp1 and MP2 are half this value. Current
through Mp3 is the assumed ratio (say 5) times the current through Mn4.
At this stage, We know the current through all the transistors.

• The required gain-bandwidth product determines gm of the first stage.

Gm
GBW = (62)
C
This Gm is equal to the gm of Mn1 or Mn2. Since the current as well as
gm of Mn1 as well as Mn2 are now fixed, their geometries can be determined
from: q
gm (M n2) = 2K 0 W/L(M n2)I(M n2) (63)
The W/L value for Mn1 is the same as that for Mn2.

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 • Since currents through Mn2,Mp2, Mp3 and Mn3 are known, their output
conductances can be calculated (go = Id /VA where VA is the Early voltage
= L/λ0 ). The overall DC gain is given by

gm (M n2)gm (M p3)
A=
(go (M n2)||go (M p2))(go (M p3)||go (M n3))

As gm for Mn2 and all go values are known, this determines the gm for MP3.
Once we know the gm as well as the current for Mp3, we can calculate its
geometry.

• Once the geometry of Mp3 is known, geometries of Mp1 and Mp2 are deter-
mined by eq 60.

• The geometries of Mn4 and Mn3 are determined from current mirror ratios
in relation to a given reference transistor for bias generation.

6 Example Design
Assume a technology where K’ for n channel transistors is 120 µA/V 2 and for p
channel transistors is 60 µA/V2
The threshold voltages for n and p channel transistors are +0.4 and -0.4V respec-
tively. We shall use channel lengths which are about 4 times the minimum channel
length. For this choice of L, assume that the Early Voltage VA = 20V for both p
and n channel transistors

We want to design an op amp with DC gain of 80 dB (Voltage gain of 10000).

The Gain Bandwidth product is required to be 50MHz and we would like a slew
rate of 20V/µs.

1. We choose a compensation capacitor value of 2 pF.

2. We shall bias the second stage at 5 times the tail current of the differential
stage.
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3. From the slew rate, I(Mn4) = 2 × 10−12 × 10−6
= 40µA

4. Therefore I(Mn1) = I(Mn2) = I(Mp1) = I(Mp2) = 20µA

and I(Mp3) = I(Mn3) = = 200µA

5. From the GBW specification,

gm (Mn2)
2π × 50 × 106 =
2 × 10−12

This gives gm (Mn2)1s '= 628µ0.

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 6. To get a gm of 628 µ0 with a current of 20µA,
q
628 × 10−6 = 2 × 120 × 10−6 × (W/L) × 20 × 10−6

This gives the W/L of Mn2 as ≈ 82

W/L of Mn1 should be the same as Mn1 and Mn2 are matched.

7. go of Mn1 and Mp1 is = 20µA/20V = 1µ0.

Therefore the parallel output conductance of Mn1 and Mp1 is 2µ0.
go of Mn3 and Mp3 is = 200µA/20V = 10µ0.
So the parallel output conductance of Mp3 and Mn3 is 20µ0.
Therefore, to get an overall DC gain of 10000,

628µ0 gm(M p3)

10000 = ×
2µ0 20µ0
This gives the gm of Mp3 as ' 32µ0.

8. To get a gm of 32µ0 with a drain current of 200µA, we should have

q
32 × 10−6 = 2 × 60 × 10−6 × (W/L) × 200 × 10−6

which gives the W/L of Mp3 as ≈ 17.

9. Since the geometry of Mp1 and Mp2 has to be in the current ratio with Mp3,
W/L of Mp1 and Mp2 should be ≈ 1.7.

10. Finally, we assume that an n type reference bias transistor of W/L = 4 is

available with a current of 10 µA. This will give the W/L of Mn4 and Mn3
as 16 and 80 respectively.

This finishes the design for the simple op amp.

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