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# The Chinese University of Hong Kong

## Department of Electronic Engineering

ELE 5260 CMOS Integrated Circuit

## Tutorial 11 CMOS Analog Circuits

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## Channel Length Modulation Factor ( ):

'I D

'VDS

Current Equation:
*** Saturation:

I DS

E
(V gs  Vt ) 2 (1  OVDS )
2

Linear:

IDS

E
2
[2(VDS (VGS  VT )  V DS ](1  OV DS )
2

Note:
1. Unlike digital circuits, we do not use MOSFETs with shortest channel. Long channel transistor
has a flatter slope in saturation region in IDS vs VDS curve large output resistance
2. We bias MOSFETs into saturation region for CMOS Analog Circuit
Small Signal Model of a MOSFET

## Note: PMOS, NMOS use the same small signal model.

Trans-conductance (gm) =
Output-conductance (gds) =

2EI DS
IDS

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## The Chinese University of Hong Kong

Department of Electronic Engineering
ELE 5260 CMOS Integrated Circuit

## CMOS Analog Circuit Sub-circuits:

Diode-Connected Transistor:

Since gm >>gds, we model MOS diode as a resistor across Drain and Source with resistance 1/gm
Simple Current Source:

Current Mirror:

I1
I2

Pcox W
2
(VGS1  VT )
2 L 1
Pcox W
2
(VGS 2  VT )
2 L 2

VGS 1

VGS 2

I2
I1

W

L 2
W

L 1

If the two transistors have the same geometry, I1 = I2. ThatTs why we call this circuit current mirror.

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## The Chinese University of Hong Kong

Department of Electronic Engineering
ELE 5260 CMOS Integrated Circuit

## Tutorial 11 CMOS Analog Circuits

DC Biasing Circuit:

EN
EP
(VDD  VR  VTP ) 2
(VR  VTN ) 2
2
2
EN
V  (VDD  VTP )
E P TN
VR
EN
1
EP

## Charateristic: - Typical Gain: -10 to -100

- High input impedance

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## The Chinese University of Hong Kong

Department of Electronic Engineering
ELE 5260 CMOS Integrated Circuit

## ***** Complete Analysis of a CMOS Common Source Amplifier

For the following circuit, find:
(i)
Small signal gain of the circuit
(ii)
The frequency of the dominant pole
Given Vtp = -1V, Vtn = 1V, pCox = 30 A/V2,

nCox

= 60 A/V2,

N=

0.001

Step I: DC analysis
The first thing we need to do is to perform a DC analysis, i.e., finding the dc current and voltages
for the transistors.
a. Identifying the DC biasing circuit (inside the dashed line), the transistors without ac signal
input are the DC biasing circuit.
b. Identify the driver MOSFET. The driver MOSFET is the transistor with ac input. In this
example M1 is the driver.
c. Identify the load MOSFET. The load MOSFET is connected to the driver MOSFET
directly. In this example M2 is the load.
d. Calculate the DC current IDS of the driver.
For the above circuit, M3, M4 and M5 forms a potential divider, i.e., VG3 = 2/3 * 6 = 4V.
EP
(V DD  VG 3  Vtp ) 2 (1  OV DS ) 15 u 10 6 u 10 u (2  1) 2 u (1  0.002) 150.3PA
2
Transistor M2 and M3 is a current mirror pair, thus I DS1 I DS 2 150.3PA .
I DS 3

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## The Chinese University of Hong Kong

Department of Electronic Engineering
ELE 5260 CMOS Integrated Circuit

## Step II: Small Signal Gain

Once we finished the DC analysis of the circuit, we could find the small signal gain by replace the
MOSFETs with small signal model. To perform small signal analysis:
-

circuit.

## Disable ALL INDEPENDENT CURRENT SOURCES and CAPACITORS by open

circuit
Now we replace the MOSFET with small signal model and simplification, we will get the following
circuit:
Super-node D

g m1

2 EI DS1

2 u 60 u 10 6 u 5 u 150.3 u 10 6

g ds1

OI DS 1

0.001 u 150.3 u 10 6

g ds 2

O IDS 2

g ds1

300.3 u 10 6 : 1

150.3 u 10 9 : 1

## g m1v gs  vds ( g ds1  g ds 2 )

Vout ( g ds1  g ds 2 )

g m1Vin
Vout
Vin

g m1
g ds1  g ds 2

Vout
Vin

300.3 u 10 6

2 u 150.3 u 10 9

999 | 1000

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## The Chinese University of Hong Kong

Department of Electronic Engineering
ELE 5260 CMOS Integrated Circuit

## Step III: Frequency Response

The method of finding frequency response of the circuit is similar for small signal gain, we also
need to find out the small signal model, but this time, we need to include those capacitors and
inductors also, i.e.
- Disable ALL INDEPENDENT VOLTAGE SOURCES by short circuit.
- Disable ALL INDEPENDENT CURRENT SOURCES by open circuit
The circuit now will change to:
Super-node D

## sC (Vout  Vin )  g m1Vin  Vout ( g ds1  g ds 2 )

Vout ( sC  g ds1  g ds 2 )
Vout
Vin

Vin ( g m1  sC )

g m1  sC
sC  g ds1  g ds 2

g m1
g ds1  g ds 2

sC
g m1
sC
1
g ds1  g ds 2
1

## The dominant pole frequency is:

g ds1  g ds 2 2 u 150.3 u 10 9
C
5 u 10 12
Thus f = /(2 ) = 9.712 kHz
Z

60120

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