Beruflich Dokumente
Kultur Dokumente
M6
Vbias1
M3
M4
M8
M9
M7
M10
M11
M1
M2
Vin+
Vin-
Vbias2
Vout
M12
M5
Vbias0
M14
CL
M13
Vbias2
M15
Erik Sll
Robert Hgglund
K Ola Andersson
Niklas U Andersson
J Jacob Wikner
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Introduction Page 3
1 Introduction
The purpose of these laboratories is to get an insight in the design procedure of analog circuit as well as using a circuit simulator in order to estimate the behavior of a few analog
circuits. The tools used in the laboratory is Cadence and the transistor-level simulator
Spectre. An introduction on how to run these tools are given in this manual as well.
For some of the exercises you will find a sign (as shown to the right). This implies
that you should do some preparatory exercises that are found in the Exercise
Manual. This is important due to a number of reasons, since it will...
reduce the time for you in front of the computer screen
help you understand some of the issues much better
... and therefore read this note:
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For the lab, you may need additional tools like Matlab and Mathematica for computations
of for example the small-signal transfer function. Mathematica is a powerful tool when you
want to derive an analytical expression to a given circuit topology.
You should now copy the netlist file to you lab directory. It is found at
cp -R /proj/tde/TSTE80/Lab/ANTIKlab ~/cadence/CSI.AMS.035/
cp -R /proj/tde/TSTE80/Lab/.artist_states $HOME
In the library manager choose the menu alternative Edit->Library Path and add the
library ANTIKlab with the path $HOME/cadence/CSI.AMS.035/ANTIKlab. Save as
cds.lib and exit the Library Path Editor. A new library will now be visible in the
Library Manager.
Starting Cadence the next time
The next time you start Cadence you just have to go to the directory
cadence/CSI.AMS.035/
and then load the required modules and use the ams_cds-command to start Cadence,
according to below. It could therefore be practical to save these commands in a text-file.
You can then copy the commands from that file to the terminal window the next time you
start Cadence. Also make sure that no other cadence modules or technology modules are
loaded. If this is the case you have to unload them before entering the commands below.
module load cadence
module load ams
ams_cds -tech c35b4 -mode fb &
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Elements such as voltage sources, transistors, and capacitors are predefined building
blocks that can be inserted in the schematic by either the menu alternative
Add>instance or by the short cut i. A subwindow will appear where you can add a component by specifying the library, cell and view. The view should be symbol. You can either
add a process defined cell for example the ones listed in Table 1, or a component of your
own.
Component
Library
Cell
View
Vdd
analogLib
vdd
symbol
Ground
analogLib
gnd
symbol
DC voltage source
analogLib
vdc
symbol
DC current source
analogLib
idc
symbol
analogLib
vsin
symbol
analogLib
isin
symbol
analogLib
vpulse
symbol
analogLib
ipulse
symbol
analogLib
vcvs
symbol
Ideal resistor
analogLib
res
symbol
Ideal capacitor
analogLib
cap
symbol
PRIMLIB
rpoly
symbol
PRIMLIB
cpoly
symbol
NMOS transistor
PRIMLIB
nmos4
symbol
PMOS transistor
PRIMLIB
pmos4
symbol
When a component is chosen to be placed in the schematic, by either writing the names of
the libraries and the cell view or by using the browse button, the properties of the selected
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components will appear further down in the Add instance window. For example the
width and length of a transistor can be defined or the voltage of a voltage source.
Defining design variables
During the circuit designing procedure it is common that, for example, transistor widths,
bias currents, and voltage values must be adjusted to ensure that all transistors are operating in their desired operation region and to meet a certain specification. In this case, it
is easier to define variables for parameters that you frequently will adjust. Defining variables is just to write a parameter name in the desired field of a component, for example the
width of a specific transistor is set to the parameter W1.
When the CADE has started change the Project Directory to /tmp/sim
by the menu alternative Setup->Simulator/Directory/Host... in
CADE and press OK.
If you do not change the project directory to /tmp/sim you will have to restart Cadence
every time you forget to save the schematic before starting the simulation.
As stated earlier, the simulation environment can use several different types of simulators. The functionality, i.e., the types of analysis method, the speed, and the approximation
methods when solving the system of differential equations, differs between the simulators.
Analysis methods that can be used are, for example, DC analysis, small-signal analysis,
transient analysis, different type of noise analysis, distortion analysis and sensitivity
analysis. In the laboratories we will use the three most commonly used analysis methods
namely DC, AC and transient analysis
The simulation setup can be divided into three parts namely the analysis setup, the setup
of the output signals, and adding the design variables of the simulation.
Analysis setup
DC
The analysis part is like the ones in Spice, you can either check the DC behavior of the circuit and check that your components are operating correctly, i.e., all transistors are operating in the correct operation region and so on. Here you can for example sweep a
parameter like the bias current in your amplifier so that all transistors are operating in
the saturation region.
AC
The properties of the circuit with respect to a small change in the DC operating point can
be evaluated by linearizing the transistors around the DC operation point. This linearization as well as the simulation of the linearized circuit is performed in the AC analysis.
Transient
The transient analysis is used when the time response of a circuit is of interest. This analysis method takes into account clipping of the circuit.
Parametric analysis
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Results Page 7
Parametric analysis are used when two or more parameters are to be swept independently
of each other. For example, the current into a simple current mirror and the width of the
output transistor. In this case sweep the current in the DC analysis and add a parametric
sweep using the menu alternative in the CADE.
Tools->Parametric Analysis
Enter the name of the variable for the output transistor width into the field Variable
Name. Add the ranges of the sweep and start the analysis by selecting
Analysis->Start
Defining output signals
The outputs of the simulation can, for example, be the output voltage from an amplifier,
the current through a current mirror or a mathematically defined function to calculate the
unity-gain frequency of a circuit. These outputs can be selected from the schematic by
using the menu command Output->To Be Plotted->Select On Schematic and then
select the output to be plotted each time you do a simulation. Note that by selecting a wire,
the node voltage for that node will be plotted, by selecting a node the current through that
node will be plotted.
Define design variables
The variables defined in the schematic view can be imported into the simulation environment. This is done by using the menu alternative
Variables->Copy from Cellview
All the variables will now appear in the variable field in the Cadence Analog Design Environment window. To assign a value to one of the parameters just double click on the variable and enter the desired value.
5 Results
The DC operation conditions of a circuit are computed when a DC simulation has been performed. If you like to display the result directly in the schematic use the menu alternative
Result->Annotate->
If you like to display a complete list of the operation condition use
Result->Print->
Different alternative in the submenu of the print and annotate menu are listed below with
a short explanation.
Menu alternative
Description
DC node voltage
DC operating point
6 The calculator
The calculator can be used to, for example, add, subtract, multiply, or divide two waves,
take the discrete fourier transform or efficiently compute the DC gain, unity-gain freES, ISY, Linkpings universitet
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quency, phase margin and slew rate of a circuit. It is very handy when you are trying to
increase the performance of a circuit.
Plotting the derivative of a wave can be done in the following way. The calculator can be
started from the toolbar in the Waveform Window. Press the Wave button and select a
wave in the Waveform Window. Click on the Special Functions selection box and choose
the deriv command. To plot the derivative just select to Plot button.
Commands to use
Command
Description
phase
phaseMargin
Computed the phase margin of the circuit. (lookout for a 180 degrees phase
shift and mag or db commands)
cross
mag
dB
value
Shortcut
Description
delete key
Delete
escape
Insert component
l (small L)
Move an object
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Properties of an object
Rotate an object
Undo
Add a wire
Zoom in a box
F1
Help
F6
Redraw
Zoom out
Zoom in
8 An example circuit
The task is to design a common source amplifier to be used in an operational amplifier.
First we start by drawing the circuit in the schematic composer. The design parameters
will be defined as variables. To use the common source circuit in a hierarchical manner
when implementing the operational amplifier we like to have a symbol for the circuit. Further, a test bench for the common source circuit must be designed to evaluate the performance of the circuit.
The first thing to do is to create a library and a schematic cellview in the library manager.
A good name for the library is lab1 and for the schematic cellview use the name
Common_source. How to create the cellview and the library was shown in Section 3.
Drawing the schematic
When you created the cellview an empty window will appear called Virtuoso Schematic
Editing. In this window we will create the circuit shown in Figure 1.
Start by inserting the transistors by pressing the shortcut for insert instance i and then
choose the NMOS transistor from the library PRIMLIB, cell nmos4, and view symbol
which from now on will be written as PRIMLIB/nmos4.
The add instance window will now be updated and more fields will appear. In the Width
and Width Stripe field insert the variable win. In the Length field add the variable L.
The NMOS transistor can now be placed in the schematic window.
Continue with the PMOS transistors from the library PRIMLIB/pmos4 and the current
source from library analogLib/idc do not forget to add variable names as in Figure 1. If
you would like to change the properties of the components in the schematic, click on the
component and press q.
Connect the components by using wires. The shortcut w can be handy. Do not forget to connect the bulks of each transistor to the correct supply voltage.
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The last step is to add pins. This is done by the shortcut p. A new window will appear
and you can add the pin names and then place them in the schematic. Use inputOutput
pins.
Your schematic should look like the one in Figure 1. The last step is to save the schematic
by pressing X (shift+x). If there are any errors in the schematic then a dialog box will
appear and there will be some crosses that are flashing on the schematic. An explanation
to the errors will be shown in the icfb window. Correct the errors and warnings and save
the schematic. The schematic is finished.
Figure 1:
Left
Vin
Right
Vout
Top
AVDD
Bottom
AGND
A symbol appears which consists of a green rectangle that will be visible when used in a
schematic view, a red rectangle surrounding the green one which is the selection box of the
circuit, and some solid red squares, pins. In this view you can change the appearance of it.
For example, it can be changed to the one shown in Figure 2. A new shape can be drawn
through the menu alternative
Add->Shape
When the symbol is ready and you do not have the large red rectangle in the symbol used
the command.
Add->Selection Box
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and then select to add it automatically. The symbol must be checked and saved by the
menu alternative
Design->Check and Save
Selection box
Pin
Figure 2:
Figure 3:
The leftmost circuit is used to define the voltage between V dd and gnd . The parts for this
structure are analogLib/vdd, analogLib/gnd and analogLib/vdc. In the vdc symbol
set the parameter DC voltage to 3.3V which is used in this example. Leave the other
fields in the vdc symbol empty.
A voltage source is connected at the input, it is found in analogLib/vpulse enter the following parameters into the component properties.
Parameter
Value
Explanation
AC magnitude
1V
AC phase
DC voltage
Vindc
Voltage 1
3.3 V
Voltage 2
0V
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Delay time
0.1n s
Rise time
1p s
Fall time
1p s
Pulse width
10u
Period
20u
The common source stage can be found in the library lab1/Common_source no parameters can be set to this component. At the output of the gain stage we have the capacitor
which is found in analogLib/cap add the variable CL as the capacitance value.
Add labels to the input and output wires by using the shortcut l (lower-case L).
Save the test bench (shift+x).
Simulation of the common source amplifier
To start the simulation environment use the menu alternative Tools->Analog Environment from the Virtuoso
Schematic
Editing window containing the
Common_source_Testbench. A new window called Cadence Analog Design Environment (CADE) will appear.
Remember to change the Project Directory to /tmp/sim by the Setup>Simulator/Directory/Host... menu in CADE.
In this window we first get the design variables from the schematic by the command
Variables->Copy From Cellview. Set the variables to the following values
Variable
Value
Unit
win
100
wbias
100
Vindc
0.65
0.7
Ibias
126
CL
10p
Continue to add the output that you like to have from the simulation. This is done by the
command Outputs->To Be Plotted->Select On Schematic. Select the output node
and end the selection by pressing escape. If you are selecting a wire the voltage of that
wire will be displayed, the current can be displayed by choosing a node.
The last part is to choose the analysis types to be used by the menu alternative
Analysis->Choose...
In this case we would like to have a DC analysis. Check the dc analysis button in the
appearing window and Save DC Operating Point. In this case we do not like to have
any type of sweep so click on the apply button.
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Performance parameters
Value
DC gain
43.6 dB
Unity-gain frequency
32 MHz
Slew rate
14.4 V/us
What will happen with the bandwidth and the slew rate if the output capacitance, CL, is
increased? Perform an analysis by hand and compare the results with simulations.
R
Vout
Vin
M1
Figure 4:
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Analog Environment from the Tools menu. Load the state first-setup from the
Session->Load State in the Cadence Analog Design Environment, CADE, window.
Try to understand how to set the analysis types, the variables and the outputs.
Run the simulator by pressing the green traffic light. Check that there are no errors or
warnings in icfb window.
The output current from the transistor is a highly nonlinear function with respect to the
applied voltages on source, gate, drain, and bulk. Hence, we have to be careful with the
operating points of the transistors. The same argument holds since the gain of the transistor can be high, hence a small shift in the DC operating point may force the transistor out
of its wanted operating region. Therefore, we always run careful DC analyses first.
Secondly, although we only have one transistor, you will discover that a large number of
parameters that can be changed in order to get a correct DC operating point for the transistor. We have the resistance, the input DC voltage, the transistor channel width and
length, etc. Mostly, we will fix the transistor length and the input and output voltages are
given by a specification. Then the transistor width is the first parameter that should be
varied.
The third, note that when you change a parameter, you do not only change the DC voltage,
you also change the gain of the circuit, bandwidth, etc. There is a delicate relation between
a large number of factors.
The input DC voltage is 1 V. Which value on the transistor width should you have in order
to get 1.5 V at the output of the circuit?
Go back to CADE and change the design variable wincs to this new value. Rerun and
check the AC output instead.
Determine the DC gain and the -3dB frequency.
DC gain
-3dB frequency
Now, go back to CADE and change the DC input voltage (Variable Vindc) to 1.5V. Rerun
the simulation and find the DC gain and -3dB frequency. Comments?
DC gain
-3dB frequency
This is what happens when you get out of the correct DC operating region, the gain is drastically changing (why?). Check the DC output voltage by using the menu
Results->Annotate->DC Node Voltages.
Change back to a 1-V DC level at the input. What is the output resistance, and DC output
voltage? (Hint: use the command Results->Print->DC Node Voltage and
Results->Print->DC Operation Point.)
What is the total power consumption? It is found using the menu
Results->Print->DC Operation Point followed by clicking on the power supply voltage source, V0.
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Is the transistor operating in its saturation region? Check that V DS > V DS , sat and
V GS V T > 0 using the command Results->Print->DC Operation Point followed by
clicking on the transistor.
Check if the simulated gain is reasonably aligning with the derived g m g out -ratio.
b)
Rsrc
Vsrc
Csrc
Cload
RC-Voltageinput
Figure 5:
Non-ideal voltage source (a) and capacitive load added to the test circuit (b).
ance to the test circuits. Mostly, we deal with CMOS circuits and the gates of the transistors are used as input stages. This implies that the load resistance is infinite, but the load
capacitance can be something in the order of 25 pF.
In analog design we never use the minimum channel length, L min , of the transistors. The
minimum channel length is not guaranteeing a proper L , it is too poorly modeled in the
simulator. Instead, we use a minimum channel length of approximately 1.5 L min to
4 L min . Hence, for our process we will in the exercises use L = 1m . However, shorter
channel lengths can be used in order to increase some performance metrics while still have
acceptable circuit yield.
The RC-filter is already design in this laboratory and it is found in
ANTIKlab->RC-Voltage-input. To use this subcircuit it is just to connect the input
voltage source to the input terminal and the output terminal is connected to the input of
the circuit under test.
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M2
Vbias
Vin
Vbias2
M1
Vout
M2
Vout
Vout
Vin
Vbias1
M1
Vbias
M2
M1
Iin
Figure 6:
(c) Vin
(b)
(a)
Transistor view of single-stage amplifier stages including active load; common source (a),
common drain (b), and common gate (c).
Preparation!
Derive the small-signal models for the three circuits in Figure 6. Derive the
input and output impedances, the DC gain, and the bandwidth. Solve exercise 7
in Exercise Manual.
Modify the schematics starting with Active_load_ in the library ANTIKlab to simulate
these building blocks instead. Note that you have to add a number of bias voltage sources
for the added transistors.
The specifications on the circuits are given in Table 2 below.
Common source(a)
Common drain(b)
Common gate(c)
Unit
Bias DC voltage
2.3
0.6
2.3, 2.3
Input DC voltage
1.65
1.15
40
1.8
40
dB
Output DC voltage
DC gain
Once again when you simulate be very careful with the DC analyses. You may have to
increase the accuracy, i.e., more points in the parameter sweep, to find proper values.
When finding the proper signal swings at input and output we sweep the DC level from 0
to 3.3 V.
The input- and output ranges are defined as the voltage ranges for which all the transistors are saturated.
We will also investigate the settling time of the circuits as well as the general time-domain
behavior. By using the vpulse source we can apply a voltage step at the input. Select the
input source and press q and enter the following values in the vpulse field.
Voltage 1
Vindc
Voltage 2
Vindc+0.001
Delay time
1u
Rise time
10n
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Fall time
10n
Pulse width
8u
Period
10u
Let the simulation go to 4us by changing adding a transient analysis in the CADE window.
Note that for the low-gain stages you may have to change the +0.001 to a somewhat larger
value, like 0.01 to 0.1, in order to see good output results. Run and plot the input and output signals. Measure the time constant. When a small step is applied to the input of a circuit with a dominating pole the output signal will have the form
V (t) = V (0) + V ( 1 e t / ) .
(1)
where V is a function of the DC gain of the circuit times the size of the step at the input.
In other words the final output voltage is V (0) + V . The time constant is defined as
(2)
V0 + V
Vout(t)
V0 + 0.63V
V0
0
Figure 7:
Compare the time constant with the output pole of your system as
1
= ------ C L R out .
p1
(3)
Comments?
Fill in the simulated results in Table 3 below and save all states.
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CommonSource (a)
CommonDrain (b)
CommonGate (c)
Bias DC voltage
Input DC voltage
Output DC voltage
DC gain
Bandwidth
Unity gain frequency ( u )
Phase at u
Time constant
Output voltage range
Input voltage range
Table 3: Simulated results.
voltages controlling i D when changing as for example the width of the bias transistor we
are going to use current mirrors instead. Later in the laboratory we will see how we can
increase the gain in a gain stage by the use of cascodes.
Iin
Iin
M1
Figure 8:
Iout
M3
M4
M1
M2
Iout
M2
The current sources are widely used as bias sources and we shall now add them as bias
sources to our amplifier stages. In order to simplify our circuits, we only use the simple
current mirror (Figure 8a). The other (Figure 8b) will work even better due to the higher
output impedance, but we have more transistors and bias voltages to control. The simple
current mirror also simplifies the understanding of the circuit building block.
As you may have found out through calculations the DC gain of an amplifier stage is given
by
gm
.
A 0 = --------g out
(4)
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At a higher level, we see that we have two approaches to increase the DC gain of the circuit; by increasing g m or decreasing g out . We also know that for a common-source amplifier we have g ds I d and g m ( W L ) I d , which tells us how to increase/decrease
g m / g out . However, we also see that
(W L) I d
(W L)
WL
A 0 = -------------------------------- ---------------------- -------- .
Id
Id
I
(5)
Hence, by decreasing the bias current by a factor of 4 the DC gain is doubled. However, if
we want to reach very high gain we have to make the current very small or the transistor
very large. This is not attractive due to more inherent noise in the circuit and lower unitygain frequency. Instead we use cascodes, and you should now compare the common-source
with and without cascodes as illustrated in Figure 9 (a) and (b).
M3
M3
M2
M6
M5
M2
Ibias2
Vout
Vout
Ibias
Vin
Ibias1
M4
M1
Vin
Figure 9:
M7
M1
M8
We solve the biasing problem of the bias transistor with a somewhat messy method. At this
stage though, the understanding of the operation is more important. We have two current
mirrors as shown in the figure. You can choose whatever current mirror rate, but the mirrors should be matched and give 100 uA in their output branches. The input DC voltages
should be equal to 0.63 V in both cases. The output DC voltages should be 1.65 V (or at
least very close to).
Preparation!
Derive the output DC gain of the stages. Solve exercise 9 in the Exercise Manual.
The schematic of the amplifiers is called ANTIKlab->Cascode. All variables
starting with cs belongs to the simple common-source amplifier. Let the sizes of both input
transistors be equally large using the variable w1.
Use subcircuits for the current and voltage sources and do not forget the capacitive load as
discussed in (Figure 5)
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To simplify your design, start with letting the mirror rates of the current mirrors be unity.
Note that it is important that you have the same current through the amplifier stages.
This may imply that the sizes of the I bias sources are not completely equal.
Let all bulks be connected to the vdd / ground for the PMOS / NMOS transistors.
Use the values shown in Table 4 to start the simulation with.
Single transistor
Cascode transistor
Unit
Input DC voltage
0.63
0.63
Bias DC current
100u
100u
W 1 and W 8
150u
150u
W 2 and W 3
300u
300u
W 4 and W 7
120u
W 5 and W 6
200u
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Single transistor
Cascode transistor
Unit
Input DC voltage
0.63
0.63
Output DC voltage
1.65
1.65
DC current
DC gain
Bandwidth
Unity-gain frequency u
Phase at u
( W L ) 1 ( L = 1 )
( W L ) 2 ( L = 1 )
( W L ) 3 ( L = 1 )
Table 5: Simulation results.
Finally, find the voltage operation ranges for the both amplifier stages. Hence, for which
input and output voltages do the transistors operate in their saturation regions?
Although it is a tedious work to find the ranges, it is very important to determine
them.
13 Intermediate wrap-up
We have now simulated the most simplest amplifier stages. Hopefully, you have also
learnt some simulation techniques. For example
first DC, then AC, finally transient analysis.
You have hopefully learned some useful simulation tricks, such as
use variables and/or parameters
simulate several types of analyses at the same time
You have noticed that when simulating analog circuits, we should not use too ideal components and you have
used subcircuits for the current and voltage sources
added capacitive loads
You have hopefully also noted that
there is a large number of different specification parameters to simulate, such as
settling time, slew rate, unity-gain frequency, phase margin, output conductance,
DC gain, DC voltages, transistor sizes, load capacitances, bias resistors, etc.
the number of parameters to modify in order to meet specification is huge
we have to cut down the number of parameters by fixing bias currents, DC voltages,
etc.
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15 Simulation of Opamps
First, we start with a brief overview of different simulation techniques for the OP/OTA. In
Figure 10 we find several circuits using an OP.
Z2
(b)
(a)
Vin
Z1
Vout
Vin
Vout
VDC
(c)
Vin
Vout
(d)
Vout
Vin
Vos
Figure 10:
(a) Open-loop. Used to find the DC gain, bandwidth, phase margin, unity-gain bandwidth, slew rate (SR), etc.
(b) Closed-loop and inverting amplifier, V out V in = Z 2 Z 1 . Notice that the DC
voltage source has to be used for single-ended OP. Used to find the output range
(OR) but also to simulate the OP in a context.
(c) Common-mode simulation. To investigate the common-mode range.
(d) Offset simulation. Used only when simulating influence of matching errors.
In open-loop configuration we have to be very careful when simulating the circuit, since
the gain is very high. This implies that small changes to transistor sizes, DC voltages, etc.,
will give strange outputs. First, we consider the open-loop simulations, (a) and (c), then we
care about the closed-loop, (b). The common-mode range, i.e., the possible common input
DC points, can be found by simulating the configuration in (c). However, an OP is always
used in a closed-loop configuration. In Figure 10(b) we show the inverting amplifier con-
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16 Differential stage
In high-performance circuits it is advantageous to use differential circuits, since it will
increase the linearity and make the circuit less sensitive to noise. A simple example of a
fully differential circuit is the CMOS differential pair as illustrated in Figure 11. The pair
has a resistive load. Let the bias current be 250 uA and the load resistances, R L , be
8 kohms. The power supply voltage should be 3.3 V and the DC output voltage will end up
at 2.3 V. (Why?) Connect all bulks to ground.
RL
RL
Vout+
VoutVin+
Ibias
M4
Figure 11:
Vbias
M1
M2
Vin-
M3
Preparation!
Derive the differential and common-mode gains of the stage. Solve exercise 11
in the Exercise Manual.
The schematic of the circuit is found in the library
ANTIKlab->diff_stage_resistive_load and the testbench is called
ANTIKlab->diff_stage_resistive_load_TB. We shall now focus on simulating the
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differential as well as the common-mode gain of a circuit, and therefore we need also to
plot the differential output voltage
(6)
V outpos + V outneg
V cm = -----------------------------------------.
2
(7)
The differential output voltage can be obtained by using the converter circuit in
Figure 12a, and the common-mode output voltage using the circuit in Figure 12b.
Vdiffout
Vcmout
posin
posin
Gain =1
Gain =.5
internal
negin
Figure 12:
internal
negin
Gain =-1
Gain =.5
The circuit elements in these circuits are voltage controlled voltage sources. The converters are called differential_out and common_mode_out and they are found in the
ANTIKlab library.
Differential input source
In order to simplify the simulation of the differential input signal we are going to use
another subcircuit. Since the input signal can consist of a DC operating point, differential
signal, and common-mode signal it is convenient to have a sub circuit as illustrated in Figure 13.
Voutp
Voutn
Gain=0.5
Gain=0.5
Vdiff
Vdiff
common
Vcm
Figure 13:
This circuit together with the concept of an internal resistance and capacitance of the voltage sources is found in the library ANTIKlab->differential_input.
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Start to simulate. Size the transistors so that V bias 0.7 V and the width of the input transistors are 200 um.
Find the DC operating point for maximum gain! All transistors must be saturated. Assume
that you sweep the input common DC level (the variable Vcm), what do you actually see at
the outputs?
Use this operation point when simulating the small-signal behavior of the circuit. Further,
determine the bandwidth, DC gain, phase-margin, etc., for the differential output signal.
Common-mode signals
Further, we have the common-mode range (CMR). This describes the possible voltage
range for the input DC voltage (of course you should have the same DC voltages at the
gates of the input transistors). Determine the CMR by sweeping the input DC voltage, use
the subcircuit from Figure 12b to plot the common-mode output signal.
Derive the common-mode rejection ratio (CMRR). CMRR is a measure of how much the
common-mode input voltage is amplified compared with the differential input signals, i.e.,
A diff
CMRR = ----------A cm
(8)
and should be as large as possible. Unfortunately A diff and A cm must be simulated in two
different circuits, but can, with the correct schematic, be simulated in the same run (use
subcircuits). Apply a differential input to the first differential stage to get A diff and a common-mode signal to the second differential stage (see Figure 10c) to get A cm . Note that we
in both cases are interested in the differential output (Eq. 6).
Determine the bandwidth, unity-gain frequency and CMRR at low frequency.
Influence from power supply
To determine the disturbance from the power supply lines (or bias wires) on the circuit performance we have the power supply rejection ratio (PSRR) measure. This is simulated by
adding a sinusoidal source to the positive and negative supplies. We then measure the
transfer functions from these sources to the output. These functions are compared with the
differential gain of the circuit. For the positive supply we only have to add an AC source in
series with the V dd symbol that is connected to the differential gain stage
Vsin with the following voltage AC 1 and DC 0
Notice that you have to cancel all other AC sources in your schematic.
Simulate and determine the transfer function from the power supply to output.
For the ground node, add a voltage source with 1 volt ac and no DC voltage. The voltage
source should be connected between the ground and the AGND node of the differential gain
stage. Modify the schematic so that you are able to measure the influence of AC sources
from the ground to the output.
Finally, PSRR is determined by the worst case, i.e., is the positive or negative supply dominating the induced disturbance. Determine the PSRR for the circuit.
Differential stage with current mirror load and single-ended output
The circuit we have simulated is a differential-pair with passive load. We know since previously that passive load will give us a poor gain. Now, we add an active load in terms of a
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PMOS current mirror as illustrated in Figure 14. Notice now that the circuit is single-
M3
M4
Vout
Vin+
M1
Vbias
Figure 14:
M2
Vin-
M5
ended.
Preparation!
Derive the differential and common-mode gains of the stage. Solve exercise 10
in the Exercise Manual.
The same set up as earlier is used, but the testbench is called
diff_stage_single_ended in the ANTIKlab library, hence the same bias current and
same transistor sizes. Your objective is now to determine the sizes of M3 and M4 that maximizes gain and voltage swing at the output. You have the DC input voltage to vary as well.
Simulate and determine the
possible input and output swing
slew rate
common-mode gain
differential gain
common-mode rejection ratio
Differential stage with transistor load and fully-differential
The next issue is to increase the gain even more and make the circuit fully differential.
Consider the circuit in Figure 15. Find the bias voltages by using current mirrors for biasing. The current through M5 should be 250 uA and use the same transistor sizes as before.
Simulate the stage and complete the table below. The circuit can be found in the testbench
ANTIKlab->diff_stage_fully_differential.
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VbiasP
M3
M4
Vout+
VoutVin+
M1
VbiasN
Figure 15:
M2
Vin-
M5
If you would like to double the -3dB frequency, what would you do? (Of course, we do not
change the load capacitance). What should you do to double the DC gain?
CONGRATULATIONS!
You have just made your first operational transconductance amplifiers. Hopefully you
have seen how the list of things to simulate has grown very fast. This will hopefully inspire
you to start to make template files and use lots of parameters, etc., to speed up your simulations.
However, the gain of the amplifiers in the previous is not high enough for our applications.
We have to use other tricks, such as multi-stage amplifiers in order to have good operational amplifiers (OP) and operational transconductance amplifiers (OTA).