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EXISTING SYSTEM:
Numerous researchers have worked on transform core designs, including discrete cosine
transform (DCT) and integer transform, using distributed arithmetic (DA), factor sharing (FS),
and matrix decomposition methods to reduce hardware cost. The inner product can be
implemented using ROMs and accumulators instead of multipliers to increase the area cost.
Low throughput
High cost
PROPOSED SYSTEM:
The proposed CSDA algorithm combines the FS and DA methods. By expanding the
coefficients matrix at the bit level, the FS method first shares the same factor in each coefficient;
the DA method is then applied to share the same combination of the input among each
coefficient position. The main strategy aims to reduce the nonzero elements using CSDA
algorithm.
High-throughput rate
Low cost
SOFTWARE REQUIREMENT:
ModelSim6.4c
Xilinx 9.1/13.2
HARDWARE REQUIREMENT:
FUTURE ENHANCEMENT:
We will modify the proposed system by reducing the Area of converting one
dimensional to two dimensional core designs.
High-Throughput Multi Standard Transform Core Supporting MPEG/H.264/VC-1 Using
Common Sharing Distributed Arithmetic
ALTERNATE TITLES:
Title 1: Efficient High-Throughput Multi Standard Transform Core realization on FPGA
Title 2: High-Throughput Multi Standard Transform Core Implementation based on
Common Sharing Distributed Arithmetic
Title 3: Implementation of High-Throughput Multi Standard Transform Core Using
Verilog HDL
PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)
Second Phase:
Remaining 40% of Base Paper with Future Enhancement (Modification)