FLEXIBLE INTEGER DCT ARCHITECTURES FOR HEVC

ABSTRACT:
We present high throughput and power-efficient architectures for the implementation of
integer DCT of different lengths to be used in upcoming High Efficiency Video Coding (HEVC).
We have shown that efficient matrix multiplication schemes could be used to derive parallel
architectures for 1-D integer DCT of different lengths. Apart from that we have proposed three
different flexible architectures which could be used for implementing the DCT of any of the
prescribed lengths such as 4, 8, 16 and 32, each having particular advantage in terms of area,
delay, or power. The proposed architectures can provide higher throughput at a lower operating
frequency than the existing architectures for HEVC. Using FPGA Spartan 3 and it are
implemented by Verilog language.

EXISTING SYSTEM:
In Existing Radix algorithm generally have a regular computational structure which
reduces implementation complexity. However, due to their recursive nature radix algorithm are
difficult to realize pipeline and are not suitable for high speed application. Although fast
algorithms can significantly reduce the computational complexity of computing the DCT,
floating-point operations are still required. Despite their accuracy, floating-point operations are
expensive in terms of circuitry complexity and power consumption.

EXISTING SYSTEM ALGORITHM:

Radix Algorithm

EXISTING SYSTEM DRAWBACKS:

Compare to proposed system

Low area efficient

High Power Conception

High Computational complexity

PROPOSED SYSTEM:
We present the generalized architecture for N-point integer DCT based on optimized
hardware-oriented algorithms for different lengths. Besides, three flexible architectures for the
implementation of integer DCT of any of the prescribed lengths of HEVC are proposed. The
proposed architectures provide a higher throughput at a lower operating frequency than existing
architectures.

PROPOSED SYSTEM BLOCK DIAGRAM:

Proposed architecture of 8-point integer DCT

PROPOSED SYSTEM TECHNIQUE:

8 Point integer DCT Method

PROPOSED SYSTEM ADVANTAGES:

Very low circuit complexity

Area Efficient

SOFTWARE REQUIREMENT:

ModelSim6.4c

Xilinx 9.1/13.2

HARDWARE REQUIREMENT:

FPGA Spartan 3

REAL TIME APPLICATION:

Geospatial remote sensing & Traffic cameras

Automatic surveillance & Homeland security

Automotive industry

Multimedia wireless sensor networks

FUTURE ENHANCEMENT:
We will modify the Flexible architectures for integer DCT computation unit.

ALTERNATE TITLES:

Flexible Integer DCT Architectures for High Efficiency Video Coding

High Efficiency Video Coding Flexible Integer DCT Architectures using Verilog HDL.

An FPGA Implementation of Flexible Integer DCT Architectures

PROJECT FLOW:

First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:
Remaining 40% of Base Paper with the Future Enhancement (Modification).