Beruflich Dokumente
Kultur Dokumente
AGENDA
Introduction
Who is MIPI Alliance
What MIPI Do
MPhy Introduction
TX- Key parameters
RX-Key parameters
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
What MIPI Do
45+ interface specifications released to date
MIPI has full ecosystem of members to support
many types of mobile and mobile-influenced
designs
Specs are widely adopted for designs across the
mobile industry and beyond
255 members worldwide
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MIPI Overview
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Camera
Display
UniPortD
UniPortM
Audio/
Data/Ctrl
Control
BB-RF 3G
BB-RF 4G
IPC
Mass
Storage
Trace
Gigabit
Trace
Software
NAND
SW
IMF
DDB
App-control
DCS
ICLC
ICLC
OST FrameWork
SPMI :
RF-FE:
DSI-1
Transport
PHY
6
App-data
App-data
App-data
CSI-2
Power
Mgmt.
D-PHY
D-PHY
serial I/F
serial I/F
PIE
Conf
UniPro
1.0
UniPro
1.5 and
2.0
D-PHY
M-PHY
serial I/
F
serial I/
F
SLIMbus
RF
Control
DigRF
3G
DigRF
4G
Conf
HSI
CMOSbased
CMOSbased
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY
serial I/F
CMOS
UniPro
1.5 and
2.0
OST
TWP
STP
UniPro
1.5 and
2.0
M-PHY
PTI
M-PHY
serial I/F
CMOS
serial I/F
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Features
Custom Clock
Self Consistent
Aggressive Power Management
Optical/Repeater ready
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-TX =
TX
Module
M-RX =
RX
Module
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY V1.0
Power On
HS Burst
LS Burst
Stall
Sleep
Hibern8
recovery
latency
Disable
power
Hibern8
25mW
1mW
ns
10mW
us
100uW
0.1-1ms 10uW
Sleep
LS Burst
Stall
HS Burst
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
M-PHY States
M-PHY Configuration
LOCAL
18
PHY
E/O
E/O
O/E
O/E
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PHY
PROT
REMOTE
M-PHY Configuration
LOCAL
19
PHY
E/O
E/O
O/E
O/E
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PHY
PROT
REMOTE
M-PHY Configuration
??
LOCAL
20
PHY
E/O
E/O
O/E
O/E
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PHY
PROT
REMOTE
M-PHY Configuration
??
LOCAL
21
PHY
E/O
E/O
O/E
O/E
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PHY
PROT
REMOTE
M-PHY Configuration
??
LOCAL
22
PHY
E/O
E/O
O/E
O/E
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PHY
PROT
REMOTE
M-PHY Configuration
??
LOCAL
23
PHY
E/O
E/O
O/E
O/E
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
PHY
PROT
REMOTE
1.45Gbps
M-PHY v1
M-PHY supports :
Bandwidth support
- HS GEAR 1
- PWM G0-G3
- SYSBURST
Bandwidth Provisional
- HS-Gear 2
- PWM G4-G5
2011
2012
2013
2014
v1.
0
v2.0
v3.0
v4.0
2.9Gbps
M-PHY v2
Bandwidth support
- HS GEAR 1 & 2
- PWM G0-G5
-SYSBURST
Bandwidth Provisional
- HS-Gear 3
- PWM G6-G7
DigRF v4
5.8Gbps
M-PHY v3
Bandwidth support
- HS GEAR 1,2 & 3
- PWM G0-G7
-SYSBURST
Bandwidth Provisional
HS-Gear 4
CSI-3/Mobile Express
UFS
LLI/SSIC
24
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
11.6Gbps
M-PHY v4
Bandwidth support
- HS GEAR 1, 2, 3 & 4
- PWM G0-G7
- SYSBURST
25
DPHY
MPHY
Unidirectional or halfduplex
<30 cm PCB, flex,microcoax
dual-simplex
< 30 cm PCB, flex,micro coax,<1.2 m
cable, optical
~ 1.25, 2.5, 5 Gb/s (A series); ~ 1.5, 3,
6 Gb/s (B series)
HS Mode
LP Mode
< 10 Mb/s
10k-600Mb/s
Electrical
signaling
HS Mode
SLVS - 200 mV
SLVS - 200 mV
LP Mode
LVCMOS - 1.2V
HS Clocking method
Embedded Clk
HS Line coding
None or 8b-9b
8b-10b
Power Energy/bit
Low
Receiver Complexity
CDR required
LP only PHYs
Disallowed
Allowed
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MIPI M-PHY IP
Key Feature List
High-Speed data transfer per lane
Multiple transmission speed ranges and rates per BURST mode to further scale
bandwidth to application needs; Mitigates interference problems.
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
MPHY TX Architecture
CLK from CMN
Block
HSCLK
LSCLK
RMMI Interface
CFGCLK
HS / LS
FSM
DATA
Interface
PPI
Interface
CTRL
Interface
TX_DP
DATA
Serializer
&
Clock Gen
DATA
PATH
BIST
CONTROL
LOOPBACK
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
BIST
HSCLK
LSCLK
Drive
r+
Term
DRIVERS
TX_DN
MPHY RX Architecture
REFCLK
RX_DP
RX_DN
PREAM P
+
TERM
DATA
De Se rialize r
&
CDR
HS / LS
FSM
LOOPBACK
34
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
SYMCLK
DATA
DATA
PATH
CONTROL
DATA
Inte rface
PPI
Inte rface
CTRL
Inte rface
RMMI Interface
CFGCLK
MPHY RX Architecture
REFCLK
HS Amp for
PREAM P
G1/G2/G3
+
RX_DN
TERM
modes
RX_DP
DATA
De Se rialize r
&
CDR
LOOPBACK
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
DATA
Inte rface
SYMCLK
DATA
DATA
PATH
CONTROL
35
HS / LS
FSM
PPI
Inte rface
CTRL
Inte rface
RMMI Interface
CFGCLK
MPHY RX Architecture
REFCLK
LP Amp for
PREAM P
low-speed
+
RX_DN
TERM
modes
RX_DP
DATA
De Se rialize r
&
CDR
LOOPBACK
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
DATA
Inte rface
SYMCLK
DATA
DATA
PATH
CONTROL
36
HS / LS
FSM
PPI
Inte rface
CTRL
Inte rface
RMMI Interface
CFGCLK
MPHY RX Architecture
REFCLK
CONTROL
LOOPBACK
37
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
HS / LS
FSM
DATA
Inte rface
SYMCLK
DATA
DATA
PATH
PPI
Inte rface
CTRL
Inte rface
RMMI Interface
CFGCLK
HS-Gear1
(Mandatory)
AND
HS Mode
HS-Gear2
(Optional)
AND
Data Transfer
Modes
AND
HS-Gear3
(Optional)
PWM Mode
(Type-1)
LS Mode
OR
SYS mode
(Type-2)
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
BIST Details
TXP
Encoding
+ Serializer
TXN
Input
Latch
BIST
Select
to
PPI/RMMI
BIST_FLAG
39
Output
Latch
RXP
Decoding
+ Deserializer
BIST
Checker
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
RXN
BIST Features
Option to
generate and check various patterns like PRBS, CRPAT, CJTPAT
etc.
run the BIST infinitely or in a burst mode.
control the burst length.
control the idle time between bursts, within limits of the MPHY
specification.
send patterns that repeat in every burst or differ in every burst.
inject a single-bit error at a programmable point in the data stream.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
BIST Modes
Burn-in Mode: Stress testing
by putting TX and RX in
maximum power consumption
modes with the help of
external loopback.
Loopback Mode: Provides a
transparent bit-by-bit path
from an M-RX serial input to
an M-TX serial output.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Jitter Test
Jitter separation is a time consuming process if Spectral
method is followed to get the exact Jitter separation.
Dual Dirac method can be used to get the Jitter split much
faster and if lesser number of samples can be taken and
extrapolate the RJ numbers to reduce the time much lower.
HS default mode is terminated mode and this has to be a
100ohm differential termination across Dp and Dn. This has
to be measure at the pin. This can be achieved only through
probing directly on a 100ohm terminated very near to the Dp/
Dn pin using an active probe.
Active probes normally have a high noise floor which adds
RJ to the measurement and this is reflected on the TX
measurements
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
G3 Eye Diagram
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
RX calibration Setup
Physical Calibration Setup
Pattern
Generator
+ Deemphasis
+ Jitter
Sources
Replica
Channel
Active Probe
Oscilloscope
SMA Cables
DUT RX
50
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Total Jitter(UI)
1.4
1.2
1
Spec TJ
0.8
0.6
0.4
0.2
0
0.8
10
26
SJ Frequency(MHz)
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
100
166.4
Jitter Components
RX input should have following components
Low frequency Jitter component as shown in the Jitter Mask
Low frequency RJ
High Frequency RJ
High frequency SJ tone
ISI to meet the Spec defines channel loss
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Questions???
54
2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
Thank You
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2012 Cadence Design Systems, Inc. Cadence confidential. Internal use only.