Beruflich Dokumente
Kultur Dokumente
de Comunicatii (APC)
Data transmission
Tx Data
10110 NIC
NIC = Network
Interface Card
Tx Signal
Rx Signal
Rx Data
10110
NIC
Transmission
medium
Octavian Catrina
0 1
Tb
t
RxC 0 1 0 1 1 0
0 1
Tb
Tx
0101100
TxC
RxC
RxC must be synchronized with TxC
Tx: Transmitter
TxC: Transmitter clock
Rx: Receiver
RxC: Receiver Clock
Try to imagine a data encoding with more levels, based on the same
principle. Example: 4 signal levels, 2 bits/level.
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Modulation techniques
Data
Baseband
transmission
(truncated signal
bandwidth)
f
Carrier
signal
Amplitude
modulation
(ASK = Amplitude
Shift Keying)
2nd Carrier
signal
Frequency
modulation
(FSK = Frequency
Shift Keying)
Phase
modulation
(PSK = Phase
Shift Keying)
f
t
f
t
f
Try to imagine a data encoding with more levels, based on these techniques.
E.g., 4 phase values, or combined amplitude and phase modulation.
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Bit rate
1 bit in Tb seconds
Bit rate: Rb= 1/Tb bit/s.
Example: Tb = 1s Rb = 1 Mbit/s.
t
0 1 0 1 1 0 0 1
Tb
Packet rate
Packets with N bits transmitted at rate Rb
Packet rate: Rp = 1/Tp = Rb/N packet/s.
Example: N = 1Kbit, Rb = 1 Mbit/s Rp = 1000 packet/s.
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Propagation delay
t0
01011
Tx
t0+Td
Propagation delay Td= d/c
Distance d
Rx
t
01011
Tx: transmitter
Rx: receiver
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Send 1
DATA 1
Transfer
T = Tp+Td
Transmission
Tp = L/R
Propagation
Td = D/V
Receive 1
ACK 1
Send 2
DATA 2
R = Data rate (bits/sec)
L = Packet length (bits)
D = Distance
V = Signal propagation
speed
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Receive 2
ACK 2
A
Send1-4
B
DATA 1
DATA 2
Receive1
DATA 3
ACK 1
DATA 4
Receive2
ACK 2
Receive3
ACK 3
Receive4
ACK 3
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Synchronization
Bit synchronization
Frame synchronization
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Bit synchronization
Principle
Manchester
encoding
Clock
bit 0 = low-to-high signal transition.
bit 1 = high-to-low signal transition.
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t0
0101
1
Distance d
Tx
t0+Td
Rx
???
Tx: transmitter
Rx: receiver
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EMI/RFI noise
Crosstalk signal
Reflection signal
Tx
Crosstalk
01011
Rx
Tx
???
EMI/RFI
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t
RxC 0 1 0 1 1 0
0 1
Tb Encoding: datasignal
0101100
Tx
Tb Decoding: signaldata
Decoding errors
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0101100
Rx
TxC
Rx clock synchronized with Tx clock
0 1
RxC
Tx
TxC 0
t
1
Rx
RxC
t
0
1 1 0
Errors !
1
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Theoretical limits
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Data networks
Challenges
Solutions
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Interconnection devices
forward data on the links
towards the destination:
Switching and routing
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Multiplexing
Using the same transmission medium for
multiple simultaneous communications
...
Multiplexed
link
Bandwidth (Hz)
Time
123456 123456 123456 123456
...
6
5
4
3
2
1
Bandwidth (Hz)
Time
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R bits/s
FDM
mux
FDM
demux
R/3 bits/s
frequency
(signal bandwidth)
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Synchronous TDM
Fixed bandwidth allocation. Good for constant bit-rate streams.
Inefficient for variable bit-rate, bursty streams. Simple, cost effective.
Fixed size slot. Fixed cycle: N slots (3)
R1 R/3 bits/s
R2 R/3 bits/s
R3 R/3 bits/s
R bits/s
Demultiplexer
R bits/s
R3 bits/s
R1+R2+R3 R
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E.g.: First In
First Served
Header
Data
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Signaling channel
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E1
E2
E2
E3
64Kbps
2Mbps
8Mbps
E0
E3
32Mbps
32Mbps
8Mbps
2Mbps
64Kbps
Signal Bit-rate
Channels
Signal Bit-rate
E0
64 Kbps 1 E0
DS0
64 Kbps
E1
2.048 Mbps 32 E0
DS1 (T1) 1.54 Mbps
E2
8.45 Mbps 4 E1 (128 E0) DS2 (T2) 6.3 Mbps
E3
34 Mbps 4 E2 (16 E1) DS3 (T3) 44.8 Mbps
E4
140 Mbps 4 E3 (64 E1)
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E1
Channels
1 DS0
24 DS0
4 DS1 (96 DS0)
7 DS2 (28 DS1)
-
Obsolete
E1/E3, T1/T3 still used.
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Features
STS-n link
ADM
STS-n
SONET (ANSI)
Bit-rate
STS-1, OC-1
51.84 Mbps ( 50 Mbps)
STS-3, OC-3
155.52 Mbps ( 150 Mbps)
STS-12, OC-12
622.08 Mbps ( 600 Mbps)
STS-24, OC-24
1244.16 Mbps ( 1.25 Gbps)
STS-48, OC-48
2488.32 Mbps ( 2.5 Gbps)
STS-192, OC-192 9953.28 Mbps ( 10 Gbps)
SDH (ITU-T)
STM-1
STM-4
STM-16
STM-64
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Circuit switching
Circuits
Circuit switches
Switch tiny, fixed-size data units between time slots on
synchronous TDM links, using mapping stored at circuit setup.
A
B
Synchronous TDM
multiplexors
S1
S2
S3
C
D
Synchronous TDM
demultiplexors
E
F
G
H
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SONET/SDH networks
OC-n
DCC
ADM
OC-n
DCC
TM
Hub
TM
OC-N
ADM
TM
OC-n ADM
OC-n
TM
ADM
OC-n
OC-n
DCC
OC-n
DS--n
TM
DS-n
STS-n
(ATM,
IP)
TM - Terminal Multiplexer.
ADM - Add/Drop Multiplexer.
DCS - Digital Cross-Connect.
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Packet switching
Packets
Encapsulated data units with routing information in header.
Packet switches
Switch variable-size packets between asynchronous TDM links
based on information in the header and forwarding tables.
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Logical path set up between network nodes across a packetswitched network. Identified on each link by a VC identifier (VCI).
Phases: VC setup, communication, VC release.
Switching table
Indicates how to forward packets
on VCs: maps VCI on each input
link to output link and next VCI.
QoS support
Ordered packet delivery.
Can guarantee QoS by
reserving resources on VC
(bandwidth, delay).
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S2
S6
1
3
S3
43
2
16
24
2
1
S1
VCI
data
4
2
S5 19
S4
Switching tables
Packet switch 1
Packet switch 3
Packet switch 5
Input
Output
Link VCI Link VCI
2 16 3 24
... ... ... ...
Input
Output
Link VCI Link VCI
1 24 2 43
... ... ... ...
Input
Output
Link VCI Link VCI
3 43 2 19
... ... ... ...
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Datagrams
Standalone packets, forwarded independently of each other,
based on source and destination addresses in the header.
Routing table
Gives next hop on the path
to each known destination.
R2
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yx
R1
x
yx
R3
R4
yx
DA,SA
yx
yx
R6
y
yx
data
Routing tables
Router R1
DA
y
...
R5
Next hop
R3, R4
...
Router R3
DA
y
...
Next hop
R6
...
Router R6
DA
y
...
Next hop
...
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Distance D
DATA
Send
Distance D
DATA
Compare with
example 1.
Receive
ACK
Receive
ACK
ACK
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Distance D
DATA
Send
DATA
Distance D
DATA
Receive
ACK
Compare with
example 3.
Receive
ACK
ACK
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Frame Relay
switch
Frame Relay
WAN
DLCI=4
DLCI=1
DLCI=9
DLCI=4
Frames
DLCI=2
DLCI=1
DLCI=5
DLCI=7
DLCI=3
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Output
Port DLCI
4
8
4
6
3
11
Input
Port DLCI
1
8
1
6
Output
Port DLCI
4
12
4
5
12
7
6
Input
Port DLCI
2
6
Output
Port DLCI
3
9
Input
Port DLCI
1
9
Output
Port DLCI
2
9
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Example: ATM
Video
/Audio
Voice Data
PBX
Cells:
5 octets
header,
48 octets
payload.
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Description
AAL
CBR
(Constant Bit Rate)
VBR-RT (real-time
Variable Bit Rate)
VBR-NRT
(non real-time VBR)
UBR
Best effort service. No traffic and QoS
(Unspecified Bit Rate) commitment. E-mail, ftp.
ABR
(Available Bit Rate)
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Type 1
Type 2
Type 3/4
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Example: MPLS
Datagram-oriented (IP).
Connection-oriented (FR, ATM) - virtual circuits (VC).
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i1
i2
i2
R1
DA=10.5.1.1
i3
R2
i1
i1
DA=10.5.1.1
DA=10.5.1.1
i2
R3 10.5.0.0/16
DA=10.5.1.1
i1
R4
10.4.3.0/24
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At Edge:
Ingress LSR
Classifies IP packets
& Adds labels (MPLS
header)
IP
IP
i1
R1
Edge LSR
L1
IP
i2
At Edge:
Egress LSR
Removes labels
(MPLS header) &
Forwards IP packets
L2
LSP
i3
IP
i1
R2
i1 LSR
LSR
i2
R4
i3
IP
L3
i1
R5
Edge LSR
LSR
MPLS domain
i1
i2
R3
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