Sie sind auf Seite 1von 21
i-1 PrimeTime: Introduction to Static Timing Analysis Workshop Synopsys Customer Education Services © 2002

i-1

PrimeTime: Introduction to Static Timing Analysis Workshop

Synopsys Customer Education Services

© 2002 Synopsys, Inc. All Rights Reserved

Services © 2002 Synopsys, Inc. All Rights Reserved Synopsys 34000-000-S16 Welcome 34000-000-S16 PrimeTime:
Services © 2002 Synopsys, Inc. All Rights Reserved Synopsys 34000-000-S16 Welcome 34000-000-S16 PrimeTime:
Services © 2002 Synopsys, Inc. All Rights Reserved Synopsys 34000-000-S16 Welcome 34000-000-S16 PrimeTime:

Synopsys 34000-000-S16

Welcome

34000-000-S16

PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-1

Unit i: Welcome

First Things First

i-2

Welcome and Introductions Materials you should have:

Student Guide Lab Guide PrimeTime Quick Reference Synopsys Online Documentation (SOLD) CD

Breaks Facilities

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-2

Unit i: Welcome

Workshop Goal i-3 Use Use PrimeTime PrimeTime to to perform perform Static Static Timing Timing
Workshop Goal
i-3
Use Use PrimeTime PrimeTime to to perform perform Static Static Timing Timing Analysis Analysis (STA) (STA)
on on a a “Functional “Functional Core” Core” prior prior to to Place Place and and Route Route (P&R). (P&R).
Obtain Obtain the the prerequisite prerequisite knowledge knowledge to to attend attend the the
“PrimeTime: “PrimeTime: Chip Chip Level Level STA” STA” workshop. workshop.
A/D
DSP
CODEC
Processor_CORE
MPEG
USB
RAM
Functional Core Core Clock
Synopsys 34000-000-S16
Welcome
PrimeTime: Introduction to Static Timing Analysis

Design Assumptions:

1. STA is performed on the Functional core only; Block level STA has been done in DC. (See Flow Diagram)

2. No scan chains yet (Flow diagram in PT:Chip level STA workshop)

3. Functional Core routing parasitic RCs (detailed SPEF) and sub block WLMs are available from early design planning (Chip level floor plan)

4. No clock tree synthesis yet (Flow diagram in PT:Chip level STA workshop)

5. Blocks may be either synthesized netlist or QTMs (will be covered if class time permits)

6. Functional Core has Logical hierarchical partitions (blocks)

7. No I/O pads, no BSD, no clock generation logic yet (Definition of Functional Core)

8. Chip specification is available (in Constraints modules)

9. Multiple Synch/Asynch clocks (in Constraints modules)

10. Multicycle paths (in Constraints modules)

11. Hold Time analysis is performed using Worst case PVT (as opposed to Best case PVT) (in Constraints modules)

12. No case analysis (absence of scan chains); no functional modes (Flow diagram in PT:Chip level STA workshop -- although it may apply to Functional CORE but is not discussed in this PT: ISTA)

PrimeTime: Introduction to Static Timing Analysis

i-3

Unit i: Welcome

Workshop Target Audience

i-4

Design or Verification engineers who perform STA at the “functional core” level

Little or no formal experience with PrimeTime

Little or no formal experience with Design Compiler

Planning to take the “PrimeTime: Chip level STA” workshop

PrimeTime:

ISTA

CHIP Synthesis (Design Compiler)

You are here
You are here
ISTA CHIP Synthesis (Design Compiler) You are here PrimeTime: CHIP Level Synopsys 34000-000-S16 Welcome

PrimeTime:

CHIP Level

(Design Compiler) You are here PrimeTime: CHIP Level Synopsys 34000-000-S16 Welcome PrimeTime: Introduction to

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

Design or Verification engineers who perform STA at the “functional core” level. In addition to block level STA, you will handle functional core integration.

Little or no formal experience with Design Compiler. If you have taken “CHIP Synthesis” or have experience using Design Compiler, do not attend this workshop: Take “PrimeTime: Chip Level STA”

If your expectation is to learn DC as you’re expanding your portfolio to include synthesis, you should take the CHIP Synthesis workshop next and then PrimeTime: Chip Level STA.

“PT:Chip Level STA Workshop” focuses on final, full chip, post route STA in order to achieve Timing closure.

PrimeTime: Introduction to Static Timing Analysis

i-4

Unit i: Welcome

What is Functional Core on a CHIP?

i-5

What is Functional Core on a CHIP? i-5 TOP MID CLOCK-GEN PLL FUNC_CORE Synthesized Synthesized JTAG/BSD
TOP MID CLOCK-GEN PLL FUNC_CORE Synthesized Synthesized JTAG/BSD Block1(wlm) Block2 Logic Synthesized RAM
TOP
MID
CLOCK-GEN
PLL
FUNC_CORE
Synthesized
Synthesized
JTAG/BSD
Block1(wlm)
Block2
Logic
Synthesized
RAM (Timing
ASYNCH
Block3
model)
LOGIC

Functional CORE constitutes “most” of the CHIP containing:

Synthesized logic blocks (Gate level netlist) and Models (RAMs)

Functional core constraints are derived from Chip-level constraints

Functional core level parasitics are extracted

Extraction is done after a CHIP level floorplan and global routing

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

Welcome PrimeTime: Introduction to Static Timing Analysis Parasitics are supplied in SPEF (Standard Parasitic

Parasitics are supplied in SPEF (Standard Parasitic Extraction Format).

At the full-chip level one must consider the following issues:

Model clock generation circuitry Analyze latch-based versus flip-flop design styles Functional vs. Test modes (Case analysis) Analyze PVT corners

These issues are addressed in the “PrimeTime: Chip level STA” workshop.

PrimeTime: Introduction to Static Timing Analysis

i-5

Unit i: Welcome

Functional Core Integration – Pre-Layout

i-6

Fully synthesized Functional Core.

Chip-Level floorplan and constraints.

Functional core inter- block RC parasitics extracted.

Write Top-Level constraints and Units 4-6 exceptions Design Compiler Read required files Resynthesis Unit 3
Write Top-Level
constraints and
Units 4-6
exceptions
Design Compiler
Read required files
Resynthesis
Unit 3
Errors/
Fix data
yes
Warnings?
no
Generate STA
Timing
Units 1,8
Reports
violations
Place&Route

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

After synthesis of all sub-blocks, perform Chip level floorplan, global routing and extract the parasitic RCs between blocks within the Functional core.

QTMs (or Timing models) may be used for the blocks for which synthesized gate level netlist is not available.

Day-1: Objective: Using the basic 5 step STA flow, constrain all the Register to Register (Internal) timing paths within the functional core

Day-2: Objectives:Using the 5 step STA flow, constrain all the I/O (interface) timing paths within the functional core and apply the necessary single clock cycle timing exceptions

PrimeTime: Introduction to Static Timing Analysis

i-6

Unit i: Welcome

PT Compatibility with other Tools

i-7

Design Compiler Mapped netlist (using WLM) Placed netlist CHIP Architect PrimeTime STAMP Parasitics, SDF PathMill
Design Compiler
Mapped netlist
(using WLM)
Placed netlist
CHIP Architect
PrimeTime
STAMP
Parasitics, SDF
PathMill
3 rd Party Layout

Physical Compiler

SDF PathMill 3 rd Party Layout Physical Compiler Synopsys 34000-000-S16 Welcome PrimeTime: Introduction to
SDF PathMill 3 rd Party Layout Physical Compiler Synopsys 34000-000-S16 Welcome PrimeTime: Introduction to

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-7

Unit i: Welcome

What Will Be Covered

i-8

Performing basic 5 step Static Timing Analysis (STA) flow on a functional core prior to P&R using PrimeTime GUI and shell (Units 1-3)

Applying required constraints and exceptions and checking for missing constraints and ignored exceptions (Units 4-6)

Creating a Quick Timing Model (Unit 7)

Analyzing in detail for timing, design rules and timing bottlenecks (Unit 8)

Synopsys 34000-000-S16

rules and timing bottlenecks (Unit 8) Synopsys 34000-000-S16 Welcome PrimeTime: Introduction to Static Timing Analysis

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-8

Unit i: Welcome

Workshop Prerequisites

i-9

Workshop Prerequisites i-9 Synopsys 34000-000-S16 Understanding of digital IC design Familiarity with UNIX, X-Windows and

Synopsys 34000-000-S16

Understanding of digital IC design

Familiarity with UNIX, X-Windows and Unix-based text editor

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-9

Unit i: Welcome

Agenda: Day One

i-10

DAY 1111
DAY
1111
Unit Register to Register Paths Lab
Unit
Register to Register Paths
Lab

0i

Welcome

         

1

Introduction

to

Static

Timing

Analysis

1 Introduction to Static Timing Analysis
2 Writing Basic Tcl Constructs in PT
2 Writing Basic Tcl Constructs in PT
3 Reading Data
3 Reading Data
4 Constraining Internal Reg-Reg Paths

4

Constraining

Internal

Reg-Reg

Paths

4 Constraining Internal Reg-Reg Paths

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

Unit 1 Objective:

Is to introduce Static Timing Analysis in PrimeTime by: Defining the 2 steps performed by a Static Timing Analyzer; Understanding under the hood calculation of cell and net delays based on NLDM (Non-Linear Delay Model) and WLM (Wire Load Model); Listing 4 types of timing paths; Identifying the path with the WNS (worst negative slack) or longest delay using the report_timing command; Interpreting results of the report_delay_calculation command and for cell and net timing arcs and Finding specific topics in SOLD using key word search.

Unit 2 Objective:

Is to find Tcl syntax errors using the Tcl Syntax checker, to fix these errors and to obtain command and variable syntax information.

Unit 3 Objective:

Is to create a basic PT setup file, read all the required files for STA and resolve errors and warnings associated with reading the files.

Unit 4 Objective:

Is to create a Tcl script, which fully constrains internal Register-to-Register paths by Applying clock constraints and design environmental attributes; Modeling multiple synchronous/asynchronous clocks, Modeling pre-layout non ideal clocks, Invoking appropriate report commands to verify the correctness of constraints and Invoking a report to verify the completeness of constraints.

PrimeTime: Introduction to Static Timing Analysis

i-10

Unit i: Welcome

Agenda: Day Two

i-11

DAY 2222
DAY
2222
Unit I/O Paths and Exceptions Lab
Unit
I/O Paths and Exceptions
Lab
5 Constraining I/O Interface Paths

5

Constraining

I/O

Interface

Paths

5 Constraining I/O Interface Paths
6 Specifying Timing Exceptions
6 Specifying Timing Exceptions
7 Introduction to Timing Models (QTM) 8 Performing STA
7 Introduction to Timing Models (QTM)
8 Performing STA
9 Summary
9 Summary
10 Customer Support
10 Customer
Support

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

Unit 5 Objective:

Is to create a Tcl script which fully constrains the Input/Output interface paths by applying port constraints and environmental attributes, modeling I/O data paths between multiple synchronous and asynchronous clock domains, modeling pre-layout non ideal clock effects, Invoking appropriate report commands to verify the correctness of constraints, Invoking a report to ensure the completeness of constraints and Identifying the effect of constraints on the path reported by a timing report.

Unit 6 Objective:

Is to Efficiently constrain a design for non-single-clock cycle behavior by Defining Timing exceptions, Modeling multi cycle path, Modeling logically false paths, Writing efficient constraints to model the above and Identifying any ignored exceptions and remove them.

Unit 7 Objective:

Is to Create a Quick Timing model using a given specification for use in PT by Defining what QTM is, Writing a QTM script to create a QTM library cell for the given specification and Modifying the link_path to use the QTM just created.

Unit 8 Objective:

Is to Apply three techniques in a systematic approach to analyze timing and design rule violations by Listing the 3 techniques in the appropriate order, Obtaining summary reports of all constraint violations and determining the next course of action, Identifying timing bottleneck blocks for re-synthesis. Enabling generation of Divide and conquer Timing reports to investigate what types of timing paths are causing violations (group_path) and Generating timing reports for setup check, hold check and showing the fanout, capacitance and transition time along the path.

Unit 9 Objective:

Is to list ways to improve the runtime and memory when using the STA flow in PT and summarize the workshop.

Unit 10 Objective:

Is to introduce you to our Customer Support Services.

PrimeTime: Introduction to Static Timing Analysis

i-11

Unit i: Welcome

Test For Understanding

i-12

In this class, what are the 2 types of blocks which you assume are contained within the floor-planned Functional Core?

In this class, what are the 2 types of blocks which you assume are contained within

In this class, how are the net parasitics (RC values) within Functional Core modeled prior to Place and Route?

Nets within a block

Nets between blocks

After attending this class, you will be able to perform Static Timing Analysis on:

(Circle all that apply)

a. Block (Module) level design that is either a mapped netlist or a timing model

b. Functional CORE level design containing synthesized gate level blocks

c. Functional CORE level design with some blocks described as an RTL verilog/VHDL file

d. CHIP level design that has been placed and routed (P&R)

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-12

Unit i: Welcome

Abbreviations and Acronyms

i-13

Acronym Acronym

Meaning Meaning

STA

 

STA

 

DC

DC

 

PT

 

PT

 

GUI

 

GUI

 

Tcl

 

Tcl

 

SOLD

 

SOLD

 

QTM

QTM

QTM QTM
QTM QTM

Synopsys 34000-000-S16

Acronym Acronym

Meaning Meaning

PVT

 

PVT

 

WLM

WLM

 

WNS

 

WNS

 

SPEF

 

SPEF

 

DRC

 

DRC

 

NLDM

NLDM

NLDM NLDM
NLDM NLDM

-

- -

-

- -
- -
- -
- -

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-13

Unit i: Welcome

 

Appendix

i-14

 

Icons used in this workshop

Conventions used in this workshop

The Synopsys “Physical Synthesis Hierarchical Design Flow”

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-14

Unit i: Welcome

Icons Used in This Workshop (1/2)

i-15

Lab Exercise Recommendation For further reference Group Exercise Acronyms

Lab Exercise

RecommendationLab Exercise For further reference Group Exercise Acronyms

For further referenceLab Exercise Recommendation Group Exercise Acronyms

Lab Exercise Recommendation For further reference Group Exercise Acronyms

Group Exercise

Acronyms

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-15

Unit i: Welcome

Icons Used in This Workshop (2/2)

i-16

QuestionChecklist Hint, Tip or Suggestion Remember C a u t i o n N o

ChecklistQuestion Hint, Tip or Suggestion Remember C a u t i o n N o t

Hint, Tip or SuggestionQuestion Checklist Remember C a u t i o n N o t e

RememberQuestion Checklist Hint, Tip or Suggestion C a u t i o n N o t

C a u t i o n Caution

N o t e Note

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-16

Unit i: Welcome

Conventions Used in this Workshop

i-17

 

Convention

Description

Courier

Indicates command syntax.

Courier italic

Indicates a user-defined value in Synopsys.

Courier bold

Indicates user input—text you type verbatim—in Synopsys syntax and examples. (User input that is not Synopsys syntax, such as a user name or password you enter in a GUI, is indicated by regular text font bold.)

[

]

Denotes optional parameters, such as pin1 [pin2

pinN]

|

Indicates a choice among alternatives, such as low | medium | high (This example indicates that you can enter one of three possible values for an option: low, medium, or high.)

Control-c

Indicates a keyboard combination, such as holding down the Control key and pressing c.

\

Indicates a continuation of a command line.

/

Indicates levels of directory structure or design’s hierarchy.

Edit > Copy

Indicates a path to a menu command, such as opening the Edit menu and choosing Copy.

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis

i-17

Unit i: Welcome

The Synopsys Physical Synthesis Flow

i-18

Objectives
Objectives

Develop a realizable floorplan for the chip and realistic design budgets for blocks

START START RTL RTL and and Chip Chip Constraints Constraints Design Planning Design Implementation Design
START START
RTL RTL and and
Chip Chip
Constraints Constraints
Design
Planning
Design
Implementation
Design
Refinement and
Chip Finishing
END END
Design Refinement and Chip Finishing END END Create a placed design which passes STA. Perform an

Create a placed design which passes STA. Perform an initial detail route of chip

ECO the P&R until it meets required performance specs for tapeout

Synopsys 34000-000-S16

Welcome PrimeTime: Introduction to Static Timing Analysis

Welcome PrimeTime: Introduction to Static Timing Analysis RTL ( R egister T ransfer L evel) The

RTL (Register Transfer Level)

The Synopsys Physical Synthesis hierarchical design flow was created by the Synopsys Design Flow Group to help promote and ease the adoption of Synopsys design tools, as well as to provide feedback and drive enhancements of product performance and usability. The Synopsys Design Flow Group engages in customer partnerships from RTL to tapeout to drive success for multi-million gate designs.

The flow encourages top-level floorplanning, power planning and global routing early in the flow followed by successive refinement of data and design until timing closure (i.e. the Design Planning, Design Implementation, and Design Refinement phases).

PrimeTime: Introduction to Static Timing Analysis

i-18

Unit i: Welcome

An Overview of Design Planning

i-19

An Overview of Design Planning i-19   RTL,       chip constraints   Power Power
An Overview of Design Planning i-19   RTL,       chip constraints   Power Power
 

RTL,

     

chip

constraints

 
Power Power Analysis Analysis
Power Power Analysis Analysis
 
RTL RTL verification verification Obtain Obtain target target RTL RTL and and toggle toggle coverage
RTL RTL verification verification
Obtain Obtain target target RTL RTL
and and toggle toggle coverage coverage

PP

CA

Power Power Planning Planning
Power Power Planning Planning
compile compile datapath datapath FV synthesis synthesis with with scan scan
compile compile datapath datapath
FV
synthesis synthesis with with scan scan

CA

ILM assignment Initial assignment Initial pin pin
ILM
assignment Initial assignment Initial pin pin
ILM Top-level Top-level global global routing routing and and congestion congestion analysis analysis
ILM
Top-level Top-level
global global routing routing and and
congestion congestion analysis analysis
Top-level Top-level repeater repeater insertion insertion ILM
Top-level Top-level
repeater repeater insertion insertion
ILM
JTAG JTAG insertion insertion
JTAG JTAG insertion insertion
 

CA

 

CA

IO IO Pad Pad Assignment Assignment
IO IO Pad Pad
Assignment Assignment
 
 
Floor-planning, Floor-planning, hierarchy hierarchy manipulation manipulation reshaping reshaping
Floor-planning, Floor-planning,
hierarchy hierarchy manipulation manipulation
reshaping reshaping

FR

Floor-planning, Floor-planning, hierarchy hierarchy manipulation manipulation reshaping reshaping FR    
 
   
 

VCS

CoverMeter

Vera

MC,

ACS

BSDC

CA

CA

CA A
CA
A

New in 2.2

Welcome PrimeTime: Introduction to Static Timing Analysis

START START RTL, RTL, Chip Chip constraints constraints Design Planning Design Implementation
START START
RTL, RTL,
Chip Chip
constraints constraints
Design
Planning
Design
Implementation
Design Refinement and Chip Finishing END END
Design
Refinement
and Chip
Finishing
END END

Synopsys 34000-000-S16

and Chip Finishing END END Synopsys 34000-000-S16 VCS VCS Verilog Simulator CA Chip Architect PP

VCS

VCS Verilog Simulator

CA

Chip Architect

PP

PrimePower

FR

Flex Route

BSDC

BSD Compiler, Boundary Scan Synthesis

FV

Formal Verification (FM Formality)

MC

Module Compiler

ACS

Automatic Chip Synthesis

ILM

Interface Logic Model

PrimeTime: Introduction to Static Timing Analysis

i-19

Unit i: Welcome

An Overview of Design Implementation

i-20

START START RTL, RTL, Chip Chip constraints constraints Design Planning Design Implementation Chip Finishing and
START START
RTL, RTL,
Chip Chip
constraints constraints
Design
Planning
Design
Implementation
Chip Finishing
and Design
Refinement
END END
New in 2.2

Synopsys 34000-000-S16

A Block Block Level Level physical physical synthesis synthesis Block Block Level Level CTS CTS
A
Block Block Level Level
physical physical synthesis synthesis
Block Block Level Level CTS CTS
CTC
Low Power
Low Power
Block Block Level Level
Detail
Optimization Optimization
Detail
Routing
Router
PC
FV
Detail Routing
Detail
One One Pass Pass Scan Scan
Router
Arcadia
Placement Placement
Block Block Level Level
RC RC Extraction Extraction
ECO ECO
Route Route
PT
ILM ILM
Generation Generation
PC
PT
Top
Level
ILM
Block Block Level Level
STA STA and and
ILM ILM creation creation
FV
Top Level
RC-
RC-
correlation
physical
synthesis
correlation
physical synthesis
Low Power
FV
Low Power
Block Block
level level IPO IPO
timing OK ?
Optimization Optimization
no
PC
PC
One One Pass Pass Scan Scan
yes
ATPG
Placement Placement
Chip Chip Integration Integration
CA
ILM
ILM
CTC,
PT
Full Full Chip Chip STA STA
Placement Placement handoff handoff
Top Top Level Level CTS CTS
STAMP
Top
Level
FV
Top Level
Detail Detail Route Route
Detail
Router
timing OK
no
yes
Welcome

PrimeTime: Introduction to Static Timing Analysis

PrimeTime: Introduction to Static Timing Analysis CTS Clock Tree Synthesis ECO Engineering Change

CTS

Clock Tree Synthesis

ECO

Engineering Change Order

PC

Physical Compiler

CTC

ClockTree Compiler

ATPG

Automatic Test Pattern Generation

IPO

In-Place Optimization

PrimeTime: Introduction to Static Timing Analysis

i-20

Unit i: Welcome

An Overview of Design Refinement

i-21

START START RTL, RTL, Chip Chip constraints constraints Design Planning Design Implementation
START START
RTL, RTL,
Chip Chip
constraints constraints
Design
Planning
Design
Implementation
Design Refinement and Chip Finishing END END Synopsys 34000-000-S16
Design
Refinement and
Chip Finishing
END END
Synopsys 34000-000-S16
Arcadia Top Level Extraction Top Level Extraction Arcadia Blocks/Top Blocks/Top RC RC Extraction Extraction PT
Arcadia
Top Level
Extraction Top Level
Extraction
Arcadia
Blocks/Top Blocks/Top
RC RC Extraction Extraction
PT
ILM Generation
PT
Full Full Chip Chip STA STA
ILM
PT
Full Full Chip Chip STA STA
ILM
no
yes
timing OK
timing OK
yes
PP
PT
Capture Capture
Block Block Level Level
Constraints Constraints
Final Final Analysis Power Power
Analysis
PT-SI
Crosstalk Analysis Crosstalk
Analysis
Top level
ILM
Detail
Block Block level level
IPO, IPO, hold hold fix fix
Top level
IPO, IPO, hold hold fix fix
Router
Crosstalk Crosstalk Repair
Repair
PC
SLE
GDSII GDSII Merge Merge
Block ECO Block Route Level Level
ECO Route
Top Top Level Level
ECO ECO Route Route
Calibre
DRC DRC
Detail
Calibre
LVS LVS
Router

PC

Route Calibre DRC DRC Detail Calibre LVS LVS Router PC Detail Router New in 2.2 SLE

Detail

Router

DRC DRC Detail Calibre LVS LVS Router PC Detail Router New in 2.2 SLE Chip Chip

New in 2.2

SLE

Chip Chip Finishing Finishing
Chip Chip Finishing Finishing

Welcome

PrimeTime: Introduction to Static Timing Analysis

Welcome PrimeTime: Introduction to Static Timing Analysis SLE Synopsys Layout Editor LVS Layout vs.

SLE

Synopsys Layout Editor

LVS

Layout vs. Schematic

DRC

Design Rule Checker

GDSII

Graphics Design Standard Format II

PrimeTime: Introduction to Static Timing Analysis

i-21

Unit i: Welcome