Beruflich Dokumente
Kultur Dokumente
Asynchronous circuits
Synchronous circuits
4. Write the next state and output equation for mealy model of a CSSN.
If x denotes the input signal and Q is the collective present states of the flipflops, then the next state of the network denoted by Q+ is given by,
Q+ = f(x,Q)
The output z is the function of both an input and present state. It is given by
Z = g(x,Q)
1
6. Write the next state and output equation for Moore model of a CSSN.
If x denotes the input signal and Q the collective present states of the flipflops, then the next state of the network denoted by Q+ is given by,
Q+ = f(x,Q)
The output z are only the function of present state and not of the external
input is given by,
Z = g (Q)
7. Compare and contrast the features of Moore and mealy state machine.
Mealy machine
Its output is a function of present
state as well as external inputs.
It requires less number of states for
implementing same function.
It is different to design a mealy
machine because of network
specification that it also a function
of current external inputs.
Moore machine
Its output is a function of present
state only.
It requires more number of states
for implementing same function.
It is easy to design a Moore
machine.
False identification
difficult.
8. What are the steps involved in analyzing a CSSN?
Logic diagram
Logic equation
Excitation table
Transition table
State table
State diagram
Network terminal behaviour
2
is
little
10. Draw the state diagram for a Moore serial binary adder.
PP0:
PP1:
UNIT-2
1. Draw a block diagram of an asynchronous sequential circuit?
n input variables
m output variables
k internal states
2. Write down the Analysis Procedure for asynchronous circuit.
Steps:
1. Determine all feedback loops.
2. Assign Yi's (excitation variables), yi's (secondary variables)
3. Derive the Boolean functions of all Yi's
4. Plot each Y function in a map, y variables for the rows
The external variable for the columns
5. Combine all the maps into one transition table
showing the value of Y=Y1Y2Yk inside each square
6. Circle the stable states and derive the state table
Those values of Y that are equal to y=y1y2yk in the same row
Total state of the circuit: combine internal state with input value
7
UNIT-3
1. Define fault
A fault of a circuit is the physical defect of one or more components are
connection of the circuit.
2. Define the term fault detection and location.
The task of determine whether fault present or not in the circuit is called
fault detection.
The task of the isolating fault is called fault location.
3. What is meant by fault diagnosis?
The combined task of fault detection and fault location is referred to as
fault diagnosis. The technique adopted to diagnose faults is testing.
4. Define Stuck-at fault.
A stuck-at fault is said to have occurred if a signal line appear to have its
value fixed either a logic 1 or 0, irrespective of input signal applied to the circuit.
Stuck-at 0 fault:
When the signal line is logic 0, the fault is called stuck-at 0 fault, it is
denoted SA0.
Stuck-at 1 fault:
When the signal line is logic 0, the fault is called stuck-at 0 fault, it is
denoted SA0.
5. Define Test Vectors.
An input combination in which the presence of a fault produces an output
different from the fault-free output is known as a test vector (TV).
6. Define Test generation
Test generation is the process of finding the set of test vectors that can detect
(or detect and locate) the faults in a circuit.
7. Define Test set
The set of test vectors used for testing the circuit is called test set. The test
set is classified,
1. Fault detection test set
2. Fault diagnosis test set
10
11
Circuit description
Fault modeling
Test generation
Fault simulation
Fault coverage evaluation
Test application
22. What is meant by Kohavi algorithm?
It is used to detect multiple faults in two level networks. The technique,
which consists of determining two sets of tests, the test and b test, considers the
altered Boolean function realized by the circuit due to the presence of the single
fault. Kohavi proved that this single fault test set detect all multiple faults.
23. What are the conditions of Kohavi algorithm?
The network must be two level AND-OR or (OR-AND) network.
AND gate must realize a prime cube.
AND-OR network must implement a Boolean function which is a
sum of irredundant prime implicants.
24. What is the test and b test?
A test: The set of distinguished min terms that tests each AND gate for
SA0 fault is called the set of a test.
B test: The set of min terms that test each AND gate for SA1 fault is called
the set of b test.
25. What are the types of fault tolerance techniques?
Static redundancy technique
Dynamic redundancy technique
13
14
UNIT-4
1. Define reliability of the system.
Reliability of a system is defined to be probability that the given system will
perform it required function under specified period of time.
Reliability of a system is a real number between 0 and 1.
R (t) = limN->WN (t)/N
2. Define failure rates.
The failure rate is the number of failures that occur per unit time in a
component or system.
It is usually denoted by the Greek letter .
3. What is meant by FIT?
The failure rates for typical electric components are so small there are several
scaled units for expressing them: percent failures per 103 hours, failures per 106
hours and failures per 109 hours. The last unit is called a FIT.
1 FIT = 1 failure/ (109 hours)
4. What is meant by infant mortality?
The failure rate of a typical electronic component is a function of time. The
typical component has a high failure rate during its early life, during which most
manufacturing defects make themselves visible; failure during this period are called
infant mortality.
5. What are the factors affecting the failure rate?
The factors that can affect component failure rates, including
Temperature, Humidity, Shock, Vibration, Power cycling
6. Define MTBF
Another measure of the reliability of a component or system is the mean
time between failures (MTBF).
The average time that it takes for a component to fail. For components
with a constant failure rate , it can be shown that MTBF is simply the reciprocal of
.
MTBF = 1/
15
16
18
UNIT-5
1. What is read-only memory (ROM)?
A read only memory (ROM) is a combinational Circuit with n inputs & b
outputs. The inputs are called address inputs are traditionally named a0, a1an1.the outputs are called data outputs are typically named d0, d1, .db-1.
2. What is word line?
The address input select one of the decoder outputs to be asserted. Each
decoder o/p is called word line because it selects one row or word of the table
stored in the ROM.
3. What is bit line?
Each vertical line is called a bit line because it corresponds to one output bit
of the ROM. An asserted word line pulls a bit line low if a diode is connected
between the word line and the bit line.
20
21
1. Read:
An address is placed on the address inputs while CS&OE are asserted. The
latch outputs for the selected memory location are delivered to DOUT.
2. Write:
An address is placed on the address inputs data word is placed on DIN then
CS & WE is asserted. The latch in the selected m/y location open and the input
word is stored. (Static-Ram timing)
23. What is the output-hold time (toh)?
It is the parameter specifies how long the output data remains valid after a
change in the address inputs. (Timing parameter)
24. What is the address setup time before write (tas)?
All of the address inputs must be stable at this time before both CS&OE are
asserted. Otherwise, the data stored at unpredictable locations may be corrupted.
25. What is the chip select setup before end of write (tcsw)?
Cs must be asserted at least long before the end of the write a cycle in order
to select a cell.
Prepared by,
2014 Batch ME Students
KNCET
TRICHY
Any correction please inform us through mail: 9rubies14@googlegroups.com
23