UNIVERSITY

OF HOUSTON CLEAR LAKE

Design of a 4 bit ALU using

VHDL
Luz Orlando Ramirez
and Alfredo Nava
CENG 3511, Section 2, Saurin Ganatra

4bitALUdesignedusingbehavioralVHDLcodingtechniques.The4bitALUusingtheaforementionedcoding
techniquessuccessfullyperformedarithmetic,logical,andshiftingoperations.TheALUperformsalimitednumberof
arithmetic,logical,andshiftingoperationsdependentontheuserdefinedinput.

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Contents
I.

Background.....................................................................................................................................................................2

II.

Project Overview.........................................................................................................................................................2

a.

Objective.....................................................................................................................................................................2

b.

Method........................................................................................................................................................................2

c.

Procedure....................................................................................................................................................................2

III.

Observations...............................................................................................................................................................3

IV.

RTL (Register Transfer Level) schematic and Waveform of ALU............................................................................3

a.

Top level.....................................................................................................................................................................3

b.

Detailed RTL schematic..............................................................................................................................................3

c.

Waveforms..................................................................................................................................................................4

V. Conclusion......................................................................................................................................................................4
VI.

Recommendation........................................................................................................................................................4

WorksCited.............................................................................................................................................................................5
Appendix.................................................................................................................................................................................6
VHDL Code for ALU.........................................................................................................................................................6
VHDL Code for 4-bit Full Adder.......................................................................................................................................9
VHDL Code for a 1-bit Full Adder.....................................................................................................................................9
Detailed RTL Schematic of designed ALU......................................................................................................................10

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Introduction
The main goal of this experiment is to design a 4-bit ALU using one main VHDL coding technique
using XILINX. The 4-bit ALU was implemented using a VHDL coding techniques that model a four bit
full adder and numerous MUXes. VHDL coding was primarily done using a student version of XILINX
software.
I.

Background

ALUs (Arithmetic Logic Units) are significant in that they primarily perform nearly all arithmetic and
logical operations. The arithmetic logic unit (ALU) is the brawn of the computer, the device that performs
the arithmetic operations like addition and subtraction or logical operations like AND and OR (Patterson,
Hennessy C-26). More detailed information about MUXes, Adders, and other devices can be found in the
textbook Fundamentals of Logic Design (2010) by Charles H. Roth, JR. and Larry L. Kinney. Also a
complete description of ALUs is provided by the text Computer Organization and Design (2009) by David
A. Patterson and John L. Hennessy.
The primary goal and results of the experiment will be discussed in the following sections.
II.

Project Overview
a. Objective
Build a 4-bit ALU that performs basic arithmetic, logic, increment/decrement and shifting
operations using only one VHDL coding technique. The 4-bit ALU will have: 4-bit input, output and
operation select lines and 1-bit carry in and carry out lines. In addition, the 4-bit ALU will perform
eleven distinct operations.
b. Method
To enter different inputs into the 4-bit ALU to determine if the outputs of the ALU correspond to the
predicted function and result. A pre-defined set of Operation Select of 4-bit inputs will aid in the
identification in the case that the ALU produces an output that does not agree with the predicted
function or outcome.
c. Procedure
Since the ALU is composed of numerous internal components the operation select inputs are a
significant role in determining what output the ALU produces. Specifically, there are only two cases in
which the carry in line is not treated as a dont care and does not affect the ALU output, these occur
when 4-bit input A needs to be transferred directly onto the 4-bit output G. Although, the design of the
4-bit ALU includes a four-bit full adder the output of the ALU is significantly affected by the numerous
MUXes used in the design as defined per the use of WHEN-ELSE VHDL statements in main VHDL
source file. In respect to the carry out output of the ALU, the ALU was designed so that the carry out
retains the previous carry in of a past operation where in the carry in is not in use.

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IIII.

Obseervations
a. The
T design im
mplemented
d effective use
u of multipplexers for aall the signaals. This alloows for each
h
siignal to be modified
m
an
nd reused acccording to tthe operationn the ALU nneeds to perrform. Thesee
where
w
used to
o increase th
he efficiency of the desiggn, and impleement four aarithmetic fuunctions with
h
on
nly a single adder.
b. The
T heavy use of MUX
Xes helped in
ncrease the stability siggnificantly bby allowing the ALU to
o
prroduce its ow
wn internal signals
s
for operations
o
whhere the Cinn was not neccessary.
c. MUXes
M
reduce errors in the design of
o the ALU is that all ccases are covvered for eaach signal, so
o
th
hat a signal will
w never giive an Unid
dentified ouutput or errorr.
d. MUXes
M
havee minimal propagation
p
delay, and aare a much better impllementation than severaal
arrithmetic com
mponents.

IIV.

RTL (Register Transfer

T
Level) schema
atic and Waaveform of A
ALU
a. Top
T level

FIIGURE 1.2 A
ALU with intternal compoonents
A larger versionn of FIGURE 1.2 is availablle in the Appeendix
section of the repport. On furthher inspection oof the ALU onee can
no
otice the prefe
ferred use of MUXes over multiple fouur bit
ad
dders.

D
RTL
L schematic
b. Detailed

FIIGURE 1.1 T
Top Level RT
TL Schematiic of ALU
Th
he schematic ddepicts a top llevel representtation of the
AL
LU with its resspective input and outputs. N
Note that Op
(3:0) is what deetermines whaat operation thhe ALU will
peerform.

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c. Waveforms
W
d.

FIG
GURE 1.3 ALU
A
Wavefform of ALU
U
Thee above wavefo
orm representss two test casess. The first teest case happenns to have oveerflow while thhe
seco
ond test case does
d
not have overflow. Th
he values of caarry in and carrry out are im
mportant to keeep
track of since if an
a arithmetic operation
o
occurrs for thousandds of times a m
missing value of carry in caan
have a significant outcome on th
he calculated prroduct.

V
V.

Concclusion

For somee ALU operaations the vaalue of carry

y in is not neeeded. Alsoo, since the 44-bit ALU V
VHDL sourcee
ccode contain
ns numerou
us WHEN-E
ELSE stateements the RTL Schem
matic in XIILINX dispplays various
internal MU
UXes. The in
nternal use of MUXes in the 4-bit ALU improoves perform
mance but thhe more thaat
M
MUXes are used the more
m
probab
ble that the cost of thee design couuld increasee. Thus, thhere exists a
pperformance cost tradeeoff in the deesign of the 4-bit
4
ALU.

V
VI.

Reco
ommendatio
on

Inclu
uding a cost-performancee analysis in
n the project to illustratee how cost caan limit the performancee
oof an ALU and vice verssa.

CENG3511

WorksCited
Roth,CharlesH.,andLarryL.Kinney.FundamentalsofLogicDesign.Stamford,CT:CengageLearning,

Patterson,DavidA.,andJohnL.Hennessy.ComputerOrganizationandDesign.Boston:MorganKaufmann,

2010. Print.

2009.Print.

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Ap
ppendix
VHDL Code for ALU

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VHDL
V
Code for 4-bit Fu
ull Adder

VH
HDL Code for
f a 1-bit F
Full Adder

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Detailled RTL Sch

hematic of d esigned AL
LU

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