IEICE TRANS. ELECTRON., VOL.E86C, NO.

3 MARCH 2003

496

PAPER

A New Dynamic D-Flip-Flop Aiming at Glitch and

Charge Sharing Free
Sung-Hyun YANGa) , Younggap YOU , Nonmembers,
and Kyoung-Rok CHO , Regular Member

SUMMARY A dual-modulus (divide-by-128/129) prescaler

has been designed based on 0.25-m CMOS technology employing new D-ip-ops. The new D-ip-ops are free from glitch
problems due to internal charge sharing. Transistor merging
technique has been employed to reduce the number of transistors and to secure reliable high-speed operation. At the 2.5-V
supply voltage, the prescaler using the proposed dynamic D-ipops can operate up to the frequency of 2.95-GHz, and consumes
about 10% and about 27% less power than Yuan/Svenssons and
Huangs circuits, respectively.
key words: dynamic D-flip-flops, prescalers, low-power circuits,
glitch free

1.

Introduction

Frequency synthesizers have been basic building blocks

in modern communication systems. One of the key elements of the frequency synthesizer is a dual-modulus
prescaler used in a fast phase-locked-loop (PLL).
High performance prescalers and voltage controlledoscillators are frequently used in high-speed applications. Costly bipolar or GaAs technologies have been
the basis of these high-speed parts, which are being replaced with rapidly improving low-cost CMOS technology. CMOS implementations become very attractive
due to their characteristics of high frequency operation,
low-power consumption yielding long battery life.
Dynamic D-ip-ops for high-speed operation and
low-power consumption are essential to high performance frequency synthesizers. Various ip-ops have
been proposed to improve the operating speed of dualmodulus prescalers [1][10]. The dynamic D-ip-op
designs in previous studies found suer from glitch and
charge-sharing problems [2], [3], which may result in incorrect operations. To alleviate these problems, additional transistors are introduced to some critical nodes
to make these nodes stable [4][6]. However, the newly
added transistors limit operating speed and increase
power consumption. In high-frequency operations, ratioed logic can replace ratioless logic without signicant
penalty on power consumption [8][10]. Ratioed logic,
however, consumes high power in low-frequency operaManuscript received December 28, 2001.
Manuscript revised July 9, 2002.

The authors are with the Department of Computer and

Communication Engineering, Chungbuk National University, San 48, Gaesin-dong, Cheongju Chungbuk, Korea.
a) E-mail: shyang@hbt.chungbuk.ac.kr

tion, and their operating frequency range is limited.

In this paper, a new dynamic D-ip-op without
glitch problems resulting from charge sharing is proposed, which is a basic building block of a high-speed
and low-power CMOS dual-modulus prescaler. The
proposed dynamic ip-op is to ensure edge-triggering
operation independent of operating frequency. By reducing the charge sharing eect, more reliable operation can be achieved. This paper is organized as follows. In Sect. 2, serious problems of conventional dynamic ip-ops, such as glitch and charge sharing, are
reviewed. Section 3 describes the structure and operation of the proposed D-ip-ops. Simulation and experimental results are summarized in Sect. 4. Finally,
the conclusions are presented in Sect. 5.
2.

Conventional Dynamic D-Flip-Flops

Dynamic or clocked logic gates are used to decrease

circuit complexity, increase operating speed, and lower
power dissipation [12]. Of various dynamic CMOS circuit techniques, a true single-phase-clock (TSPC) dynamic CMOS circuit is operated with one clock signal
that is never inverted. Therefore, no clock skew exists
except for the clock delay problems, and even higher
clock frequency can be achieved [2], [11].
Figure 1 shows a TSPC D-ip-op for high-speed
operation introduced in [1], [4][6]. The ip-op consists of nine transistors, where the clocked switching
transistors are placed closer to power/ground for higher
speed [6]. The state transition of the ip-op occurs at
the rising edge of the clock signal, clk.
Figure 2(a) shows the operation: Qb becomes high

Fig. 1

A TSPC D-ip-op for high-speed operation [1].

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497

(a) D = 0, clk = 0 1: Qb 1

Fig. 3

Simulation results of the D-ip-op in Fig. 2.

(b) D = 1, clk = 0 1: Qb 0
Fig. 2

Operation of a conventional dynamic D-ip-op [1].

along clk changing low to high with D = 0. In Fig. 2,

the dotted lines are the conducting paths when clk =
0, and the solid lines when clk = 1. If D = 0 and clk
= 0, MPS1, MP1, and MPS2 are turned on and n1 , y1 ,
and y2 become high. If the signal clk changes low to
high, the node y2 is discharged to low through MN2 and
MNS1, making MP2 be on and Qb high. Figure 2(b)
shows the case with clk changes low to high and D =
1 making Qb be low. The analysis is extended to other
input combinations in the same manner.
2.1 Glitch and Charge Sharing Problems
Edge-triggered ip-ops take incoming data at the edge
of a clock signal. Glitch problems may occur making
the ip-ops fall into wrong states. Consider the circuit
in Fig. 2(a) with clk = 0 and D = 0, where y1 and y2 are
precharged to high voltage. If clk changes low to high,
the node y2 is discharged to low after some delay. In
other words, y2 remains high for a short time, in which
MN3 and MNS2 are turned on and Qb may change
to low. By discharging of y2 , then, Qb returns to the
correct state of high. A glitch may appear at Qb as
indicated (a) in Fig. 3.
Consider the circuit in Fig. 2 to discuss charge
sharing eects. When clk is low, the node y2 is always
precharged high making MN3 on. The nodes, then, Qb
and n3 may share their charges. The high level of Qb
is somewhat lowered by sharing charges with the low
level of n3 as indicated (b) in Fig. 3.
Glitches induced by charge sharing among internal nodes are illustrated in Fig. 3. With clk low and D

Fig. 4

Toggle conguration using D-ip-op.

high, both n1 and y2 are precharged to the VDD level

and y1 is discharged to ground. Then clk changes to
high making MNS2 turn on and Qb low. Here, clk is
assumed high for a while and D changes high to low
instantly, then MN1 becomes o and MP1 turned on.
Nodes n1 and y1 share their charges through MP1 making y1 rise above the threshold voltage of MN2. With
clk high and MNS1 on, the node y2 discharges slowly,
which leads MP2 to be turned on and Qb to rise to
high. This is shown as (c) and (d) in Fig. 3. At the
point (c), if clk changes to low right after D changes
to low, there is no critical operation due to the small
amount of discharge at y2 and MP2 cannot be turned
on. However, the edge-triggering operation of the ipop is prevented in the case that the discharging time
of y2 is long as shown at (d) in Fig. 3.
Charge sharing raises more serious problems when
the D-ip-op is used as a toggle-ip-op operating in
a lower frequency range. For toggle operations, Qb is
tied to D as shown in Fig. 4. By changing clk low to
high with Qb in a high state, Qb toggles to low. Since
Qb and D are tied together, D is forced to change high
to low right after clk changes low to high. The time
that D stays low is almost half the period of clk. In a
lower operating frequency, y2 would have enough time
to discharge making MP2 turn on strongly and Qb high.
The ip-op, therefore, loses its edge-triggering characteristics and fails to perform proper operations.

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Fig. 6

A D-ip-op design proposed by Huang [6].

Fig. 7

Simulation waveforms of Huangs D-ip-op.

(a) Simulation waves at clk = 2 GHz

(b) Simulation waves at clk = 3 GHz

Fig. 5

Simulation waveforms of toggle-ip-op of Fig. 4.

Figure 5 shows the simulation result of the toggleip-op. As shown in Fig. 5(a), when the frequency of
2-GHz is applied to clk, the toggle operation is not performed because of the long discharging time of the node
y2 . In Fig. 5(b), however, the ip-op shows the proper
toggle operation under the suciently high frequency of
3-GHz because the discharging time of y2 is small. As
a result, in the low frequency the edge-triggering characteristic of the ip-op gets worse and the reliability
degrades. The toggle-ip-op in Fig. 4 operates properly above 2.5-GHz when it is designed using 0.25-m
CMOS technology. Though the ip-op violating the
edge-triggering feature can be used as a component of a
divide-by-4/5 synchronous counter in a high-frequency
dual-modulus prescaler, it cannot be used as a ip-op
alone [7][10]. The edge-triggering characteristics are
very important for reliable operation.
2.2 Huangs D-Flip-Flop
Huang proposed a D-ip-op circuit shown in Fig. 6
aiming at the elimination of glitches as shown in Fig. 3
[4][6]. To alleviate the charge sharing, the small size
transistor MN5 prevents y1 from rising when D changes
high to low during clk high. MN5 and the inverter
INV1 make a pull-down path of y1 as follows. If D
changes high to low during clk = 1, n1 and y1 share
their charges. That is, y1 would rise up, but the output

of INV1 still has a high value turning on MN5. This

makes y1 low and stable resolving the charge sharing
problem.
The same analogy applies Qb having MP3 and
INV2. A transistor MN4 is introduced between MN3
and MNS2 to remove glitches. That is, MN4 driven
by INV1 breaks the pull-down path of Qb. When D
= 0 and clk = 0, nodes y1 and y2 are precharged to
high. If clk changes low to high, y2 discharges to low.
This operation cannot be completed instantaneously:
MN4 prevents Qb from pulling down to ground. Figure 7 shows the simulation waveforms with the clock
frequency of 100 MHz.
Introduction of MN4 in Fig. 6 brings a new problem as the point (a) of Fig. 7. For clk = 0 and D =
0, y1 and y2 are precharged to high. If clk changes
low to high, y2 discharges to low and Qb becomes high.
Though D changes low to high when clk = 1, Qb remains high. At this time, y1 = 0 and clk = 1, n3 and n4
are low because both MN4 and MNS2 are turned on.
If clk changes to low, y2 is precharged to high. Then
Qb shares charges with n3 and n4 through MN3 and
MN4. This makes the voltage of Qb fall down. Even
though MP3 can stabilize Qb, the time for returning to
a correct logic value is somewhat long.
3.

Proposed Dynamic D-Flip-Flop

We now introduce a new dynamic D-ip-op eliminat-

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499

ing glitches and reducing the number of transistors. It

is based on a ratioed logic design technique and transistor merging.
3.1 Transistor Merging
Transistor merging is to reduce the number of transistors and thereby save both power and silicon area while
suppressing glitch occurrences. Pull-up and pull-down
transistors are combined together yielding a circuit having fewer pull-up and pull-down transistors. Consider
the circuit shown in Fig. 1, where the nodes n1 and y2
have the same potential of VDD during clk = 0. When
clk = 1, its operation is independent of the n1 level and
y2 may stay high or discharge to low. This observation
leads to merge two pull-up transistors of the conventional design. MPS1 and MPS2 in Fig. 1 are merged to
MPS1 as shown in Fig. 8(a). With the same analysis,
MNS1 in Fig. 8(a) replaces MNS1 and MNS2 in Fig. 1.
3.2 Charge Sharing Problems
In Fig. 8(a), with clk = 0, y2 is always high turning on
MN3 and causing charge sharing between n1 and Qb
and resulting in an incorrect value at Qb. It is eective
to introduce a transistor MNS2 driven by clk between
MP2 and MN3 [2]. Figure 8(b) shows the proposed
circuit, where MNS2 blocks charge sharing between Qb
and n2 . The simulation result for the circuit of Fig. 8(b)

(a) Toggle-ip-op using the transistor merging technique

is shown in Fig. 9. The 2-GHz sinusoidal wave is applied

as the clock. An inverter is connected to the Qb node
to generate the Q signal. Under 1.8-GHz, the toggle
connection ip-op in Fig. 8(b) ends up wrong operations due to long discharging time of y2 , and yields an
unpredictable state of y2 . While the structure in Fig. 4
fails to operate at 2-GHz, the structure in Fig. 8(b) can
operate at the frequency of 2-GHz. The reason is that
y2 in Fig. 8(b) starts discharging later than y2 in Fig. 4
since inserting MNS2 makes Qb discharge slowly.
Figure 10 shows the proposed D-ip-op comprising nine transistors, which is free from glitches induced
by charge sharing. The MPS2 transistor driven by clk
as shown in Fig. 10 can eectively reduce charge sharing experienced in the circuit of Fig. 1. MPS2 disturbs
charge distribution path between y1 and y2 preventing MN2 from turning on. This guarantees the correct
edge-triggering operation of the ip-op and enhances
its reliability. Unfortunately, the critical path to pull
up y1 node is longer and thereby some speed degradation is expected.
The operation of the proposed D-ip-op shown in
Fig. 10 is as follows. Consider the circuit of Fig. 11(a),
where nodes y1 , n1 , and y2 are precharged high with
clk = 0 and D = 0. During this phase, MNS1 and
MP2 are o, and Qb holds the previous value. Note
that both n2 and n3 are weak high because of y1 and

Fig. 9

Simulation results for the proposed circuit of Fig. 8(b).

(b) Charge sharing protection between Qb and n1 using MNS2

Fig. 8 The proposed toggle-ip-op designed with transistor
merging technique.

Fig. 10

The proposed D-ip-op for glitch elimination.

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(a) D = 0, clk = 0 1: Qb 1
Fig. 12
Fig. 10.

Simulation results of the proposed D-ip-op in

the initial charge of y2 node, Qinitial , is

Qinitial = Cy2 V DD

(1)

The total charge after charge sharing, Qf inal , is

Qf inal = (Cy2 + Cn1 ) Vf inal

(b) D = 1, clk = 0 1: Qb 0
Fig. 11 Operations and signal paths of the proposed
D-ip-op.

According to the charge conservation law, Qf inal =

Qinitial must be satised.
(Cy2 + Vf inal ) = Cy2 V DD

(3)

Thus the nal voltage of y2 , Vf inal , is

Vf inal =

y2 being high. Assuming that clk changes low to high,

MPS1 and MPS2 are turned o and MNS1 and MNS2
are on. Since y2 cannot discharge instantly, a pull-down
path is formed consisting of MNS2, MN3, and MNS1.
But n2 and n3 keep weak high from the previous phase
resulting in a small glitch due to the voltage drop of
Qb. As y2 becomes low through MN2 and MNS1 path,
Qb rises high.
Considering that clk = 0 and D = 1 as shown in
Fig. 11(b), y2 is precharged to high but y1 is low. This
makes MN2 be turned o. If clk changes low to high, Qb
discharges low through the path consisting of MNS2,
MN3, and MNS1. If we change D to low when clk =
1, MP1 is turned on, but the charge sharing between
y1 and y2 never occurs due to the blocking transistor
MPS2. This implies that MN2 remains o and the pulldown path of node y2 does not exist.
Though there exists the charge sharing eect between y2 and n1 , it is dierent from (c) and (d) of
Fig. 3. As shown in Fig. 12(b), after charge sharing y2
has a stable nal value, since clk = 1 and MN2 is o.
On the other hand, the charge sharing in Fig. 3 turns
on MN2, and y2 continues to discharge.
The voltage drop of y2 resulting from charge sharing between n1 and y2 is determined by the ratio of the
total capacitance of n1 and y2 as follows. We assume
that y2 and n1 nodes are initially VDD and ground,
respectively. This is the worst case condition. Then

(2)

Cy2 V DD
V DD
=
Cy2 + Cn1
1 + Cn1 /Cy2

(4)

The parameters of the employed process are as

follows: the junction capacitance Cj at zero bias
is 1 fF/m2 , the junction capacitance of the sidewall Cjsw,p (Cjsw,n ) is 0.041 (0.083) fF/m, Cjgate,p
(Cjgate,n ) is 0.587 (0.82) fF/m, and the gate-oxide capacitance is 6.64 fF/m2 . From the layout, the parasitic capacitances for interconnection lines are extracted
to the order of 101 102 fF, which have a little eect
on the calculation of the parasitic capacitance. With
the source/drain area and their perimeters, Cn1 is calculated to 8.4 fF and Cy2 is calculated to 30.5 fF. Since
(Cn1 /Cy2 ) = 3.63, Vf inal is 1.96 V at VDD = 2.5 V,
which is lower than the threshold voltage of a PMOS
transistor of 0.6 V. If we lower the logic threshold voltage of the inverter consisting of MP2, MNS2, MN3, and
MNS1, this eect can be further alleviated. Note that
the nal voltage of y2 after charge sharing, Vf inal , does
not change any more, which is the dierence from (c)
and (d) of Fig. 3.
Simulation results in Fig. 12 show successful operations of the proposed design. Nine transistors and
one inverter (i.e., 11 transistors) are used to build the
same logic operation of Qb and Q of Fig. 7 with reliable
edge-triggering operations.
Figure 13 shows the structure and the simulation
result of Yuan/Svensson D-ip-op [2], [11], which has
no charge sharing problem but has glitch problems [6].

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501

(a) Yuan/Svenssons D-ip-op

(a) Yuan/Svenssons D-ip-op

(b) Huangs D-ip-op

(b) Simulation result
Fig. 13

4.

Yuan/Svenssons D-ip-op and the simulation result.

Simulation and Experimental Results

To evaluate the performance of the proposed D-ipop, a divide-by-16 asynchronous counter and a dualmodulus divide-by-128/129 prescaler have been designed. Huangs general purpose D-ip-ops [6] of
Fig. 6 and Yuan/ Svensson D-ip-ops [2], [11] of Fig. 13
are used to build an asynchronous counter and a
prescaler for the performance comparison. The circuits
have been resized in 0.25-m technology. Figure 14
and Fig. 15 show the transistor sizing and the layout for
the three D-ip-ops, respectively. The proposed ipop occupies almost the same area as Yuan/Svenssons
ip-op and about 23% less area than Huangs ipop. Yuan/Svensson ip-op operates at the highest
frequency among the three ip-ops. The proposed ipop shows the lowest power consumption, the medium
speed, and the medium power-delay product (PDP).
The maximum operating frequency and the PDP of
the proposed circuit is slightly degraded from stacking three PMOS transistors, MPS1, MP1, and MPS2
as shown in Fig. 10. The lowest power consumption
is achieved by merging of the pull-up and pull-down
transistors. The proposed ip-op in Fig. 10 can be
also obtained by connecting the sources of MP1 and
MN3 to the nodes y2 and n2 in Fig. 13(a), respectively.
Table 1 summarizes the comparison of the number of
transistors and the layout area for three D-ip-ops.

(c) The proposed D-ip-op

Fig. 14 Transistor sizing for (a) Yuan/Svenssons D-ip-op,
(b) Huangs D-ip-op, and (c) the proposed D-ip-op. For all
transistors, the channel length L is 0.25-m.

4.1 Asynchronous Counter

Figure 16 shows the schematic diagram of a divide-by16 asynchronous counter. In each ip-op, node Qb
is fed back to the node D to get a toggle operation
at the rising edge of the clock signal. The divide-by16 counter consists of four cascaded toggle ip-ops,
in which clk drives the rst ip-op and its output Q
drives the next ip-op in turn. The output signal, the
divide-by-16 signal of the main clock, is acquired at the
node Q of the last ip-op stage. The conguration
provides with a practical load conditions for high speed
operation: it employs the next stage ip-ops as its
load instead of the articial load capacitance.
The maximum operating frequency and the power-

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(a) Layout of Yuan/Svenssons D-ip-op (15.6 15.15 m2 )

Fig. 17 Performance comparison of divide-by-16 asynchronous
counters.
Table 2 Transistor dimensions of the proposed D-ip-op related to the scale factor, Sf . = 2.25 m Sf , and the channel
length is 0.25-m for all transistors.

(b) Layout of Huangs D-ip-op (20.4 15.15 m2 )

(c) Layout of the proposed D-ip-op (15.75 15.0 m2 )

Fig. 15

Table 1

Fig. 16
counter.

Layout of three dynamic D-ip-ops.

Comparison for three D-ip-ops.

Schematic diagram of a divide-by-16 asynchronous

delay product versus the supply voltage are evaluated

through the SPICE simulation. Figure 17 summarizes
the simulation results, where the power-delay products
are measured at the maximum frequency of Huangs

circuit for an apparent comparison. At the supply voltage of 2.5-V, the maximum operating frequencies of the
proposed circuit, Huangs circuit, and Yuan/Svenssons
circuit are 4.06-GHz, 3.07-GHz, and 4.85-GHz, respectively. The power-delay products of them at the maximum frequency of Huangs counter (i.e., at the frequency of 3.07-GHz) are 3.113-pJ, 4.284-pJ, and 2.744pJ, respectively. The performance of the proposed circuits is better than that of Huangs circuits in the operating frequency and the power-delay product. At
the frequency of higher than 3-GHz, Huangs ip-op
in Fig. 6 suers from the speed degradation since the
added inverter, INV1, fails to follow the input frequency.
To nd out the eect of the supply voltage and
the device size on the divide-by-16 counter, simulations
have been performed scanning the supply voltage and
the device size. Table 2 shows the working transistor
dimensions of the proposed D-ip-op, where the scale
factor Sf is used to change the transistor width. For
convenience, the parasitic capacitances of each transistors source/drain are calculated with the transistor width and the source/drain length without sharing
source/drain areas with the adjacent transistors.
As shown in Fig. 18, the supply voltage has been
considered from 1.0 to 3.5-V and Sf from 0.2 to 2.0.
The counter operates up to 4.06-GHz with Sf of 1.0.
As the supply voltage and Sf are increased, the maximum operating frequency is gradually increased and
nally saturated as shown in Fig. 18(a). The operating
frequency saturation at high Sf is due to the increase
of the parasitic capacitances. The power consumption
illustrated in Fig. 18(b) shows that the power consumption plane becomes steeper along the supply voltage
and the scale factor increase. The optimum values of

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503

(a) Maximum operating frequency versus VDD and scale factor

Fig. 20

Dual-modulus divide-by-128/129 prescaler.

(b) Power consumption versus VDD and scale factor

Fig. 18 Maximum operating frequency and power
consumption features.
Fig. 21

Performance comparison of divide-by-128 prescalers.

factor is 1.0, the rising time of the clock must be faster

than 0.9-ns. However, if we select the scale factor of
0.2, the rising time requirement becomes a slower value
of 2.1-ns. Figure 19 can be used to estimate the driving
capability of clock drivers for the proper operation of
ip-ops.
4.2 Dual-Modulus Prescaler

Fig. 19 Maximum allowable rising time of the clock according

to the scale factors.

the supply voltage and Sf can be deduced from (a)

and (b) of Fig. 18 with a specication on the maximum
operating frequency and the power consumption.
It is important to control the rise/fall rate at
the clock edge in dynamic ip-ops [2], [6], [11]. The
proposed ip-op requires the clock rising time below
about 1 ns for the correct operation. For the rising time
slower than 1-ns, the precharge and the evaluation may
occur in the middle of a rising edge leading the ip-op
to the wrong operation [6]. A smaller device size allows a slower edge rate of the clock signal. As shown in
Fig. 19, the maximum allowable rising time is decreased
as the device size increase. For example, when the scale

The block diagram of the dual-modulus divide-by128/129 (64/65) prescaler is shown in Fig. 20. The
dual-modulus prescaler has two counters: a divideby-4/5 synchronous counter and a divide-by-32 asynchronous counter. As the output signal of the divideby-4/5 counter, fso in Fig. 20, is connected to the clock
input of the divide-by-32 counter, the prescaler can divide the main clock signal by 128 or 129. The divideby-4/5 counter is the only part operating at the maximum frequency determining the overall speed of the
prescaler [5]. As several logic gates are inserted between the ip-ops to get a proper operation of the
prescaler, the speed degradation is unavoidable due to
the propagation delay.
The select signal chooses the division ratio of the
prescaler between 64/65 and 128/129. When the select is low, the last toggle ip-op in the asynchronous
counter is bypassed and the prescaler operates as a

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Fig. 22 The chip photograph of the dual-modulus prescaler.

The chip area including oscillator was measured to 85 m54m.

erate at about 4-GHz with the supply voltage of 3.5 V.

A dual-modulus divide-by-128/129 prescaler has
been fabricated employing 0.25-m CMOS technology.
The chip photograph is shown in Fig. 22. The area of
the chip including oscillator was 85-m by 54-m. Figure 23 shows the measured output from the fabricated
chip at the supply voltage of 2.5-V. In Fig. 22(a), the
measured output frequency of the prescaler was 22.62MHz (T = 44.2 ns), and the input clock frequency is
estimated to 2.895-GHz. The result is very close to the
simulation result. The output waveforms according to
the division ratios are also shown in Fig. 23(b).
5.

(a) Measured output waveform for the divide-by-128 prescaler

Conclusions

A new dynamic D-ip-op for high-speed operation

and low-power consumption is presented aiming at
glitch free operation. The ip-op consists of only
nine transistors based on the transistor merging technique, which is smaller than other alternatives. The
fewer transistors in the ip-op can achieve faster operation and lower power consumption. To evaluate
the proposed ip-op circuit, a dual-modulus divideby-128/129 prescaler has been designed and fabricated
using 0.25-m CMOS technology. At the 2.5-V supply
voltage, the prescaler using the proposed dynamic Dip-ops can operate up to the frequency of 2.95-GHz
consuming 3.621-mW, and shows half the power-delay
product of Huangs circuits.
Acknowledgement

(b) Output waveform according to the division ratios

Fig. 23

Measured waveforms of the prescaler.

The authors would like to thank Hynix Semiconductor and Integrated Circuit Design Education Center
(IDEC) for the signicant support to fabricate the test
chip as well as the reviewers for their valuable comments.
References

divide-by-64/65 counter. When the select is high,

the prescaler operates as a divide-by-128/129 counter.
When the mode signal is low (high), a divide-by-64 (65)
or 128 (129) prescaler is obtained.
The maximum operating frequency and the powerdelay product versus the supply voltage of the
prescalers are also measured. As shown in Fig. 21,
at 2.5-V supply voltage, the maximum operating frequencies in the proposed circuit, Huangs circuit, and
Yuan/Svenssons circuit are 2.95-GHz, 2.77-GHz, and
3.12-GHz, showing the power-delay products of 6.443pJ, 11.699-pJ, and 5.353-pJ, respectively. For comparison, the power-delay products are measured at the
maximum frequency of Huangs circuit (i.e., at the frequency of 2.77-GHz). Each circuit operates at almost
the same frequency, since the speed of prescaler is limited by the propagation delay of the logic gates. Note
that the prescaler using the proposed ip-ops can op-

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achieve low power consumption and high frequency, Electron Lett., pp.386387, Aug. 1973.
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Sung-Hyun Yang
received the B.S.
and M.S. degrees in Computer and Communication Engineering from Chungbuk
National University, Cheongju, Korea in
1999 and 2001, respectively. He is currently pursuing the Ph.D. degree in Computer and Communication Engineering at
the Chungbuk National University, Korea.
His research interests are highspeed and low-power circuit, CMOS active pixel image sensor, analog-to-digital
conversion, and continuous-time lter designs.

Younggap You
received the B.S. degree in Electronic Engineering from the
Sogang Jesuit University, Seoul, Korea
and the M.S. and Ph.D. degrees in Electrical Engineering from the University of
Michigan, Ann Arbor, U.S.A., in 1981
and 1986, respectively. From 1975 to
1979, he was with the Agency for Defense Development, Korea, where he was
involved in high speed digital design. He
worked as a principal engineer at LG
Semiconductor, inc., Seoul, Korea, form 1986 to 1988. He is
currently a Professor in Dept. of Computer and Communication
Engineering at Chungbuk National University, Cheongju, Korea.
His research interests are fault tolerant computing, computer architecture, cryptography, cellular system design, and frequency
synthesis technology.

Kyoung-Rok Cho
received the B.S.
degree in Electronic Engineering from
Kyoungpook National University, Taegu,
Korea in 1977, and M.S. and Ph.D. degrees in Electrical Engineering from the
University of Tokyo, Tokyo, Japan, in
1989 and 1992, respectively. From 1979
to 1986, he was with TV research center of Gold Star Company in Korea. He
is currently a Professor in Dept. of Computer and Communication Eng. of Chungbuk National University, Korea, since August 1992. His research
interests are in the eld of high-speed and low-power circuit design, and ASIC design for communication system. From 1999
to 2000, he was a visiting scholar at Oregon State University,
OR. He is a member of Institute of Electrical and Electronics
Engineer (IEEE), and Korea Institute Tele-communication Electronics (KITE).