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Section-B
Sunder Deep Group of Institutions
Department of Electronics & Communication Engg.
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13. Define the term pull-up and
pull-down network used
in an inverter circuit. Will NMOS
and PMOS alone be used
for PUN as well as PDN ? Give reasons in support of your answers.
14. Explain the difference between polycide and silicide CMOS process.
Which would be likely to have higher performance and why.
15. List the parameters that affect the threshold voltage of a MOS
transistor. What is effect of high-K dielectric when used instead of SiO2
in MOSFET?
16. Which polysilicon gate ( n+ or p+) are preferred and why? Does the
present technology
17. In which region I-V characteristics the MOSFET simply acts as a like
a resistor? How does the gate voltage modify its resistivity?
18. Comparison the pass transistor logic circuit with that of transmission
gates.
19. What is the basic difference between diffusion and ion implantation
process? Why ion-implantation is preferred in modern VLSI Design
20. Explain symbol , different colours and lines used for drawing stick
diagram. Draw a stick diagram of CMOS inverter.
21. Draw a stick diagram for 2 input NAND Logic Gate using CMOS
Logic.
Section-B
21. Sketch the cross section and explain the operation of n-channel
enhancement type MOS transistor. Draw the characteristics of the
device. How many diffusion steps are required to form it.
22. What are different methods for CMOS fabrication process? Explain
any one of them in detail with suitable diagram.
23. Draw and Explain N-MOS inverter with enhancement mode pull up
and its transfer characteristics. Why depletion load is preferred compared
to enhancement load.
24. What a VLSI design rules? Why it is required? Describe the Lambda
based design rules and layout methodology for CMOS circuit design.
Explain with suitable diagram.
25. What do you mean by sheet resistance? Explain how the sheet
resistance concept is applied to MOS transistor and inverter.
26. Describe the standard cell based design. Enlist the various standard
cell library. What is the parameter of good VLSI Design?
27. Write a short note on Built-in-self test (BIST) techniques
28. Draw and explain the generic FPGA architecture. Discuss the
various programming technique employed in FPGA. Explain with
suitable sketch.
29. What is VLSI testing? Explain different types of fault models used in
VLSI testing.
30. Discuss stuck at fault model. Explain a stuck at 1/0 mode for testing a
logic gate with suitable example.
Section-B
38. Enlist the classification of CMOS digital logic families. Why CMOS
VLSI Design is better techniques than its counterpart.
39. Explain the Concept of regularity, modularity, semi custom and full
custom styles of VLSI system design.
40. Explain the scaling down of MOS transistor using Constant field
Scaling and its limitations.
42. Prove that pull-up to pull-down ratio for an NMOS inverter driven by
another NMOS inverter is 4/1.
43. Calculate the delay involved in cascade pass transistors.
Section-B
Section-B
49 .Draw six transistors SRAM cell and explain Different modes of
operation.
50. Draw a CMOS shift register circuit.
51. Draw CMOS SR and JK FLIP Flop.
52. Implement the Boolean function f(A, B, C) = A. BC + ABC +
ABC using COMS logic.
53. Derive the expression for VIH, VIL, NML, and NMH for CMOS inverter.
54. Explain CMOS edge triggered flip flop with help of input and output
waveforms.
Section-B
Section-B
10. What is Flash Memory ? Explain NAND flash memory cell.
11. Explain the classification of Dynamic CMOS logic circuit and design
a 2 input EXOR logic Gate using Domino logic.
Section-B
1. Explain the effect of constant voltage scaling on delay and power delay
product.
2. Explain the term voltage bootstrapping in CMOS logic with suitable
example.
3. Explain various types of power dissipation in CMOS circuits.
4. Write a short note on adiabatic logic circuit. Differentiate between single
struct-at fault and multiple struct-at fault.
5. Define the term controllability and observability. Discuss in brief Ad-hoc
testable design techniques.
6. Write a short note on Built-in-self test (BIST) techniques
7. Explain the following :
(i) Scan Based Technique.
(ii)
Fault
Section-B