Beruflich Dokumente
Kultur Dokumente
AMBA 2.0
Advanced System Bus (ASB)
Advanced Peripheral Bus (APB2 or APB)
AMBA 3.0
Advanced eXtensible Interface ( AXI v1.0)
Advanced High-performance Bus Lite
(AHB-Lite v1.0)
Advanced Peripheral Bus (APB3 v1.0)
Advanced Trace Bus (ATB v1.0)
AMBA 4.0
AXI Coherency Extensions (ACE)
AXI Coherency Extensions Lite (ACE-Lite)
Advanced eXtensible Interface 4 (AXI4)
Advanced eXtensible Interface 4 Lite (AXI4Lite)
Advanced eXtensible Interface 4 Stream (AXI4-Stream v1.0)
Advanced Trace Bus (ATB v1.1)
Advanced Peripheral Bus (APB4 v2.0)
AMBA defines both a bus specification and a technologyindependent methodology for designing, high-integration
embedded controllers. Advanced eXtensible Interconnect
(AXI4.0) was introduced in AMBA 3.0 as the successor on-chip
bus protocol of the AHB in AMBA 2.0. The AXI4.0 protocol is a
high-performance and high bandwidth bus includes a number of
features that make it suitable for high-speed submicrons
interconnect.
1.1 AMBA axi4.0 Architecture
AMBA AXI4 supports burst and unaligned data transfers. In
AMBA AXI4.0 system i n t e r fa c e 16 masters to slaves. Each
master and slave has their own 4 bit identification tags. .
AMBA AXI4 system c o n s i s t s o f m a s t e r , s l a v e a n d
b u s i n t e r c o n n e c t s . The AXI4.0 consists of five channels
namely write address, write data, read data, read address, a n d
w r i t e r e s p o n s e ch an n el s.
The A X I 4 . 0 protocol supports the following mechanisms:
Burst and unaligned data transfers and up-dated write
r e s p on s e a ckn owl e d g m en t .
A burst data bits wide 8, 16, 32, 64, 128, 256,512 or
1024 bits.
Updated AWCACHE and ARCACHE signalling
details.
300
www.iaetsd.in
301
www.iaetsd.in
2. PROPOSED WORK
The AXI4.0 to APB4.0 Bridge provides an interface between the
high-performance AXI domain and In this proposed work data
transactions can be done between high speed AXI4.0 bus to low
power APB4.0 bus using asynchronous FIFO.Which act as a
interface between them. Read and write transfers on the AXI4.0
bus are converted into corresponding transfers on the APB4.0.
2.1 Asynchronous FIFO
Asynchronous FIFOs are widely used in the computer
networking industry to receive data at a particular clock and
transmit them at another clock. An asynchronous FIFO has two
different clocks one for read and one for write. There are issues
that arise when passing data over asynchronous clock values.
Data could be over-written and hence lost when the write clock is
faster than the read clock, . In order to overcome these problems,
control signals like write pointer, read pointer, empty and full
flags are required.
302
www.iaetsd.in
the write pointer will equal array _size -1. This means that the
last location in the array is the next location that will be written
to. At this condition, the write pointer to become 0 due to write,
and set full. Note that in this condition the write pointer and read
pointers are equal, and not empty or null but the FIFO said to be
full. This implies that the FIFO full/empty decision depends on
the write pointer and read pointers when they will become equal
due to the read or write operation between them but not based on
the pointer values alone. When the pointer equality is a reset or a
read, the FIFO said to be empty; if the cause is a write, the FIFO
said to be full.
Now consider that we begin a multiple reads. The read pointer is
incremented by each read operation till the point where the read
pointer equals array_ size -1. At this point, the data from this
location of RAM or array size is available on the output bus of
FIFO.Succeeding logic reads this data and provides a read signal
(active for one clock). And hence the read pointer to become
equal to the write pointer again (after both pointers have
completed one cycle through the array). However, empty is set
since pointers are equal due to read operation.
303
www.iaetsd.in
304
www.iaetsd.in
3. CONCLUSION
305
www.iaetsd.in
4. FEATURES
5. FUTURE SCOPE
[5]
http://www.arm.com/products/system-ip/amba/ambaopenspecifications.php
[6]
ARM, "AMBA Protocol
Specification 4.0",
www.arm.com, 2010 ARM,AMBA Specification
[7] LogiCORE IP AXI to APB Bridge (v1.00a) DS788 June
22, 2011 Product Specification.
[8] Simulation and Synthesis Techniques for Asynchronous
FIFO Design Clifford E.Cummings, Sunburst
Design, Inc. SNUG San Jose 2002 Rev 1.2.,FIFO
Architecture, Functions, and Applications SCAA042A
November 1999.
[9]
Lahir, K., Raghunathan A., Lakshminarayana G.,
LOTTERYBUS: a new high-performance
communication architecture for system-on- chip deisgns,
in Proceedings of Design Automation
Conference, 2001.
[10] Ying-Ze Liao, "System Design and Implementation of AXI
Bus", National Chiao Tung University,
October 2007.
AUTHOR BIOGRAPHY
6. ACKNOWLEDGMENT
I A VIJAY KUMAR would like to thank Assistant Prof T.
Vinaysimha Reddy, who had been guiding through out to
complete the work effectively and successfully, and would also
like to thank the Prof.P Sanjeeva Reddy HOD, ECE Department
and other Professors for extending their help & support in giving
technical ideas about the paper and motivating to complete the
work effectively & successfully.
7. REFERENCES
ARM, AMBA Specifications (Rev2.0). [Online]. Available
at http://www.arm.com, 1999
[2] ARM, AMBA AXI Protocol Specification (Rev 2.0),
Available at http://www.arm.com, March 2010
[3] Shaila S Math, Manjula R B, Survey of system on chip
buses based on industry standards, Conference on
Evolutionary Trends in Information Technology(CETIT),
Bekgaum,Karnataka, India, pp. 52, May 2011
[1]
[4]
Design and Implementation of APB Bridge based on
AMBA 4.0 (IEEE 2011), ARM Limited.
306
www.iaetsd.in