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e-ISSN: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 1, Ver. 1 (Jan - Feb. 2015), PP 36-44
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Abstract: With the recent rapid advances in multimedia and communication systems, real-time signal
processing like audio signal processing, video/image processing, or large-capacity data processing are
increasingly being demanded. The multiplier and multiplier-and-accumulator (MAC) are the essential
elements of the digital signal processing such as filtering, convolution, and Inner products.
Index Terms: Booth multiplier, carry save adder,Booth multiplier,Digital signal processing(DSP), multiplier
and-accumulator(MAC).
I.
Introduction
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(3.4)
(3.5)
(3.6)
(3.7)
GROUP
GROUP2
GROUP3
GROUP4
GROUP5
DELAY
11
13
16
19
AREA
57
87
117
147
DELAY
3
3
3
6
AREA
5
4
6
13
Table 3.2. Delay and Area Count of the Basic Blocks of CSLA
BINARY VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BEC-1
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
DOI: 10.9790/2834-10113644
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DELAY
13
16
19
22
AREA
43
61
84
107
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DOI: 10.9790/2834-10113644
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References
[1].
[2].
[3].
[4].
[5].
Fayez Elguibaly, A fast parallel multiplier accumulator using the modified booth algorithm, IEEE Trans on Circuits and
systems,vol.47,September 2000
Young-Ho Seo,Dong Wook Kim, A New VLSI Architecture of Parallel Multiplier and Accumulator Based on Radix-2 Modified
Booth Algorithm,IEEE Trans.on VLSI,vol.18,February 2012
B Rajani kumari,K.V Ramana Rao,Dynamic Power Suppression Technique in Booth Multipliers,IJITEE 2278-3075, Volume-1,
Issue-4, September 2012
G.Sasi,Design of Low Power /High Speed Multiplier Using Spurious Power Suppression Technique IJCSMC, Vol. 3, Issue. 1,
January 2014, pg.37 41
R.Sheshadri M.E, Spurious Power Suppression Technique for VLSI Architecure,IJCSE Vol. 3 No.6 Dec 2012-Jan 2013
DOI: 10.9790/2834-10113644
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