Sie sind auf Seite 1von 5

Multiple Choice Questions

Chapter 2
Each question has four choices. Choose most appropriate choice of the answer.
1. 8051 has following SFRs. (i) A, B and PSW (ii) P0, P1, P2 and P3 (ii) DPH and
DPL (iii) SCON, TCON, SBUF, TMOD, TH1, TL1, TH0 and TL0 (iv) PCON (v) IE
and IP
(a) all except i

(b) all except iv

(c) all except v

(d) all are correct

2. Program memory in 8051 is (a) 64 kB external (b) 64 kB total external plus internal
(c) 64 kB internal (ii) 64 kB external plus 4 kB internal
3. 8051 has (i) internal bus width of 8-bits (ii) separate external address cum data bus
width of 16-bits. (iii) four ports (iv) one port can be used as AD0-AD7 and another as
A8-A15 (v) stack pointer address of 16-bit (vi) 32 bytes in four register banks and in
addition 32 bytes internal RAM between 00H and 1FH (vii) four register banks,
which can also be used as internal RAM between 00H and 1FH (total 32 bytes) (viii)
SFRs between addresses 00H and FFH.
(a) i, iii, iv, vii

(b) all except vii

(c) all except v and vii (d) all are correct

4. (i) The processor issues the address of the instruction byte or word to the memory
system through the address bus. (ii) A control bus has signals to control the timing of
various actions during interconnection (iii) The processor issues the address of the
instruction byte or word to the memory system and address of the IO ports and
devices. (iv) A control bus has signals to control the timing of various actions during
interconnection including the interrupt and DMA handling to control the timing of
various actions during interconnection (v) the data bus is used to fetch data from
memory (vi) the data bus is used to fetch data from IO ports and devices
(a) i, ii, iv, v (b) i, ii, iii, v and vi (c) all are correct (d) i, ii, iv, and vi
5. Serial interface in 8051 has following serial communication mode (a) one full duplex
synchronous and three half duplex asynchronous (b) three full duplex asynchronous

Embedded Systems..Arhitecture, Programming and Design

and one half duplex synchronous (c) four asynchronous UART modes (d) four
synchronous serial.
6. Eight Port P3 pins 0 to 7 can function as (i) P3.0, ., P3.7 (ii) RxD, TxD, INT0,
INT1, T0, T1, WR, RD (iii) Sync data , Sync clock, GT0, GT1, T0, T1, WR, RD (iv)
P3.0, P3.1, P3.2, P3.3, P3.4, P3.5, WR, RD (v) P3.0, P3.1, GT0, GT1, T0, T1, WR,
RD (vi) Sync data , Sync clock, GT0, GT1, T0, T1, RD, WR (vii) RxD, Sync clock,
GT0, GT1, T0, T1, RD, WR
(a) i, ii, iii, iv and v (b) i, ii, iv, v (c) vi and vii (d) ii, iii, iv and v
7. An interrupt driven IO is used (a) to handle synchronous input-outputs (b) as interrupt
service routine executes fast (c) because the events are asynchronous and during the
interval for wait for data the processor can perform other tasks (d) because the events
are synchronous and processor can simultaneously perform other tasks
8. When the number of devices or systems need the use of the bus then (a) independent
bus request method ensures access to all at the same instant (b) polling requesting bus
ensures fastest access to device needing the bus (c) daisy chain method of bus
arbitration is used for devices/systems are granted bus accesses in order of increasing
priority, low priority first and higher next (d) daisy chain method of bus arbitration is
used for devices/systems are granted bus accesses in order of decreasing priority, high
priority first and lower next
9. (a) Advance processing unit have a common cache for data and instructions (b) Use
of caches makes pipeline functioning faster (c) Instruction cache sequentially stores,
like an instruction queue, the instructions in FIFO mode and lets the processor
execute instructions at great speed while, through pre-fetch control unit the processor
accesses external system-memories at relatively much slower speeds (d) Advanced
processing units include instruction pipelining unit so that its execution unit can
process fast.
10. 80x86, Pentium, Itanium architectures have DI (i) 8-bit, 16-bit, 32-bit and 64-bit
general purpose registers (ii) 8-bit, 16-bit, and 32-bit general purpose registers, no
64-bit registers (iii) memory mapped IOs (iv) CS, DS, SS, ES, FS and GS 16-bit
segment registers (v) CS, DS, SS and ES 20-bit segment registers (vi) three pointer
registers IP, SP and BP (vii) two pointer registers used as index SI and DI
(a) ii, iii, v and vi (b) i, iii, v and vi (c) i, iv, vi and vii (d) ii, iii, iv, vi and viii

Chapter 1 Solutions to Review Questions


3

11. ARM 9/9/11 (a) processes the 32-bit instructions from the external memory (b)
processes the 32-bit as well 16-bit instructions from the external memory, depending
upon instruction set mode (c) 3 stage pipeline (d) 224 interrupt vector addresses for
software interrupt instruction and 8086 has 28 interrupt vector addresses for software
interrupt instruction.
12. (i) System bus interconnects the subsystems interconnects the processor with the
memory systems and may not connect to the set of signals called I/O bus. (ii) Twolevel bus architecture enables interface using an I/O bus to I/O devices, with specific
interfaces for each I/O device (iii) two-level bus architecture using an I/O bus allows a
computer to interface with a wide range of I/O devices, without having to implement a
specific interface for each I/O device (iv) An I/O bus supports a specific set of devices,

not allowing users to add devices to a system after it has been hardwired. (v) Devices
can be designed to interface with the IO bus, allowing them to be compatible with any
system that uses the same type of I/O bus. (vi) The I/O bus creates an interface
abstraction that follows the processor to interface with a wide range of I/O devices
using a very limited set of interface hardware
(a) i, ii, iv, v and vii (b) i, iii, v, vi (c) iii, v and vi (d) all except ii
13. (i) ARM7 has Princeton memory architecture. ARM9 processor has Harvard architecture. (ii)
ARM has 32-bit architecture but supports 16 bit or 8 bit data types also (iii) ARM is
programmable as little endian or big endian data alignment in memory (iv) Faster
implementation is due to the instant availability of the register word to the executionunit. (v) Reduced code lengths are due to Most instructions use registers as operands.
(vi) Few bits in the instruction specify a register as operand. 8, 16 or 32 bits specify a
memory address as operand and the displacement bits in the instruction (vii) ARM7
and ARM9 microprocessors have a combination of RISC and CISC features ARM
supports to a complex addressing modes based instruction set. (viii) ARM processor

Embedded Systems..Arhitecture, Programming and Design

has an RISC core for processing. (ix) There is an in-built compilation unit. It first
compiles the CISC instructions into RISC formats, which are then implemented by
the RISC core of the processor. (x) Internally the implementation for many
instructions is like in an RISC (without the micro-programmed unit).
(a) all except vii and ix (b) all correct (c) all except i and v (d) all except i and ii
14. SHARC has SHARC provides (i) two word sizes 32-bit and 48-bit (ii) two word sizes 32bit and 64-bit (iii) two full sets of 16 general-purpose registers for the fast context switching
(iv) four full sets of 16 general-purpose registers for the fast context switching (v) registers
of 32-bit and a few special registers l of 48 bits that may also be accesses as pair of 16-bit and
32-bit registers (vi) ON chip memory of 1 MB (vii) ON chip memory of 8 MB (viii) OFF
chip as well as ON-chip Memory can be configured for 32-bit or 48 bit words. (ix) two set of
32-bit and one set of 128-bit address buses and two sets of 128-data buses (x) two sets of 32bit and one set of 128-bit address buses and two sets of 32-bit and one set of 128-bit address
buses.

(a) ii, iii, v and vii (b) i, iii, v, vi, viii and ix (c) all except i and v (d) all
VelociTI TM VLIW architecture extension has (i) packed
data processing (ii) parallel execution Octal 16-bit MAC / Quad 8-bit MAC units (iii)
Level 4 Cache and (iv) instruction packing unit

15. DSP TMS320C64x64

TM

(a) ii and iii (b) i and ii (c) all (d) i and iv


16. A simple model (a) for RAM and ROM both is random-access model of memory
when all memory operations take the same amount of time independent of the address
of the byte or word at the memory (b) for ROM is not random-access model of
memory when all memory operations take the same amount of time independent of
the address of the byte or word at the memory (a) for RAM and ROM both is randomaccess model of memory but all memory operations take the different amount of time
dependent of the address of the byte or word at the memory (a) for RAM only is
random-access model of memory when all memory operations take the different
amount of time dependent of the address of the byte or word at the memory

Chapter 1 Solutions to Review Questions


5

17. A processor having Harvard architecture in main memory has (i) distinct address

spaces for accessing the program memory and data memory, (ii) distinct control
signals for accessing the program memory and data memory, (iii) distinct processor
instructions for accessing the program memory and data memory, (iv) distinct data
paths for the bytes for data and for the program, (v) helps easier handling of streams
of data that are required to be accessed in cases of single instruction multiple data
type instructions and DSP instructions.
(a) all correct (b) i, iii, iv and v (c) i, ii, iv (d) i, iii and iv
18. (a) RISC (b) CISC (c) VLIW (d) Superscalar processors possess hardware for
instruction-level parallelism from sequential programs and possess hardware to
efficiently take care of the collisions in execution unit and of data and control hazards
in pipeline.
19. (a) EPROM is an electrically erasable and device programmer Programmable Read
Only Memory (b) all addresses in flash memory are erasable in single cycle (c) in a
strict sense, ROM means a masked ROM made at a foundry from the programmers
ROM (d) RAM is programmable using a device programmer Read Only Memory
image file.
20. Dhrystone is a (a) benchmarking program, which measures the performance of a
processor for processing integers and strings (characters) (b) unit of performance with
1 MIPS = 1957 Dhrystone/s (c) benchmarking program, which measures a C program
performance for processing integers (d) program for strings processing in DSPs
.

Solutions to Multiple Choice Questions


1.

2.

3.

4.

d
11.
b

b
12.
c

a
13.
b

c
14.
b

Chapter 2
5.
6.
b
a
15.
16.
d
a

7.

8.

9.

c
17.
a

d
18.
d

c
19.
c

10.
c
20.
a