DebuggingUVM PDF

Debugging UVM
Product Version 13.2

January 2014
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Debugging UVM
Contents
Introduction to SimVision for UVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Starting a UVM Debugging Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Probing UVM Objects to the Simulation Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Using the UVM SystemVerilog Debugging Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Using the UVM Toolbar and Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Displaying UVM Test Environment Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Managing the UVM Configuration Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Recording Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Configuring Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Running the Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Showing Objections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Viewing the SystemVerilog Unified UVM Hierarchy in the Design Browser . . . . . . . . . . . 19
Viewing UVM Objects in the Design Browser in Interactive Mode . . . . . . . . . . . . . . . 20
Viewing UVM Objects in the Design Browser in Post-Processing Mode . . . . . . . . . . 22
Displaying UVM Base Clases in the Design Browser . . . . . . . . . . . . . . . . . . . . . . . . . 24
Viewing UVM Class Objects in the Class Browser Sidebar . . . . . . . . . . . . . . . . . . . . . . . 25
Displaying Logical Path Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Displaying UVM Base Classes in the Class Browser . . . . . . . . . . . . . . . . . . . . . . . . . 27
Viewing UVM Objects in the Waveform Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Using Windows Designed for SystemVerilog UVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
The UVM Register Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Opening the UVM Register Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Register Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing Registers and Register Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sending Registers to Other SimVision Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the UVM Sequence Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Opening the UVM Sequence Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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All Rights Reserved.
Debugging UVM
Using the Navigation Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Sequencers Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Sequence Types Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Sequence Hierarchy Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Sequence Data and Methods Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Viewing a Sequence Class Definition in the Source Browser . . . . . . . . . . . . . . . . . . . . .
See Also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sending a Sequence to the Waveform Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Debugging UVM
1
Introduction to SimVision for UVM
SimVision is the unified graphical debugging environment for the Cadence Incisive Simulator.
You can use SimVision to debug digital, analog, or mixed-signal designs and testbenches
written in Verilog, SystemVerilog, VHDL, SystemC, e, or a combination of those languages.
SimVision tailors itself to the language or languages that make up your test environment. That
is, windows, toolbars, and menu choices are added or removed to suit the test environment.
When the test environment contains UVM, for example, SimVision adds the UVM Register
Viewer and UVM Sequence Viewer windows to the debugging environment. Several custom
built-in layouts are provided for typical uses.
In addition to the features added to support the various programming languages, SimVision
provides the following features when UVM is detected in the design:
Built-in window layout for UVM debugging
UVM toolbar in the Console, Design Browser, and Source Browser windows
Class Debug Preferences to show or hide UVM base classes
Design Browser Preference to show or hide the UVM hierarchy
In the Design Browser window, a single UVM hierarchy is displayed for components and
transaction streams
For More Information
Starting a UVM Debugging Session on page 2
Probing UVM Objects to the Simulation Database on page 5
Using the UVM SystemVerilog Debugging Layout on page 7
Using the UVM Toolbar and Menu on page 10
Viewing the SystemVerilog Unified UVM Hierarchy in the Design Browser on page 19
Viewing UVM Class Objects in the Class Browser Sidebar on page 25
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Viewing UVM Objects in the Waveform Window on page 27
Using Windows Designed for SystemVerilog UVM on page 28
Getting Help on page 29
See Also
Introduction to SimVision
Debugging SystemVerilog
Videos
SimVision UVM Tcl Debug Commands
SimVision UVM Toolbar and Message Links
SimVision UVM Register Viewer
All SimVision Videos
Starting a UVM Debugging Session

The irun utility provides options specifically for compiling, elaborating, and simulating UVM
test environments. The following options are most commonly used:
-uvm or -ml_uvm enables UVM or multi-language UVM features, such as loading the
UVM Tcl and GUI interfaces.
-uvmtest declares the root of a multi-language test hierarchy. This option also enables
multi-language UVM features, so the -ml_uvm option is not required when you use this
option.
Other options are available to let you specify a different UVM library or to provide debugging
access to the UVM base class hierarchy.
You should also use the following options when starting a debugging session with SimVision:
-linedebug allows you to set breakpoints on lines in the source code.
-access rwc gives full read, write, and connectivity access to the objects in the test
environment. Read access is needed at a minimum to use the UVM debugging features
in SimVision.
-gui starts SimVision as the debugging environment.
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-snapshot gives access to the design snapshot when you run SimVision in
post-processing mode, so that SimVision can access information about the full test
environment.
For example:
> irun -access rwc -linedebug -gui -uvm +incdir+../sv ubus_tb_top.sv -uvmtest
sv:test_2m_4s
This example uses -access, -linedebug, and -gui to provide access to design objects
and source line numbers, and to invoke SimVision at startup. The -uvm option enables UVM
features. The +incdir+ option is used here to specify the directory in which the source files
are located. When irun looks for the top-level source file, ubus_tb_top.sv, it includes
../sv in its search path. The -uvmtest option specifies the top level of the the hierarchy,
test_2m_4s. The sv: prefix indicates that the top level is written in SystemVerilog.
This command starts SimVision with its default window layout. That is, SimVision opens a
Design Browser and a Console window, as shown in Figure 1-1 on page 4. The Design
Browser displays the design hierarchy, and the Console window lets you run the simulator and
SimVision through their Tcl command interfaces. SimVision provides several built-in layouts,
including a UVM debugging layout. It also lets you create your own layouts.
Tip
To make objects in the UVM component hierarchy visible in SimVision windows,
click Run to end of build phase,
, in the UVM toolbar.
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Figure 1-1 Starting SimVision with the ubus Test Environment
See Also
UVM Command-Line Options in the irun User Guide
Customizing the Layout of SimVision Windows in Introduction to SimVision
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Debugging UVM
Invoking SimVision in Running SimVision
Using the Console Window in Introduction to SimVision
Probing UVM Objects to the Simulation Database

Simulation databases store information about the signal transitions that occur during
simulation. You can use these files to debug your design in post-processing mode, rather than
while running the simulation. You specify the information you want to save by probing objects
to the database.
You can create probes in any of the following ways:
Send the objects you want to probe to the Waveform window. The objects are
automatically probed when you run the simulation.
Select a top-level scope, then open the Probe form and specify the objects within that
scope that you want to probe.
Issue a probe command in the simulator tab of the Console window.
For example:
1. Select ubus_tb_top in the Design Browser, then right-click and choose Create Probe
from the pop-up menu. SimVision opens the Probe form. The ubus_tb_top scope is
displayed in the list of scopes at the top of the form. You can choose the types of objects
in the area below the scope list, as shown in Figure 1-2 on page 6.
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Figure 1-2 Opening the Probe Form
2. Enable the types of objects you want to probe, such as tasks, functions, sub-scopes, and
the objects within in each scope, as shown in Figure 1-3 on page 7.
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Figure 1-3 Selecting Objects to be Probed
3. Click OK.
You can create the same probe by issuing the following command in the simulator tab of the
Console window:
ncsim> probe -create ubus_tb_top -depth all -tasks -functions -all -database waves -waveform
To minimize the size of the simulation database, UVM base class objects are not probed by
default. If you need to save this information, you can probe these base classes in either of the
following ways:
Enable Include UVM base classes in the SimVision Probe form.
Specify the -uvm option on the probe command.
See Also
probe in the Incisive Simulator Tcl Command Reference
Creating and Managing Probes in Running SimVision
Using the UVM SystemVerilog Debugging Layout

The UVM SystemVerilog Debugging layout is targeted at engineers and designers creating
SystemVerilog testbenches based on UVM. This layout opens a Design Browser, Console
window, Source Browser, Waveform window, UVM Register Viewer, and UVM Sequence
Viewer, as shown in Figure 1-4 on page 8.
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Figure 1-4 The UVM SystemVerilog Debugging Layout

Design Browser
Source Browser
Console window
(in background)
Waveform window
(in background)
UVM Sequence Viewer
UVM Register Viewer
Tip
When a window is hidden in the background. Choose the window from the Windows
menu to bring it to the foreground.
The UVM debugging layout is made up of the following windows:
Design BrowserLets you access the objects in your design and monitor the RTL
signals during simulation
Source BrowserDisplays the source code for designs and instances
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Console windowProvides access to Tcl commands for SimVision and the simulator
Waveform windowLets you view simulation data along X and Y axes
Sequence ViewerProvides a unified view of the sequence activity of a testbench
Register ViewerLets you visualize and debug the register packages in the testbench
You can specify this layout at startup, switch to the layout during a SimVision debugging
session, or set it as your default layout.
To specify the layout at startup:
Include the -layout option and specify uvmdebug as the layout. For example:
irun -s -gui -layout uvmdebug -linedebug -uvm +incdir+../sv ubus_tb_top.sv
+UVM_TESTNAME=test_2m_4s
To switch to the layout after startup:
Choose Windows Layout UVM SystemVerilog Debugging from any SimVision

window.
To set the layout as your default window layout:

1. Start SimVision.
2. Choose EditPreferences from any SimVision window.
3. Open the Layouts section of the Preferences window.
4. Choose the UVM SystemVerilog Debugging layout from the Default layout to load
when starting SimVision drop-down menu.
5. Choose the UVM SystemVerilog Debugging layout from the Default layout to load
when starting SimVision drop-down menu, as shown in Figure on page 10.
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Figure 1-5 Choosing the UVM Debugging Layout
UVM SystemVerilog
Debugging layout
When you set UVM SystemVerilog Debugging as your default layout, you do not need to use
the -layout option at startup.
See Also
Customizing the Layout of SimVision Windows
Setting Preferences
Using the UVM Toolbar and Menu

When SimVision detects UVM in the test environment, it adds a UVM toolbar to the Console,
Design Browser, Source Browser, UVM Sequence Viewer, and UVM Register Viewer
windows, and it adds a UVM menu to all the windows. Many of the toolbar buttons and menu
choices perform same functions as the UVM Tcl commands supported by the Incisive
Simulator.
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Debugging UVM
Figure 1-6 on page 11 shows the UVM toolbar. By default, the Configuration Database and
Show Objections buttons are hidden. You can add these buttons to the toolbar, or remove
any buttons that you do not use. In addition, you can choose to show or hide the toolbar.
Figure 1-6 The UVM Toolbar
Run to end of
build phase
Configure database
Set a phase
breakpoint
UVM tools menu
Access UVM help
Set message
verbosity
Run to beginning of
the next phase
Show objections
By default, the Configuration Database and Show Objections buttons are hidden. You can
add these buttons to the toolbar, or remove any buttons that you do not use. In addition, you
can choose to show or hide the toolbar.
To add the Configuration Database and Show Objections buttons to the UVM toolbar:
1. Choose View Toolbar Customize from the menu bar. This opens the Customize
Toolbars form.
2. Select UVM Controls from the toolbars list on the left side of the form. The Customize
Toolbars form displays a list of UVM toolbar buttons to the right side of the form, as shown
in Figure 1-7 on page 12.
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Figure 1-7 Selecting UVM Toolbar Items
3. Enable Configuration Database and Show Objections to add these buttons to the
toolbar, or disable any buttons that you want to remove from the toolbar.
4. Click Close when you are finished customizing the toolbar.
To show or hide the UVM toolbar:
1. Right-click on a blank space in any toolbar, or choose View Toolbars from the menu
bar, then enable or disable UVM Controls.
Displaying UVM Test Environment Information on page 13
Managing the UVM Configuration Database on page 14
Recording Transactions on page 15
Configuring Messages on page 15
Setting Breakpoints on page 17
Running the Simulation on page 18
Showing Objections on page 19
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See Also
Customizing Toolbars in Introduction to SimVision
Displaying UVM Test Environment Information

You can get information about the UVM test environment, such as information about your
factory configuration, the UVM components in your environmnt, and the version of the UVM
library that you are using.
To list information about the factory configuration:
Choose List Factory Information from the UVM tools,

, drop-down menu, or choose
UVM List Factory Information from the menu bar. This issues the following command
in the simulator tab of the Console window:
ncsim> uvm_factory -print -all_types
To list UVM components:
Choose the components you want to view from UVM tools,

from the UVM List UVM Components menu:
, drop-down menu, or
AllLists all UVM components in the test environment, by issuing the following
command in the simulator tab of the Console window:
ncsim> uvm_component -list
Top LevelLists the name, type, size, and value of the top-level UVM components,
by issuing the following command in the simulator tab of the Console window:
ncsim> uvm_components -tops
uvm_test_topLists the name, type, size, and value of the UVM components under
uvm_test_top, by issuing the following command in the Console window:
ncsim> uvm_component -describe uvm_test_top -depth -1
To display the UVM library version:
Choose UVM Library Version from the UVM tools,

, drop-down menu, or choose
UVM Show Library Version from the menu bar. This issues the following command in
the simulator tab of the Console window:
ncsim> uvm_version
See Also
uvm_factory in UVM Tcl Commands
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uvm_component in UVM Tcl Commands
uvm_version in UVM Tcl Commands
Managing the UVM Configuration Database

The UMV configuration database is a UVM resource for storing simulation information about
read/write operations to UVM components. You can turn on and off the tracing of this
information, create an audit trail of these operations, or display the information in the Console
window.
To enable or disable tracing of read/write operations to the configuration database:
Choose Configuration Database Trace ON or OFF from the UVM Tools,

,
drop-down menu, or from the UVM menu. This issues one of the following Tcl commands
ncsim> uvm_config_db -trace on
ncsim> uvm_config_db -trace off
To enable or disable logging of read/write operations:
Choose Configuration Database Audit ON or OFF from the UVM Tools,

,
drop-down menu, or from the UVM menu. This issues one of the following Tcl commands
ncsim> uvm_config_db -audit on
ncsim> uvm_config_db -audit off
To display the contents of the UVM database in the Console window:
Choose Configuration Database Dump from the UVM Tools,

, drop-down menu,
or from the UVM menu. This issues one of the following Tcl commands in the simulator
tab of the Console window:
ncsim> uvm_config_db -dump
See Also
uvm_config_db -trace in UVM Tcl Commands
uvm_config_db -audit in UVM Tcl Commands
uvm_config_db -dump in UVM Tcl Commands
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Recording Transactions
You can turn transaction recording on and off during the simulation to save transactions to the
simulation database. You can view these transaction in the Waveform window.
To turn transaction recording on:
Choose Transaction Recording ON from the UVM drop-down menu,

. or from the
UVM menu. This issues the following command in the simulator tab of the Console
window:
ncsim> uvm_set -config * recording_detail UVM_FULL
To turn transaction recording off:
Choose Transaction Recording OFF from the UVM drop-down menu,

. or from
the UVM menu. This issues the following command in the simulator tab of the Console
window:
ncsim> uvm_set -config * recording_detail UVM_NONE
See Also
uvm_set in the UVM Tcl Commands
Viewing Transactions in the Waveform Window in Using the Waveform Window
Configuring Messages
SimVision adds hypertext links to UVM messages in the Console window. These links let you
access the source code at which a message is reported, or access relevent objects in the
Design Browser. You can turn these hyperlinks off, if you are not interested in using them.
You can set the verbosity of UVM messages to determine whether a message is reported at
run time. This gives you the option of ignoring certain types of messages, depending on what
you are investigating during the debugging session.
Using Hyperlinks in UVM Messages on page 16
Setting the Verbosity of UVM Messages on page 16
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Using Hyperlinks in UVM Messages

UVM messages in the SimVision console window contain several hyperlinks. These links can:
Display the corresponding source code line in the Source Browser by clicking the
hyperlink line containing a file name.
Display the class object in the Design Browser by clicking the hyperlink portion of the line
contain a class object name.
Set the primary cursor in the target waveform window to the time appropriate time by
clicking the hyperlink timestamp.
Sequences appear as part of the design object attribute, after a @@ symbol embedded in
the hyperlink line. Clicking the hyperlink for a sequence (the hyperlink after the @@ in a
hyperlink line) displays the last transaction sent by the sequence in a watch window. See
the note below for additional details
Note: In order to view transactions, transaction recording must be enabled. If transaction
recording is not enabled, a watch window will still be opened, but its contents will be
empty.
You can click the hypertext link and perform the default action for the link, or right-click and
choose one of the following actions from the pop-up menu:
Open source code file in the Source Browser and highlight the line number that
generated the message
Display the class object from corresponding source code line in the Source Browser
Display the corresponding class object in the Design Browser
Display the corresponding class object in the Watch Window
Set the primary cursor to the appropriate time in the Waveform Window, and any other
windows that track the cursor.
Setting the Verbosity of UVM Messages

To set the verbosity of messages:
Choose the verbosity level from the UVM Verbosty,
, drop-down menu. Choices are:
NoneThe message is always reported. This setting is equivalent to UVM_NONE

verbosity level.
LowThe message is reported if its verbosity is UVM_LOW or higher.
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MediumThe message is reported if its verbosity is UVM_MEDIUM or higher.
HighThe message is reported if its verbosity is UVM_HIGH or higher.
FullThe message is reported if its verbosity is UVM_FULL or higher.
These menu choices issue a uvm_message Tcl command in the simulator tab of the
Console window. For example, if you choose the verbosity level of High, SimVision
issues the following command:
ncsim> uvm_message UVM_HIGH *
To turn hypertext links on and off:
Choose Configuration Database SystemVerilog Message Hyperlinks ON or OFF

from the UVM Tools,
, drop-down menu, or from the UVM menu. This issues one of
the following Tcl commands in the simulator tab of the Console window:
ncsim> uvm_message -hyperlinks on
ncsim> uvm_message -hyperlinks off
See Also
uvm_message in UVM Tcl Commands
Video
SimVision UVM Toolbar and Message Links
Setting Breakpoints
You can use the UVM toolbar to set breakpoints on UVM phases, and to run the simulation
to the end of any phase.
To set a UVM phase breakpoint:
Click Set Breakpoint,

are:
, and choose the phase breakpoint that you wan to set. Choices
Break on Build Phase
Break on Connect Phase
Break on End-of-Elaboration Phase
Break on Start-of-Simulation Phase
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Break on Run Phase
Break on Extract Phase
Break on Check Phase
Break on Report Phase
Break on Finalize Phase
The breakpoints you create in this way are added to the Breakpoints page of the Properties
window. In this window, you can add more breakpoints, enable and disable breakpoints, and
delete breakpoints.
See Also
uvm_phase in UVM Tcl Commands
Managing Breakpoints in the Properties Window in Running SimVision
Running the Simulation

You can use the UVM toolbar to run the simulation from one UVM phase to the next.
To run the simulation to the end of the build phase:
Click Run to UVM build phase done,

simulator tab of the Console window:
. This issues the following command in the
ncsim> uvm_phase -run -build_done
To run to beginning of the next phase:
Click Run to beginning of next phase,

. This issues the following command in the
Console window, where phase_name is the next phase:
ncsim> uvm_phase -run phase_name
See Also
uvm_phase in UVM Tcl Commands
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Showing Objections
If the simulation becomes stalled during a phase or at the end of a test run, it could be caused
has been raised by the UVM phasing system. You can return information about objections
raised during the current phase, or all objection from all phases.
To return objection raised during the current phased:
Choose Show Objections Current from the UVM drop-down menu,

. or from the
UVM menu. This issues the following command in the simulator tab of the Console
window:
ncsim> uvm_objection
To return objectsions raised during all phases:
Choose Show Objections ALL from the UVM drop-down menu,

. or from the UVM
menu. This issues the following command in the simulator tab of the Console window:
ncsim> uvm_objection -all
See Also
uvm_objection in UVM Tcl Commands
Viewing the SystemVerilog Unified UVM Hierarchy in the

Design Browser
The Design Browser scope tree shows all of the objects that make up the test environment,
as follows:
The UVM component hierarchy displays the user-defined UVM components and any
sequence transactions created during simulation.
The design hierarchy displays the scopes defined by the DUT.
The Packages hierarchy displays the packages that are included in the test environment.
All objects in the SystemVerilog UVM component hierarchy have both a logical name,
beginning with $uvm, and a physical name, ending with an @-sign and instance number. The
$uvm notation is a short-hand representation of the physical name. The logical name shows
up in tooltips and in the status bar of SimVision windows when you hover over these objects.
You can also refer to these objects by their logical name in Tcl commands.
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Due to the way UVM components are recorded in the simulation database, these objects are
placed in different locations in the hierarchy, depending on whether you are running the
simulation interactively or in post-processing mode.
Tip
UVM components and transactions are dynamic objects. You must click Run to end
of build phase,
, to see these objects in the Design Browser.
Viewing UVM Objects in the Design Browser in Interactive Mode on page 20
Viewing UVM Objects in the Design Browser in Post-Processing Mode on page 22
Displaying UVM Base Clases in the Design Browser on page 24
See Also
Using $uvm to Represent UVM Pathnames in the Incisive Simulator Tcl Reference
Accessing Design Objects in Using the Design Browser
Viewing UVM Objects in the Design Browser in Interactive Mode

When you run a simulation interactively, the Design Browser places the user-defined UVM
components and sequence transactions at the top of the scope tree under the UVM folder, as
shown in Figure 1-8 on page 21. This top-level for UVM components is equivalent to the $uvm
logical pathname.
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Debugging UVM
Figure 1-8 Scope Tree in Interactive Mode
UVM Component Hierarchy

DUT Design Hierarchy
Packages Hierarchy
When you select a UVM component from the scope tree, the signal list displays the
component and its subcomponents. The selected component is displayed at the top of the
list, and its subcomponents are expanded below it. For example, in Figure 1-9 on page 22,
ubus0 is selected in the scope tree, and displayed in the signal list with its sub-components.
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Debugging UVM
Figure 1-9 Displaying UVM Components in the Signal List
You can expand and collapse subcomponents, or make a subcomponent the top of the
hierarchy in the signal list.
To expand a subcomponent:
Click the + next to the component name. Its subcomponents are added to the list, and
the + changes to a -.
To collapse a subcomponent:
Click the - next to the component name. The subcomponents are removed from the list,
and the - changes to a +.
To make a subcomponent the top of the hierarchy:
Click UVM,
, to the left of the component name.
Viewing UVM Objects in the Design Browser in Post-Processing Mode

When you record data to a simulation database, sequence transactions are written to the
UVM component hierarchy, using the $uvm logical name. Therefore, when you run the
simulation in post-processing mode, the Design Browser displays the sequence transactions,
under the UVM component hierarchy, and when you select a sequencer, its recorded
sequences are displayed in the signal list, as shown in Figure 1-10 on page 23.
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Debugging UVM
Figure 1-10 Displaying Sequence Transactions in Post-Processing Mode
Class objects are not recorded by their $uvm logical name. Therefore, the Design Browser
displays the user-defined class hierarchy in the Packages folder, as shown in Figure 1-11 on
page 24. Because class objects are not recorded under $uvm, you cannot see their
subcomponents in the signal list. Furthermore, to see the UVM class hierarchy, you must load
the snapshot into SimVision, in either of the following ways:
Use the -snapshot option on the simvision command line. For example:
> simvision -snapshot ubus_tb_top waves.shm
In the Design Browser window, right-click the database name at the top of the scope tree,
and choose Explore Full Design from the pop-up menu.
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Debugging UVM
Figure 1-11 Displaying the UVM Component Hierarchy in Post-Processing Mode
Also keep in mind that in post-processing mode, the Design Browser can show only the
objects you have recorded. This is true of non-UVM objects, as well as UVM objects.
Displaying UVM Base Clases in the Design Browser

By default, the scope tree in the Design Browser sidebar lists only classes that are defined by
you. Classes and class fields that are defined in the UVM class library are filtered by default.
These UVM base classes are listed under Packages in the Design Browser scope tree. A
filter icon and an ellipsis are displayed at their location in the hierarchy, as shown in
Figure 1-12 on page 25.
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Debugging UVM
Figure 1-12 Filtering UVM Base Classes from the Design Browser
Filter icon
To turn off filtering of UVM base classes in any of the following ways:
Right-click the filter icon,

menu.
Click UVM,
, in the UVM toolbar and enable Display UVM Base Classes in the
drop-down menu.
Choose Edit Preferences from the menu bar, then select Class Debug from the list
of the left side of the Preferences form, and enable Display UVM Base Classes.
, and enable Display UVM Base Classes in the pop-up
Viewing UVM Class Objects in the Class Browser Sidebar

The Class Browser sidebar lets you browse the class hierarchy in your design. The sidebar
is present in the Design Browser and Source Browser windows. The sidebar itself behaves
the same in both windows, but it interacts with each window in a slightly different way:
In the Design Browser, you use the sidebar to select the class objects you want to
monitor. The default operation when you double-click on a class is to go to the class
definition.
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Debugging UVM
In the Source Browser, you use the sidebar to locate class definitions in the source code.
Displaying Logical Path Names on page 26
Displaying UVM Base Classes in the Class Browser on page 27
See Also
Viewing Classes in the Class Browser in Debugging SystemVerilog
Displaying Logical Path Names

When you select a class object that is a UVM component in the object list of the Class
Browser sidebar and send that object to another window, or route it to another pane of the
same window, the UVM component-based logical path is displayed.
For example, if you send a physical class object, such as ubus_master_monitor@5030_7,
from the Class Browser sidebar to another window, the UVM logical path of that object is
displayed as $uvm:(uvm_test_top.ubus_example_tb0.masters[1].monitor).
The following windows convert the UVM component physical class objects to UVM
component-based logical path objects:
Object list of the Class Browser sidebar
Call stack of the Source Browser
Class variables in the Design Browser signal list
Class variables in the Watch Window
Class objects in the SystemVerilog Data Browser
In addition to sending class objects from one window to another, the same method applies to
sending objects from one window region to another in the same window. For example, when
the Class Browser sidebar is displayed in the Source Browser and you select a class object,
if that class object has a UVM logical path, then the logical path based scope is displayed as
the scope in the Source Browser instead of the physical class object.
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Displaying UVM Base Classes in the Class Browser

By default, UVM base classes are filtered from the Class Browser. However, you can display
these base classes, if you need to see them.
To show UVM base classes from the UVM toolbar:
Enable Display UVM Base Classes in the UVM drop-down menu on the UVM toolbar.
To show UVM base classes by setting a Class Browser preference:

1. Choose Edit Preferences from any SimVision window, then select Class Debug
from the list on the left side of the window, or click Options . in the Class Debug sidebar.
SimVision opens the Class Browser Options form, as shown in Figure 1-13 on page 27.
Figure 1-13 The Class Debug Options Form
2. Enable Display UVM Base Classes if you want to show these classes in the Class
Browser, or disable the option to hide these classes.
The Class Browser Options settings are linked to the Class Debug Preference page, so that
when you change the setting in one window, the change is also applied to the other.
Viewing UVM Objects in the Waveform Window

SystemVerilog UVM components are added to the Waveform window as scopes. You can
then expand the scope to see the objects contained within the component, as shown in
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Figure 1-14 Adding uvm_test_top to the Waveform Window
When you set the signal list to display signal names in Path.Name format, SystemVerilog
UVM class objects are displayed by their logical name, beginning with $uvm, as shown in
Figure 1-15 Displaying the Path .Name of SystemVerilog UVM Objects
SystemVerilog UVM class objects

displayed in Path.Name format
This logical name is also displayed in the status bar when you hover the cursor over the UVM
class object.
Using Windows Designed for SystemVerilog UVM

In addition to the standard windows for graphical debugging, SimVision also provides the
following windows specifically to help debug SystemVerilog UVM test environments:
Register Viewer
The UVM Register viewer supports the register model defined in the UVM_REG register
and memory specification, as well as the register model defined in the UVM e register
and memory package, named vr_ad. You use the UVM Register Viewer to visualize and
debug the register packages in Incisive.
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Debugging UVM
Sequence Viewer
The UVM Sequence Viewer provides a unified view of the sequence activity of a
testbench. The UVM Sequence Viewer can help you understand the relationship
between sequencer components and the sequences running on them, as well as the
hierarchical nature of those sequences.
The UVM Register Viewer on page 31
Using the UVM Sequence Viewer on page 43
Getting Help
The Help menu on all SimVision windows gives you access to the documentation in the
Cadence Help Library. In addition to the Help menu on all SimVision windows, the following
Help links are available on the UVM toolbar:
CDNS Docs UVM help Introduction

Opens the UVM Introduction to a list of UVM-related documentation in the Cadence Help
system.
UVM Commands
Invokes one of the following UVM help commands in the simulator tab of the Console
window:
Transaction RecordingIssues the help uvm_set command
System Verilog Message HyperlnksIssues the help uvm_message command
List Factory Information Issues the help uvm_factory command
Show ObjectionsIssues the help uvm_objection command
Configuration DatabaseIssues the help uvm_config_db command
List UVM ComponentsIssues the help uvm_component command
UVM Library VersionIssues the help uvm_version command
See Also
Getting Help in Introduction to SimVision
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2
The UVM Register Viewer
The UVM Register Viewer supports the register model defined in the UVM_REG register and
memory specification, as well as the register model defined in the UVM e register and
memory package, vr_ad. You use the UVM Register Viewer to visualize and debug the
register packages in SimVision.
Opening the UVM Register Viewer on page 31
Sending Registers to Other SimVision Windows on page 39
See Also
Register and Memory Modeling Package for e (vr_add) in the UVM e Reference
Video
SimVision UVM Register Viewer
Opening the UVM Register Viewer

To open the UVM Register Viewer:
From the UVM tools drop-down menu,
From the menu bar, choose File New UVM Register Viewer , UVM UVM
Register Viewer, or Windows New UVM Register Viewer.
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, choose UVM Register Viewer.
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Debugging UVM
<i_italics>
Tip
Like other multi-instance SimVision windows, such as the Design Browser and
Source Browser, more than one UVM Register Viewer window can be opened at the
same time. When you have multiple Register Viewer windows, only one is the target.
The target window is the one to which any operation is applied. For example, if you
select objects in one window, you can add those objects to the target window.
When the window opens, it displays the Register Block Hierarchy on the left side of the
window. When you select a register block in the hierarchy, the right side of the window
displays the registers in that block. For each register in the block, the Register Viewer displays
its name, offset, width, value, desired and mirrored values, and read/write and connectivity
access as shown in Figure 2-1 on page 32.
Figure 2-1 The UVM Register Viewer
Register block hierarchy
Registers
Status bar
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Register fields
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Debugging UVM
<i_italics>
When you hover the cursor over a register or register field, the status bar at the bottom of the
window displays the SystemVerilog path of that element, as shown in Figure 2-2 on page 33.
This is a SystemVerilog logical path if the register model was instantiated within a
uvm_component. Otherwise, it is a SystemVerilog physical path.
Figure 2-2 Register Viewer Status Bar
Path information
The SimVision UVM Register Viewer also supports the vr_ad UVM e Registers & Memory
package. Figure 2-3 on page 33 shows the UVM e Register Viewer with the vr_ad register
specification. For the vr_ad register, the Offset column is replaced by an Address column,
and the Desired and Mirrored columns are not available.
Figure 2-3 e Registers in the UVM Register Viewer
When you hover over an element in the e register hierarchy, the status bar displays the full e
path of the register (for example, sys.my_env.mem_map.xcore_regs.reg0).
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Debugging UVM
<i_italics>
Viewing Register Blocks on page 34
Viewing Registers and Register Fields on page 35
See Also
Managing Windows in Introduction to SimVision
Viewing Register Blocks

The Register Block Hierarchy displays the structural hierarchy of the registers, as shown in
Figure 2-4 on page 34. Each element of the hierarchy is shown with its name and its object
type (enclosed in parentheses). Register block hierarchy elements can be register blocks,
register maps, register files, and memories.
Figure 2-4 The Register Block Hierarchy
At simulation time 0, the Register Block Hierarchy is empty because the UVM build phase has
not completed. When the build phase is complete, the register hierarchy is filled in
automatically and fully expanded. If the simulation is reset to time 0, the Register Block
Hierarchy is cleared.
To expand a register block:
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Debugging UVM
<i_italics>
Click the + button next to the register block name. The button changes from + to .
To collapse a register block:
Click the - button next to the register block name.
If there are many register blocks, you can search for the registers that match a search pattern.
To search for register blocks:
In the Find field, enter a glob-style expression representing the register block name,
partial name, or type.
See Also
Searching for Objects in the SimVision Tcl Command Reference
http://www.accellera.org/home/ for information on the UVM_REG and vr_ad register

hierarchies
Viewing Registers and Register Fields

When you select a register block hierarchy element, its registers are displayed in the
Registers area of the window. You can expand a register to see the register fields, as shown
in Figure 2-5 on page 35.
Figure 2-5 Viewing UVM_Reg Register Blocks and Fields
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Debugging UVM
<i_italics>
Registers are displayed in a tree view with two levels of hierarchy. Each register can be
expanded to display the fields of that register.
To expand a register:
Click the + button next to the register name. The + button changes to a - button.
To collapse a register:
Click the - button next to its name.
To expand and collapse all registers in the register block:
Choose View Expand All or Collapse All from the menu bar, or right-click within the
Registers area of the window and choose Expand All or Collapse All from the pop-up
menu.
By default, register values are synchronized with the current simulation time. However, you
can turn off syncrhonization. The values then reflect those obtained from the SST2 database,
if you have probed that register to the database.
Values in the Register Viewer window are updated whenever simulation stops, such as at a
breakpoint. Any values that changed during the last time step are highlighted in blue and both
the previous and the current values are displayed, separated by ->, as shown in Figure 2-5
on page 35.
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Debugging UVM
<i_italics>
Figure 2-6 Viewing Register Value Changes
By default, register field values are displayed in the radix in which they are recorded.
To change the radix of register field values:
Select a radix from the Format Radix menu. The new radix is applied to all register
fields in the window. As recorded returns the values to the radix in which they were
recorded during simulation.
If you have many registers, you can filter the registers displayed in the window.
To filter registers in the window:
Enter a regular expression representing the register name, or partial name, of the
registers you want to display in the window, or precede the expression with ~ to specify
the registers you want to remove from the window. The status bar at the bottom right
corner of the Registers area shows you the number of registers currently displayed, and
the total number of registers in the test environment.
Note: The filter string is applied only to the registers themselves, not to the register
fields. Therefore, if a register is filtered, its fields are not displayed.
See Also
Manging Time in the SimVision Windows in Introduction to SimVision
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Debugging UVM
<i_italics>
Creating and Managing Probes in Running SimVision
Setting Breakpoints
You can set breakpoints on register fields, on value changes, on desired or mirrored changes,
or on method calls.
To set breakpoints on register fields:
If you select a block, a breakpoint is created for all fields of all registers in that block.
If you select a register, a breakpoint is created for all fields of the selected register.
If you select a register field, the breakpoint is created for that register field only.
To set a breakpoint on a value change:
Select a register block, register, or register field, then click Set object breakpoint,
or right-click and choose Break on value change from the pop-up menu.
To set a breakpoint on a desired or mirrored change:
Select a register block, register, or register field, then right-click and choose Break on
Desired change or Mirrored change from the pop-up menu.
To set a breakpoint on a method call:
Select a register block, register, or register field, then right-click and choose Break on
read() call, write() call, update() call, or mirror() call from the pop-up menu.
Note: The Break on menu is not shown if there are no registers contained within the register
block hierarchy element.
You can enable, disable, delete and create breakpoints, including those in UVM designs, from
the Breakpoints section of the Properties window.
See Also
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<i_italics>
Sending Registers to Other SimVision Windows

The Send To toolbar in the Register Viewer contains buttons to send registers to the
Waveform window, Source Browser, and Watch window. These windows are the most useful
for debugging UVM registers. When you send a register to these other windows, you send the
SystemVerilog class object associated with the register.
To send UVM registers to the Waveform window:
Select the register, or registers, and click Send to Waveform,

Send to Waveform from the menu bar.
, or choose Windows
The register is displayed in the Waveform window in a collapsed state, as shown in Sending
a Register to the Waveform Window on page 39.
Figure 2-7 Sending a Register to the Waveform Window
You can expand the register by clicking the + button next to the register name in the signal list.
To send a register to the Source Browser:
Select the register and click Send to Source Browser,

, or choose Windows
Send to Source Browser from the menu bar, or right-click and choose Send to
Source Browser from the pop-up menu.
The Source Browser opens at the register definition, pointed to by a blue arrow, as shown in
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Debugging UVM
<i_italics>
Figure 2-8 Sending a Register to the Source Browser
To send the register to the Watch window:
Select the register and click Send to Watch Window,

, or choose Windows Send
to Watch Window from the menu bar, or right-click and choose Send to Watch
Window from the pop-up menu.
The register and all of its elements are sent to the Watch window in their expanded state, as
shown in Figure 2-9 on page 41.
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Debugging UVM
<i_italics>
Figure 2-9 Sending a Register to the Watch Window
See Also
Introduction to the Waveform Window in Using the Waveform Window
Accessing the Design Source Code in Using the Source Browser
Monitoring Signal Values in the Watch Window in Using the Watch Window
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<i_italics>
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3
Using the UVM Sequence Viewer
Sequences are a powerful tool for generating complex test stimuli. The UVM Sequence
Viewer provides a unified view into the sequence activity of a testbench. The UVM Sequence
Viewer can help you understand the relationship between sequencer components, the
sequences running on them, including sequence items, as well as the hierarchical nature of
the sequences.
You can use the Sequence Viewer to navigate the sequence hierarchy from the top down and
analyze the activity of all sequences in the test. If you have identified a sequence item that is
generating incorrect stimuli, you can send it to the Sequence Viewer and debug the sequence
hierarchy from the bottom up.
You can also send sequences to the Waveform window and Stripe Chart Vewer, where you
can view them as transactions, as follows:
In the Waveform window, sequence transactions show what data was generated over
simulation time. The Waveform window is perhaps best for analyzing transactions in
relation to signal transitions as they occur over time.
In the Transaction Stripe Chart Viewer, sequence transactions are shown as a list of
stripes or as rows in a table. The Stripe Chart Viewer is perhaps best for analyzing
transaction attributes and their values, and the relationship of transactions to each other.
Note: In this release, the UVM Sequence Viewer supports only SystemVerilog.
For More Information:
Opening the UVM Sequence Viewer on page 44
Using the Navigation Area on page 47
Using the Sequence Hierarchy Area on page 50
Using the Sequence Data and Methods Area on page 51
Viewing a Sequence Class Definition in the Source Browser on page 53
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See Also
Viewing Transactions in the Waveform Window in Using the Waveform Window
Analyzing Transactions in the Stripe Chart Viewer in Using the Stripe Chart Viewer
Opening the UVM Sequence Viewer

To open the UVM Sequence Viewer for top-down debugging:
Click UVM tools,

, in the UVM toolbar and choose UVM Sequence Viewer, or
choose UVM UVM Sequence Viewer, or Windows New UVM Sequence
Viewer from the menu bar of any SimVision window.
When you open the Sequence Viewer in this way, the Sequence Viewer displays the
sequencer hierarchy in the navigation area on the left side of the window, as shown in
Figure 3-1 on page 45. The sequence hierarchy is a subset of the design hierarchy displayed
in the Design Browser. That is, it contains only the portion of the hierarchy that contains
sequences. You can navigate through the hierarchy to find the sequence and sequence items
you are interested in debugging.
When you select a sequencer in the navigation area, its sequences are displayed in the
Squence Hierarchy. When you select a sequence, its data and methods are displayed in the
Sequence Data and Methods area.
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Debugging UVM
Figure 3-1 Opening the Sequence Viewer

Navigation area
Sequence hierarchy area
Sequence data and methods area
If you know which sequence item is causing a problem, you can send it directly to the
Sequence Viewer from any SimVision window.
To open the Sequence Viewer at a selected sequence item for bottom-up debugging:
From any SimVision window, right-click the sequence item and choose Send to
Sequence Viewer from the pop-up menu, or choose Windows Send to Sequence
Viewer from the menu bar.
When you open the Sequence Viewer in this way, it displays information about the selected
sequence, as shown in Figure 3-2 on page 46.
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Figure 3-2 Opening the Sequence Viewer to a Selected Sequence Item
Tip
Like other multiple view windows in SimVision , such as the Design Browser and
Source Browser, more than one UVM Register Viewer window can be opened at the
same time. When you have multiple Register Viewer windows, only one is the target.
The target window is the one to which any operation is applied. For example, if you
select objects in one window, you can add those objects to the target window.
By default, all sequences are displayed, regardless of whether they are in the finished state.
To display only finished sequences:
Enable View Display Finished Sequences, or right-click over the Sequence Hierarchy
and enable Display Finished Sequences from the pop-up menu. The Sequence Viewer
hides sequences that are not in the finished state.
By default, sequence items are displayed in the window.

To hide sequence items:
Disable View Display Sequence Items, or right-click over the Sequence Hierarchy and
disable Display Sequence Items from the pop-up menu.
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Debugging UVM
By default, UVM sequencer base classes are not displayed in the window.
To show or hide UVM sequencer base classes:
Choose Edit Preferences and enable or disable Display UVM base classes from the
Class Debug tab of the Preferences window, or enable or disable UVM Display UVM
Base Classes in the UVM toolbar.
Using the Navigation Area on page 47
Using the Sequence Hierarchy Area on page 50
Using the Sequence Data and Methods Area on page 51
See Also
Managing Windows in Introduction to SimVision
Using the Navigation Area

The Navigation area is divided into two tabbed areas for navigating the sequence hierarchy:
Sequencers tabDisplays the UVM sequencers in the UVM component hierarchy
Sequence Types tabDisplays a list of all sequence types defined in the design
For each sequencer or sequence type, the Sequence Viewer displays the name of the
sequencer and the number of sequences and sequence items currently in flight on the
selected sequencer.
When you select a sequencer or sequence type, information about its sequences are
displayed in the Sequence Hiearchy area. Only one sequencer can be selected at a time.
When you hover the cursor over a sequencer or sequence type, a tooltip shows the following
information:
The full SystemVerilog logical path
The SystemVerilog physical class object of the sequencer
The arbitration mode of the sequencer
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Debugging UVM
The Sequencers Tab on page 48
The Sequence Types Tab on page 49
The Sequencers Tab

The Sequencers tab displays sequencers in the context of the overall component hierarchy,
as shown in Figure 3-3 on page 48. The Sequencer Hierarchy column shows that portion of
the component hierarchy that contains UVM sequencers. The rest of the component
hierarchy is omitted. The hierarchy starts at the UVM test top, so that you can focus only on
the UVM component hierarchy that is relevant to the sequencers.
Figure 3-3 The Sequencers Tab
To expand and collapse the sequencer hierarchy:
Click the + button to the left of the sequencer name, or right-click and choose Expand All
from the pop-up menu. The + changes to a - button.
Click the - button to collapse the sequencer, or right-click and choose Collapse All. The
- changes to a + button.
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Debugging UVM
If you have a large hierarchy, you can use the Find field to locate a specific sequencer or
sequencers.
To search for a sequencer:
Enter a glob-style string pattern in the Find field, then click Search Down,
Up,
, to find the sequencers whose names match the specified string.
, or Search
See Also
The Sequence Types Tab

The Sequence Types tab lists sequence types in table format, as shown in Figure 3-4 on
page 49. Initially, the sequence types are ordered alphabetically by name, but you can sort
them in reverse order or by their object count.
Figure 3-4 The Sequence Types Tab
To reverse the sorting order:
Click the Name header to reverse the sorting order.
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Debugging UVM
To sort the sequence types by count:
Click the Count header once to sort by count in ascending order. Click again to reverse
the order.
Because a design might contain hundreds of sequence types, the Sequence Viewer lets you
filter sequence types by name, by UVM sequence type, or by count.
To filter by name:
Enter a glob-style string pattern in the Filter field. If you specify more than one pattern,
they are ORedsequence types that match any of the patterns are displayed.
To show or hide UVM base class sequence types:
Enable or disable Show/Hide UVM sequence types,
To show or hide sequence types with no instantiated class objects:
Enable or disable Show/hide classes with no instantiated objects,
See Also
Using the Sequence Hierarchy Area

When you select a sequence in the navigation area, the Sequence Viewer displays its
associated sequences in the Sequence Hierarchy, shown in Figure 3-5 on page 50. The
sequences are displayed in a tree view, corresponding to the calling hierarchy of the
sequences. That is, subsequences are indented below their parent sequences, and lines
connect squences to their subsequences.
Figure 3-5 Sequence Hierarchy
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Debugging UVM
For each sequence, the Sequence Hierarchy displays the following information:
The Name column displays the name of the sequence, preceded by an icon to indicate
its type, as follows:
Root sequence
Sub-sequence
Sequence item
The Object column displays the instance name and handle of the sequence.
The Begin and End columns show the start and end time of the sequences. If the start
or end time of a sequence are not available, a dash (-) is displayed.
The State column shows the state of the sequence, such as FINISHED when the
sequence is finished, or BODY when it has stopped in mid-flight. The column is blank
when the sequence has no state.
To expand and collapse the hierarchy, and see subsequences and sequence items:
Click the + button to the left of the sequence name, or right-click and choose Expand All
from the pop-up menu. The + changes to a - button.
Click the - button to collapse the sequence, or right-click and choose Collapse All. The changes to a + button.
As you navigate through the sequence hierarchy, you can lose track of the relationship
between a subsequence and its parent, or the subsequence and the root sequence. The
Sequence Viewer provides toolbar buttons to jump to these locations in the hierarchy.
To jump to a subsequences parent sequence:
Select the sequence and click Jump to parent,

Parent Sequence.
, or right-click and choose Go To
To jump to the root sequence:
Select the sequence and click Jump to root,

Sequence.
, or right-click and choose Go To Root
Using the Sequence Data and Methods Area

When you select a sequence in the Sequence Hierarchy, the Sequence Data and Methods
area displays information about the data items and methods in that sequence, as shown in
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Figure 3-6 The Sequence Data and Methods Area
For each data item, the Sequence Viewer displays the following information:
The Name column shows the class handle, variable, or class object.
The Value column shows the class instance handle or the value of each data member
or array element at the current simulation time.
The Size column shows the size of queues and arrays; otherwise, it is blank.
The Type column shows the class object type, such as logic, string, or int.
All values in the Sequence Hierarchy are based on the current simulation time, and they are
displayed in the radix in which they were recorded.
To change the simulation time:
Enter a new time in the Time toolbar, or move the primary cursor in the Waveform
window.
To change the radix:
Choose a radix from the Format Radix menu.
Setting Breakpoints
You can set breakpoints on sequences and sequence items and methods.
To set a breakpoint on a sequence:
Select the sequence in the Sequence Hierarchy, then right click and choose Break on
body() method or Break on state change.
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Note: These breakpoint menus are not displayed if they are not relevant to the selected
sequence.
To set a breakpoing on a sequence item or method:
Select the item or method from the Sequence Data and Methods area, then right-click
and choose Break on change.
Sequence-related breakpoints are added to the Simulation Breakpoints area of the

Properties window. Like other breakpoints that you set in SimVision, they breakpoints can be
viewed, disabled, or deleted from the breakpoints section of the Properties window..
See Also
Viewing a Sequence Class Definition in the Source

Browser
While looking at the sequences in the Sequence Hierarchy, you might want to see its class
definition.
You can jump to the sequence class definition in the Source Browser in any of the following
ways:
Double-click the sequence in the Sequence Hierarchy.
Drag and drop the sequencer, sequence, or sequence item into the Source Browser
window.
Right-click the sequence in the Sequence Hierarchy and choose Set Debug Scope
from the pop-up menu.
The Source Browser opens the source code containing the sequence definition, and sets the
blue arrow to the appropriate line in the source code.
See Also
Accessing the Design Source Code in Using the Source Browser
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Sending a Sequence to the Waveform Window

To send a sequence to the Waveform window:
Select the sequence in the Sequence Hierarchy, thend right-click and choose Send to
Waveform.
Sequences are displayed as transactions in the Waveform window, as shown in Figure on

page 54.
Figure 3-7 Sequence Transaction in the Waveform Window
See Also
Viewing Transactions in the Waveform Window
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Debugging UVM

Product Version 13.2

20002014 Cadence Design Systems, Inc. All rights reserved.

Starting a UVM Debugging Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Opening the UVM Sequence Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Product Version 13.2

Using the Navigation Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Product Version 13.2

Built-in window layout for UVM debugging

Class Debug Preferences to show or hide UVM base classes

Design Browser Preference to show or hide the UVM hierarchy

For More Information

Starting a UVM Debugging Session on page 2

Probing UVM Objects to the Simulation Database on page 5

Using the UVM SystemVerilog Debugging Layout on page 7

Using the UVM Toolbar and Menu on page 10

Viewing UVM Class Objects in the Class Browser Sidebar on page 25

Product Version 13.2

Viewing UVM Objects in the Waveform Window on page 27

Using Windows Designed for SystemVerilog UVM on page 28

Getting Help on page 29

SimVision UVM Tcl Debug Commands

SimVision UVM Toolbar and Message Links

SimVision UVM Register Viewer

All SimVision Videos

Starting a UVM Debugging Session

-linedebug allows you to set breakpoints on lines in the source code.

-gui starts SimVision as the debugging environment.

Product Version 13.2

Product Version 13.2

Figure 1-1 Starting SimVision with the ubus Test Environment

UVM Command-Line Options in the irun User Guide

Customizing the Layout of SimVision Windows in Introduction to SimVision

Product Version 13.2

Invoking SimVision in Running SimVision

Using the Console Window in Introduction to SimVision

Probing UVM Objects to the Simulation Database

Issue a probe command in the simulator tab of the Console window.

Product Version 13.2

Figure 1-2 Opening the Probe Form

Product Version 13.2

Figure 1-3 Selecting Objects to be Probed

Enable Include UVM base classes in the SimVision Probe form.

Specify the -uvm option on the probe command.

probe in the Incisive Simulator Tcl Command Reference

Creating and Managing Probes in Running SimVision

Using the UVM SystemVerilog Debugging Layout

Product Version 13.2

Figure 1-4 The UVM SystemVerilog Debugging Layout

UVM Sequence Viewer

UVM Register Viewer

Source BrowserDisplays the source code for designs and instances

Product Version 13.2

Waveform windowLets you view simulation data along X and Y axes

Sequence ViewerProvides a unified view of the sequence activity of a testbench

To switch to the layout after startup:

Choose Windows Layout UVM SystemVerilog Debugging from any SimVision

To set the layout as your default window layout:

Product Version 13.2

Figure 1-5 Choosing the UVM Debugging Layout

Customizing the Layout of SimVision Windows

Using the UVM Toolbar and Menu