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Interview questions in Verilog with Answers:

1. What are the two different design methodologies?

The first one is the top-down design methodology and the other one is the bottom
down design methodology. In the top-down design method, we first define the top
blocks and then identify the sub-blocks required to build the top block. The subblocks are further divided into until we come to the leaf cells, which cannot be
divided any further. In the bottom up design method, it is the other way round
starting from the smallest level to the top-level block. Typically, a mixture of both
these methods is being followed in the industry today.

Define a module?
A module is the basic building block of Verilog. It can be an element or a
collection of lower level design blocks. Elements are grouped into a module to
provide common functionality that will be used in various places in the design

3. What are the different levels of abstraction?

The internals of each module in Verilog can be described in four different levels
of abstraction. Independent of the levels of these abstractions, the module behaves
in the same way to the environment. The internals of the module are hidden from
the environment
The first level of abstraction is the Behavioral or the algorithmic level. Here the
module is implemented in terms of the desired design algorithms independent of
the hardware implementation details
The second level of abstraction is the data flow level. Here the module is
designed by specifying the flow of data
Next level of abstraction is the gate level modeling. Here the module is described
in terms of the logic gates and interconnections between them
The last level of abstraction is the switch level. Here the internals of the module
are designed in terms of switches, storage nodes and interconnections between
The higher (first) the level of abstraction, the more flexible and technology
independent is the design. If the switch level of abstraction is being used, then it
very much technology dependent. Thus, a small change in the design will cause a
significant change in the design.
In general, a combination of the behavioral level and the dataflow constructs are
being used today and this is called as register transfer level design or the RTL
4. What is instantiation and instances?
The process of creating objects from a module is called as instantiation and this
created object is called as instances

5. What is a stimulus block/ test bench?

Once the design block is completed, the functionality of such a block is tested and
checked by applying stimulus to the block. Such a block is called as the stimulus
block or a test bench.
6. What is the difference between wire and a reg data type?
A wire represents structural interconnections between various components and a
register represents variable, which are being used to store data. The net and
register are the two different data types in Verilog and wire is a net.
7. What is the difference between === and ==?
Both of these are equality operators. == Checks for equality of zero and one and
the result is unknown if an x or z is present. === is the case equality function and
this checks for equality of the two variables including x and z.
8. What is the difference between casex and case statements?
Both these statements are multibranching statements and the difference is that
casex treats x and z as dont care in the case item and in the case expression.
Casez treats all the z values as dont cares in the case and in the case expression
but the case statement does not do either of the two.
9. What is the difference between unary operator and logical operator?
All logical operators require two operands to perform their function and in the
other hand unary operators require only operand to perform their function.
10. What is the function of the statement parameter?
Parameters are commands which are used in Verilog to define particular
constants. Parameters cannot be used as variables and parameters for each module
can be overridden individually at compile time.
11. Why is defparam used?
They are used in a module to override the parameters values. The new parameter
value will be decided by the defparam command
12. What is the difference between $ monitor and $display statements?
Both of these are essentially system tasks. System tasks are commands used in
Verilog which begin with the sign $. $display is used to display the values of
variables or nets or whatever is present in the parameter list. Suppose the values
of the variables inside the display command changes then a new $display
command has to be invoked to display the new value. The $monitor requires to be
invoked only once and it displays all the variables and signals in the parameter list
even when one of them inside the parameter list changes.

13. What is the difference between $stop and $finish statements?

These two commands are also essentially system tasks as they begin with the $
sign. The $stop command will stop/pause* the simulation at that point and go into
an interactive mode. This command is used whenever the designer wants to
suspend the simulation and examine the values. The $finish command on the
other hand will completely terminate the simulation.
14. What are keywords and identifiers?
Keywords are basically special identifiers which are used to define the language
constructs and all the keywords are used in lower case letters as Verilog
differentiates between lower case and upper case letters.
Identifiers on the other hand are names that are given to objects such as to
registers, functions, modules etc. so that they can be referenced in design.
Identifiers are case sensitive. The identifiers cannot start with a digit or a dollar
sign. The dollar sign is reserved for system tasks.
15. What are escaped identifiers?
They are a class of identifiers which begin with the backslash and end with the
white spaces. White spaces include the new line, tab and the space. All characters
between the backslash and the white spaces are processed
16. What are strings?*
These are essentially a sequence of characters, which are enclosed in double


**What are the two compiler directives?**

Include and define are the two complier directives in Verilog. The define directive
is used to define text macros in Verilog and the include directive is used to
include a entire Verilog source file into another during compilation
18. What are ports and what are the different types of ports?
Ports essentially provide the interface by which the modules can communicate
with the environment. They are also called as terminals. The different types of
ports are the input ports, output ports and the inout ports.
19. What is turn off delay?
The turn off delay is associated with gate level modeling and is the delay
associated with a gate output transition to the high impedance value from another
20. What are the key features of behavioral modeling?
The key features with behavioral modeling are that they must start with an initial
or an always statement. The statements begin and end can be used along with the
initial statements to group various blocks. They are equivalent to the {} in C

21. Differentiate between Inter assignment Delay and Inertial Delay and intra
assignment delay?
The inter assignment delay is the type of delay used in behavioral modeling and it
is called as regular delay control. It waits for the appropriate amount of time steps
before executing the command. The inertial delay is encountered in data flow
modeling and it is the property where if the period of the input pulse is shorter
than the delay in the continuous assignment statement, the input is not propagated
to the output. The intra assignment delay is also used in behavioral modeling and
here the value of the expression on the right hand is evaluated first and after the
specified time delay it is assigned to the left hand side variable from a temp
22. What is the difference between the following lines of code?
reg1<= #10 reg2;
reg3 = # 10 reg4;
The first statement is non-blocking statement and the second statement is block
23. What are the differences between blocking and non-blocking statements?
The blocking statements use the operator = and the whole statement is completely
executed before the control passes on to the next statement. Non blocking
statements on the other hand use<= as the operator and for such statements, the
right hand side of the expression is evaluated and assigned to the left hand side
after the specified time interval. Non-blocking statements can be used
effectively to model concurrent data flow transfers like in shift registers because
the result is not dependent on the order of data flow and they can avoid the race
conditions, which are possible, if blocking statements are used.
Both these statements are used in behavioral modeling and are the basic
procedural assignments statements
24. What is the difference between procedural assignment statements and
continuous assignment statements?
The first difference between the two is that procedural statements are used in
behavioral modeling and continuous statements are used in data flow modeling.
In addition, in procedural statements the value placed on the variable will remain
unchanged unless another procedural statement updates the variable with a
different value. In the continuous one, the value of the right hand side expression
would be placed continuously on the left side net.
25. Explain the different types of continuous statements?*
There are three different types of continuous statements:
Regular continuous assignment
Wire out;

Assign #10 out= in1 & in2;

Implicit continuous assignment
Wire #10 out= in1 & in2;
Implicit net assignment
Wire #10;
Assign out= in1 & in2;

26. What is the difference between inertial delay and transport delay?
Inertial delay models are simulation models that filter the pulses, which are
shorter than the propagation delay of Verilog gate primitive or the continuous
assignment. They swallow all the glitches. Verilog simulates inertial delay by
Transport delay models on the other hand are simulation models that pass all the
pulses, including pulses, which are shorter than the propagation delay of the
corresponding Verilog statement. They pass glitches, delayed in time. Transport
delay models can be modeled in Verilog by adding explicit delay values to the
RHS of the non-blocking assignment.
27. Why is it called as blocking statements?
It is called as blocking assignment because, once a blocking assignment is
encountered, it will first execute that step and then only proceed to the next step.
In the sense, it blocks the execution of other steps unless this step is finished
28. Why is it called as non-blocking statements?
A non-blocking statement does not block other assignments from being executed
between the evaluate and the update steps of a non-blocking assignment
29. What are the various multiway branching statements in Verilog?
The different multiway statements in Verilog are case, casex, casez.
30. What are the various loop commands in Verilog?*
The various loop commands in Verilog include for, repeat, forever, while.
31. What is the difference between sequential and parallel blocks??? **
The keywords begin and end are used to group statements into a sequential block
and these blocks are processed in the order in which they are mentioned. A
statement is executed only after its preceding statement is finished execution. If a
delay is specified then it is relative to the time when the previous statement
finished execution.
Parallel blocks on the other hand start with keyword fork and join, all statements
inside a parallel block are executed concurrently, and if a delay is mentioned then
that delay is relative to the time, the block was entered.
32. What are the various key features of blocks?

There are three special features of the blocks, which are nested blocks, named
blocks and disabling of named blocks. In nesting of blocks essentially, they can
be mixed. Both sequential and parallel blocks can be mixed with each other.
These blocks can be given a name also, it will become a named block, and if we
have to disable such a named block, we can use the disable block command to do
33. What is the benefit of using Behavior modeling style over RTL modeling?
The advantage of Behavioral modeling is that it is written with higher level of
abstraction and the simulation speed is faster.
34. How do you implement the bi-directional ports in Verilog HDL?
Bi-directional ports in Verilog are implemented using the inout statements.
35. What is the difference between Behavior modeling and RTL modeling?
Behavioral modeling is used to check the functionality of the circuit and RTL
modeling is used to describe the real circuit.

Behavioral Models : Higher level of modeling where behavior of logic is

RTL Models : Logic is modeled at register level
Structural Models : Logic is modeled at both register level and gate level.
36. What is the difference between a Verilog task and function?
A function will return a single value and a task will not return any value. A
function will also execute itself in one simulation time unit and a task can contain
time controlling statements. A function cannot enable task, but task can enable a
function or other tasks.



A Verilog HDL function is the same as a task, with very little differences, lik
cannot drive more than one output, can not contain delays.

functions are defined in the module in which they are used. It is possible
functions in separate files and use compile directive 'include to in
function in the file which instantiates the task.
functions can not include timing delays, like posedge, negedge, # de
means that functions should be executed in "zero" time delay.
functions can have any number of inputs but only one output.
The variables declared within the function are local to that function. Th
declaration within the function defines how the variables passed to th
by the caller are used.
functions can take, drive, and source global variables, when no local var
used. When local variables are used, basically output is assigned o
end of function execution.
functions can be used for modeling combinational logic.
functions can call other functions, but can not call tasks.

37. Given the following Verilog code, what value of "a" is displayed?
Always @(clk) begin
a = 0;
a <= 1;

38. Given the following snippet of Verilog code, draw out the waveforms for
"clk" and "a".
Always @(clk) begin
a = 0;
#5 a = 1;
39. What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;
40. What is the difference between:
c = foo ? a: b;
if (foo) c = a;
else c = b;
41. How can you swap 2 integers a and b, without using a 3rd variable?
The two integers can be swapped using Verilog non-blocking assignments. This
does not require the use of a third variable. If we use blocking assignments
statements then we would require the use of a third variable.
42. Which one is preferred in design entry? RTL coding or Schematic? Why?**
43. Explain the Verilog race condition?
A Verilog race condition is said to occur when two or more simulation steps that
are schedules to occur in the same simulation time would give rise to different
combination of values if the order of the steps were interchanged.
44. Mention some the guidelines used for coding in Verilog?
Use blocking assignment for expressing combinational logic and use nonblocking assignment to express sequential logic. We should not use both the types
of statements in the same block.

Key points to have in mind while writing doing RTL coding for a finite state
1. There are three different ways of coding in RTL. One always block, two always
block and the three always block. The two always block and the three always
block are the preferred style of coding.
2. After obtaining the state transition diagram, first assign the values to each of the
states. This can be done in binary encoding or one-hot encoding.

In one-hot encoding the number of bits used is equal to the number of states of
the FSM, with only of the bits being one for each state representation. In binary
encoding the number of flip-flops required is the logarithmic value of the
number of states to the base two.

4. These assignments to the states can be made either using the parameter command
or using the compiler directive command, define. The parameter is the command,
which is preferred because, declaring the state assignments using parameters
creates local definitions and hence the same name of the state can be used for a
different Verilog module where a separate parameter statement would make
different assignments to the states.
5. In general, FPGA vendors always recommend the use of one-hot encoding style
because flip-flops are plentiful in an FPGA and the combinational circuits
required in one-hot encoding is less that that required in binary encoding. As these
combinational circuit elements size determine the performance of these FPGA,
the one-hot encoding is preferred.
6. Some of the main goals of FSM coding are that the coding style should be easy to
code and understand, should be compact, should facilitate easy debugging and
should yield efficient synthesis results.
7. There are essentially two main blocks in the two always and the three always
coding style of a FSM. They are the combinational always block and the
sequential always block.
8. In the sequential always block, we always use non-blocking assignment
statements and are used to code clocked or sequential logic. The sensitivity list of
a sequential block is an edge based sensitivity list.
9. The two main reasons why we prefer to use non-blocking statements with intra
assignment delays is that it gives the appearance of the clk-q delay in the
waveform viewer and it helps avoid hold time problems.

10. The next type of always block is the combinational always block. This block used
blocking statements and is used to update the next state value. The sensitivity list
of these combinational blocks is not edge based.
11. In the combinational always block, the value of next state is set to a default value.
This is essentially a coding trick and is useful in debugging. If a next state
assignment has not been made inside the combinational always block then the
outputs during simulation will go to default value X at that particular point during
simulation and hence can be carefully debugged
12. Suppose we use a two always block method for coding a FSM, then we would
have one combinational always blocks, which will be used for assigning the
states, and the value of the output registers. The sequential always block would be
used for checking the asynchronous logic at the beginning.
13. Suppose we use a three always block method of coding a FSM, then we will first
have the sequential always block for the asynchronous logic and then the
combinational always block for making the state assignments and then one more
sequential logic for making the output assignment
14. Suppose we want to use an output-encoded style of coding, then a SAB followed
by a CAB and then we would have a continuous assignment statement for the
15. In General, if we have to implement a state machine design having two separate
constraints, the we can create two state machine design for each of them and then
combine the output of the state machines to get the desired output.

Codes for various circuits

1) 2-1 mutliplexer using gate level modeling.
2) 2-1 mutliplexer using behavioral modeling- using if statement and using case
3) 2-1 mutliplexer using data flow modeling
4) 4-1 mutliplexer using gate level modeling
5) 4-1 mutliplexer using data flow modeling
6) 4-1 mutliplexer using behavioral modeling-using if statement
7) Positive/Negative D latch
8) Asyncronous/Syncronous D and T flip flops
9) Encoders/decoders

Gate level modeling for mux2:

module mux2(out,i0,i1,s0);
output out;
input i0,i1,s0;
//internal wires
wire sbar,y1,y2;
not g1(sbar,s0);
and g2(y1,i0,sbar);
and g3(y2,i1,s0);
or g4(out,y1,y2);
Data Flow :
Behavioral :
If or case statements
Case sel
0: q<=a;
1: q<=b;

A Dataflow MUX Parameterized Width

module mux21n(q, sel, a, b);
parameter WID = 16;
input sel;
input[WID-1:0] a, b;
output[WID-1:0] q;
assign q = sel ? b : a;
By default, this is now a 16-bit wide MUX.
When instantiating, the default value of 16 can be overridden:

mux21n M1(q, sel, a, b);

// Instance a 16-bit version mux21n #(4)
M0(q, sel, a, b); // Instance a 4-bit version

Race conditions :
The order of execution isn't always guaranteed within Verilog. This can best
be illustrated by a classic example. Consider the code snippet below:


What will be printed out for the values of a and b? Depending on the order
of execution of the initial blocks, it could be zero and zero, or alternately
zero and some other arbitrary uninitialized value. The $display statement
will always execute after both assignment blocks have completed, due to
the #1 delay.


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