Logic Design I

EEL 3712 U01

Fall 2013

Lecture 6

Product-of-Sums Simplification
K-map has been used to simplify Boolean functions in
sum-of-product form.
The result can be converted to product-of-sums form by
using De Morgans Law using the following procedures:

Simplifying F function using K-map

Find F from F using De Morgans law
F is in sum-of-products form and F is in product-ofsums form.

Example: Product-of-Sums Function

Simplifying : F ( A, B, C, D) (0,1,2,5,8,9,10) into productof-sums form
F ' (3,4,6,7,11,12,13,14,15)
F ' AB CD BD '
F ( A' B' )(C ' D' )( B' D)

If using direct K-map

optimization
F B' D' B' C' A' C' D

Example 2
Boolean function based on truth table:

F ( x, y, z ) (1,3,4,6)

F ( x, y, z ) (0,2,5,7)
K-map simplification:

F x' z xz'
F ' xz x' z '
F ( x' z ' )( x z )

Dont-Care Conditions
In most cases, the values of Boolean functions are defined
as either 1 or 0.
For some applications, the Boolean functions are
undefined or unknown for some minterms.

Undefined minterms of a Boolean function are called

dont-care conditions
In K-maps, the minterms with dont-care conditions are
represented with x. They can be interpreted as either 0
or 1 in function simplification.
The values of the minterms with dont-care conditions are
selected to generated the simplest Boolean function.

Example: Dont-Care Conditions

Boolean function: F (w, x, y, z) (1,3,7,11,15) with
dont-care conditions: d (w, x, y, z) (0,2,5)

Gate-Level Implementations
Based on sum-of-products form: F B' D'B' C' A' C' D

Two-level AND-OR form

Based on product-of-sums form: F ( A' B' )(C ' D' )( B' D)

Two-level OR-AND form

Tree Diagrams of Logic Gate Implementation

Each node on a tree diagram

represents a gate, and the
number of gate inputs is
written beside each node.

Four-Level Realization of Z

NAND and NOR Gates

NAND and NOR gates are more commonly used for logic
implementations than AND and OR gates.
Any digital systems can be implemented with NAND
gates (Inverters can be considered as the NAND gates
with one input)

AND-Invert and Invert-OR gates

NAND can be represented as the following two forms:
AND-Invert form:

Invert-OR form (using DeMorgans Law):

Two-Level NAND Implementations

The Boolean function in the form of sum-of-products can
be implemented with two-level NAND gates
F AB CD (( AB)' (CD)' )'

Example
Implement the following Boolean function with NAND
gates: F ( x, y, z) (1,2,3,4,5,7)

Step 1. Simply the Boolean function using K-map

Step 2. Implement the final result (sum-of-products form)
using AND and OR gates,
Step 3. Convert all AND-OR gates to NAND gates.

Multilevel NAND Circuits

Used when Boolean functions in multilevel format:
F A(CD B) BC '
Step 1: Directly implement logic using AND,OR gates.

Step 2: Convert AND/OR gates to NAND gates with

AND-invert (Invert-OR) symbols.

Example: Multilevel NAND Logic

Boolean function: F ( AB' A' B)(C D' )
Direct implementation using AND-OR gates:

Convert AND/OR gates to NAND gates:

NOR Gates
Any logic circuits can be implemented with NOR gates
and Inverters.

Two forms (graphic symbols) of NOR gates

Examples: NOR Gates

Implementing: F ( A B)(C D) E

Implementing: F ( AB' A' B)(C D' )

AND-NOR Logic Implementation

NAND-AND and AND-NOR are equivalent logic forms

Convenient for implementing sum-of-products Boolean

equations.
Example: F ( AB CD E )'

OR-NAND Logic Implementation

OR-NAND and NOR-OR are the same logic forms of
two-level implementation.
Convenient for implementing product-of-sums Boolean
equations.

Example: F [( A B)(C D) E ]'

Example
Implement the following Boolean function with two-level
forms of (AND-NOR, NAND-AND, OR-NAND, NOROR) F ( x, y, z) (1,6)
Simplification using K-map:

F ' x' y xy' z F ( x' y xy' z )'

F x' y ' z ' xyz' F ( F ' )' [( x y z )( x' y ' z )]'

Two-level Implementations
Different forms of two-level implementations:

Exclusive-OR (XOR) Function

XOR, denoted by , performs the following Boolean
function: x y xy' x' y
If x y, x y 1
If x y, x y 0

Some identities for XOR operations:

x0 x
x 1 x'

x y ' x' y ( x y )' xy x' y '

x x 0

A B B A

x x' 1

( A B) C A ( B C ) A B C

XOR Gate Implementation

Using AND-OR gates:

Using NAND gates:

Odd Function
Boolean function of a three-variable odd function:
F ( A, B, C ) AB' C ' A' BC ' ABC A' B' C
(1,2,4,7)

K-map:

Three-Variable Odd Function

Representation using XOR gates:
F ( A, B, C ) AB' C ' A' BC ' ABC A' B' C
( AB' A' B)C '( AB A' B' )C
( A B)C '( A B)' C ( A B) C
A B C

Implementation using XOR gates:

Three-Variable Even Function

3-variable even function: F ( A, B, C ) ( A B C )'
K-map:

Implementation:

Four-Variable Odd & Even Functions

4-variable odd function: F ( A, B, C , D) A B C D
4-variable even function: F ( A, B, C , D) ( A B C D)'
K-maps:

Parity Checking
Parity bit: additional bit generated with binary data to
make the number of 1s either odd or even prior to the
transmission.
Parity checking: checking the parity (number of 1s) at the
receiver.
Even-Parity generator: generating one parity bit to make
the total number of 1s even before transmission.
3-bit even-parity generator (truth table & circuit):

Parity Checker
Parity Checker at receiver: If there is a transmission (one
bit) error, the output is 1; otherwise, the output is zero.
3-bit parity checker: C x y z P