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D-Type flip-flop (Toggle switch)

The D-type flip-flops are used in prescalar/divider circuits and frequency phase detectors.
Figure 1 shows how the flip-flop (latch) can be made using 2-input logic circuits and Figure 2
shows the input and output waveforms

The enable pin needs to be high for data to be fed to the outputs Q and Q bar.

The output will only change on the falling edge or trailing edge of the applied clk input.

NAND
NAND Q
Enable

NAND Q
NAND
NOT

Latch

Figure 1 Simple D-type Flip-flop circuit

The D type flip-flop has only one input (D for Data) apart from the clock.
The INDETERMINATE state is avoided with this flip-flop.
When the clock goes high, D (a 0 or a 1) is transferred to Q.
When the clock goes low, Q remains unchanged.
Q stores the data until the clock goes high again, when new data may be available.

Figure 2 Output waveforms of the D-type flip-flop. In this circuit the Q output changes
state on the leading edge of the clock.
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At A, clock and data are high.

Q goes high and stays high until B.

At B, clock is high and data is low.

Q goes low and stays low until C.

At C, clock and data are both high.

Q goes high and stays high until E.
Q does not change during clock pulse D, because clock and data are still both high.

At E, data is low, so Q goes low.

At F, data is high so Q goes high.

As with the other flip-flop circuits the operation can be improved to eliminate indeterminate
states by adding a master latch. The circuit of the master-slave D-type flip-flop is shown in the
ADS simulation setup shown in Figure 3.

The inverter connected between the two CLK inputs ensures that the two sections will be
enabled during opposite half-cycles of the clock signal.

Each logic gate is made up of CMOS FETS (based on the 0.8um process) as described in the
other tutorials on individual gates.
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VtPulseDT VtPulseDT V
V_DC
SRC4 SRC2
SRC1
Vlow=0 V Vlow=0 V
DT DT Vdc=5.0 V
Vhigh=5 V Vhigh=5 V
Delay=25 usec Delay=0 nsec
D Width=50 usec Clk Width=10 usec
Period=100 usec Period=20 usec
Rout=1 Ohm Rout=1 Ohm

V
V Vcc V
Vcc V A
Vcc
D A
Vcc NAND OUT A

B
NAND
buffered
OUT A
OUT
B buffered

B
NAND
buffered
OUT
Q
NAND

Port B buffered

NAND_buffered
NAND_buffered NAND_buffered Port
D X2
X8 NAND_buffered X4 Q
Num=1
X7 Num=3
V
V V Vcc
V Vcc Vcc
A

A
Vcc
A
OUT
A
OUT B
NAND OUT
Q_bar
NAND NAND buffered

NAND OUT B buffered B buffered

Clk B buffered

NAND_buffered Port
NAND_buffered NAND_buffered Q_bar
NAND_buffered X5
Port X6 X3 Num=4
Clk X9
Vcc
V
Num=1 TRANSIENT
IN OUT
NOT

Tran
NOT Tran1
X10 StopTime=150 usec
MaxTimeStep=250

Figure 3 ADS simulation setup of the master-slave D-type flip-flop circuit. In this simaulation there are two square wave generators, the clock at
50KHz and the data (with a 25us delay) running at 10KHz. The simulation is a time-domain transient.
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The resulting simulation of the circuit shown in Figure 3 is shown in Figure 4.

D-type Flip-flop transitions occur on the falling

of the Clk input
6

4
Clk 3
,V
2

-1
0 20 40 60 80 100 120 140 160

time, usec
6
5

4
D, 3
V
2

1
0

-1
0 20 40 60 80 100 120 140 160

time, usec

Q, 3
V
2

-1
0 20 40 60 80 100 120 140 160

time, usec
Figure 4 Simulation of the Master-slave D-type flip-flop. Note that the transitions occur
on the falling edge of the applied clock signal+1/2 half clock cycle due to the slave
action.
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The D-type flip-flop can be configured as a T-type or Toggle flip-flop. With this configuration
the Q_bar output is connected to the D input and the signal/clock is connected to the clk
input. The output of this flip-flop will have a frequency half that of the input.

The ADS simulation of Figure 6 is shown below (Figure 5)

D-type Flip-flop transitions occur on the falling

of the Clk input. This D-type is configured as
a T-type toggle flip-flop
6

4
Clk 3
,V
2

-1
0 20 40 60 80 100 120 140 160

time, usec
6

Q, 3
V
2

-1
0 20 40 60 80 100 120 140 160

time, usec

Figure 5 Simulation results of the D-type flip-flop configured as a T-type (Toggle) flip-
flop by connecting the D input to the Q_bar output. Such circuits are common in
frequency prescalar circuits.
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V
V Vcc V
A
Vcc V A
OUT A
Vcc
Vcc NAND
OUT A B OUT
B
NAND
NAND OUT
buffered
B
NAND
Q
buffered buffered
B
buffered
NAND_buffered Port
NAND_buffered NAND_buffered
NAND_buffered X2 Q
X8 X4
X7 Num=3
V
V V Vcc

V A
Vcc
A
Vcc
A
OUT
Vcc NAND
A NAND OUT NAND OUT B
buffered
OUT B B
NAND buffered buffered

Clk B
buffered
NAND_buffered
NAND_buffered NAND_buffered VtPulseDT
NAND_buffered X5
Port X6 X3 SRC2
Clk X9 Vlow=0 V
Vcc
V
Num=1 TRANSIENT Vhigh=5 V
V IN
NOT
OUT
Delay=0 nsec
V_DC Tran Width=10 usec
SRC1 Tran1 Period=20 usec
Vdc=5.0 V NOT
X10 StopTime=150 usec DT
Rout=1 Ohm
MaxTimeStep=250 nsec

Clk

Figure 6 Transient ADS simulation of a D-type Flip-Flop configured as a T-type flip-flop by connecting the D input to the Q_bar output.
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RF Application

Phase detectors are part of a Phase Locked Loop (PLL) and can be either analogue eg mixer
or digital eg D-type flip-flop. When a mixer is used the output consists of the sum and
difference frequencies.

In an analogue mixer a number of different frequencies are generated within the mixer namely
the sum of the frequencies and the difference frequency (otherwise known as the beatnote)
when both input frequencies are the same is the phase difference is zero and the beatnote is
DC.

Most PLL circuits now use digital phase detectors formed from two D-type flip-flops as shown
in Figure 7.

Vhigh

D
D type
Flip-Flop Q1 Q1
F1 Clk

Clear NAND
Vhigh

D
D type
Flip-Flop Q2 Q2

F2 Clk

Figure 7 D-type flip-flop application - Phase frequency phase detector