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RRUS 01 2 log

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[2015-01-13 08:04:21.248] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298948 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3661 + DpdDelay:1749
[2015-01-13 08:04:21.252] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30435[ns] = salCarrierReportedDelay:298948 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:21.252] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 08:04:21.332] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 08:04:21.332] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 08:04:21.332] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 08:04:21.352] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 08:04:21.352] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 08:04:21.356] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 08:04:21.356] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 08:04:21.356] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 08:04:21.564] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 08:04:21.564] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 08:04:21.564] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955800
[2015-01-13 08:04:21.564] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.

[2015-01-13 08:04:21.564] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr


lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955840 (result: true)
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7
, txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 08:04:21.568] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955840 (result: true)
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 08:04:21.568] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 08:04:21.568] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955840 (result: true)
[2015-01-13 08:04:21.572] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o

n branch 1 calculated to 4900 (closest actual 4900)


[2015-01-13 08:04:21.572] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 08:04:21.572] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 3
[2015-01-13 08:04:21.572] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 4
[2015-01-13 08:04:21.572] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 08:04:21.572] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 801 event :8
[2015-01-13 08:04:21.576] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 7, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 955800, state: OFF; dev: 6, txFreq: 0, state: O
FF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq:
0, state: OFF;
[2015-01-13 08:04:21.576] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 3, rx: 0
[2015-01-13 08:04:21.576] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:4 carrier
configuration
[2015-01-13 08:04:21.576] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 08:04:21.576] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 08:04:21.580] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 08:04:21.580] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955840 (result: true)
[2015-01-13 08:04:21.648] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 801, event: 8
[2015-01-13 08:04:21.648] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :8
[2015-01-13 08:04:21.648] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 08:04:21.672] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 08:04:21.672] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true

[2015-01-13 08:04:21.672] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte


r 1
[2015-01-13 08:04:21.676] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 08:04:21.676] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :1024
[2015-01-13 08:04:21.680] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
61 [0.1ns]
[2015-01-13 08:04:21.680] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 08:04:21.680] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 08:04:21.680] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298948 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3661 + DpdDelay:1749
[2015-01-13 08:04:21.684] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :128
[2015-01-13 08:04:21.684] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 08:04:21.684] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 08:04:21.684] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
61 [0.1ns]
[2015-01-13 08:04:21.684] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 08:04:21.684] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 08:04:21.684] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
61 [0.1ns]
[2015-01-13 08:04:21.684] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1262), hardDelay:(834)
[2015-01-13 08:04:21.684] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 08:04:21.688] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte


dDelayDl:298948 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3661 + DpdDelay:1749
[2015-01-13 08:04:21.688] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:3)tTrpToArp:30435[ns] = salCarrierReportedDelay:298948 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 08:04:21.688] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 08:04:21.700] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:33, clientId:102
[2015-01-13 08:04:21.724] - fault_manager.cc:1910 INFO:Set event PA_ON_EVENT to
time: 20000[ms], from 0x10097
[2015-01-13 08:04:21.724] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOffEvent
[2015-01-13 08:04:21.724] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 08:04:21.728] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 08:04:21.728] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 08:04:21.728] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 08:04:21.728] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 5, ccData.filterBranch 2, carrierConf.carrierId 798
[2015-01-13 08:04:21.728] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 08:04:21.728] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 5; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 955800, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 955800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800, sta
te: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF; dev:
8, txFreq: 0, state: OFF;
[2015-01-13 08:04:21.728] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 08:04:21.732] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 08:04:21.740] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON

[2015-01-13 08:04:21.816] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq


= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 08:04:21.820] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 08:04:21.820] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:21.820] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 08:04:21.820] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-i[-42.55 -8.00], DpdPma:-i[-i -i], Pmb:-i, TorPmb:-58.23[-i -8.00] d
B)
[2015-01-13 08:04:21.820] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 798 ENABLE ev
ent
[2015-01-13 08:04:21.820] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 798 ENABLE ev
ent
[2015-01-13 08:04:21.820] trDcProc commonCsc.cc:130 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 08:04:21.820] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 798
[2015-01-13 08:04:21.824] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin
g #####: PAR = 750
[2015-01-13 08:04:21.824] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:30, clientId:102
[2015-01-13 08:04:21.828] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 08:04:21.828] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 08:04:21.828] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 7, ccData.filterBranch 3, carrierConf.carrierId 801
[2015-01-13 08:04:21.828] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 08:04:21.912] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 7; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, tx
Freq: 955800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800,
state: INIT; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF;
dev: 8, txFreq: 0, state: OFF;

[2015-01-13 08:04:21.912] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in


put enabled
[2015-01-13 08:04:21.912] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
2 already unblocked.
[2015-01-13 08:04:21.912] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 801 ENABLE ev
ent
[2015-01-13 08:04:21.912] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 801 ENABLE ev
ent
[2015-01-13 08:04:21.912] trDcProc commonCsc.cc:130 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 08:04:21.912] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 801
[2015-01-13 08:04:21.916] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:33, clientId:102
[2015-01-13 08:04:21.920] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 08:04:21.920] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 08:04:21.920] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 792
[2015-01-13 08:04:21.920] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 08:04:21.928] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-33.97[-61.50 -8.00] dB)
[2015-01-13 08:04:21.928] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 1; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, tx
Freq: 955800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800,
state: INIT; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: INIT
; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 08:04:21.928] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:21.928] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
2 already unblocked.
[2015-01-13 08:04:21.928] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
3 already unblocked.
[2015-01-13 08:04:21.932] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 792 ENABLE ev
ent

[2015-01-13 08:04:21.932] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt


rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 792 ENABLE ev
ent
[2015-01-13 08:04:21.932] trDcProc commonCsc.cc:130 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 08:04:21.932] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 792
[2015-01-13 08:04:21.936] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:24, clientId:102
[2015-01-13 08:04:21.944] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 08:04:21.944] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 08:04:21.944] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 3, ccData.filterBranch 1, carrierConf.carrierId 795
[2015-01-13 08:04:21.944] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 08:04:21.944] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 3; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800
, state: INIT; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: INI
T; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 08:04:21.944] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 08:04:21.948] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 08:04:21.948] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
2 already unblocked.
[2015-01-13 08:04:21.948] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
3 already unblocked.
[2015-01-13 08:04:21.948] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 795 ENABLE ev
ent
[2015-01-13 08:04:21.948] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 795 ENABLE ev
ent
[2015-01-13 08:04:21.948] trDcProc commonCsc.cc:130 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 08:04:21.948] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 795

[2015-01-13 08:04:21.952] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin


g #####: GAIN_OFFSET = -2 (gainOffset:0 + gainMargin:-2)
[2015-01-13 08:04:21.952] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:27, clientId:102
[2015-01-13 08:04:21.968] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0x0 pa1Adj 0x4779
[2015-01-13 08:04:22.492] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.092855, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 08:04:22.636] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.47[-61.50 -8.00] dB)
[2015-01-13 08:04:22.636] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 08:04:22.636] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x04340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 08:04:22.636] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 08:04:22.668] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 08:04:22.668] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 54 deg
[2015-01-13 08:04:22.668] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24947
[2015-01-13 08:04:22.668] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 30666 us.
[2015-01-13 08:04:22.668] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 2 deg.
[2015-01-13 08:04:22.696] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24533 us. IntegerDelay: 0x1d3 FracDela
y: 0x36
[2015-01-13 08:04:22.696] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fc
[2015-01-13 08:04:22.696] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2743, currentDpdDelay[1]=1714 (0.1 ns)

[2015-01-13 08:04:22.696] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga


Delay:3659 [0.1ns]
[2015-01-13 08:04:22.696] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.696] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.700] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 08:04:22.700] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.700] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.700] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298911 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1714
[2015-01-13 08:04:22.700] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30431[ns] = salCarrierReportedDelay:298911 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:22.700] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 08:04:22.716] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 08:04:22.716] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.716] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.716] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 08:04:22.716] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)

[2015-01-13 08:04:22.716] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.716] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298911 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1714
[2015-01-13 08:04:22.720] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298911 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:22.720] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 08:04:22.732] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 08:04:22.732] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.732] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.732] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 08:04:22.732] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.732] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.732] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298911 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1714
[2015-01-13 08:04:22.736] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30431[ns] = salCarrierReportedDelay:298911 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:22.736] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns

[2015-01-13 08:04:22.748] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga


Delay:3659 [0.1ns]
[2015-01-13 08:04:22.748] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.748] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.748] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 08:04:22.748] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 08:04:22.748] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 08:04:22.748] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298911 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1714
[2015-01-13 08:04:22.752] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30431[ns] = salCarrierReportedDelay:298911 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 08:04:22.752] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 08:04:22.764] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 08:04:22.764] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 08:04:22.764] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id5
[2015-01-13 08:04:22.764] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id7
[2015-01-13 08:04:22.976] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x2062efb C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x6e
b4b9c C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0x8a5
57ce pa1Adj 0x4779
[2015-01-13 08:04:23.780] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,

fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1effb02 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
28d21 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0xb42
2e9d pa1Adj 0x4779
[2015-01-13 08:04:24.784] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x2062748 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
053ea C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0xb3f
671b pa1Adj 0x4779
[2015-01-13 08:04:25.804] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efdfab C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8f
fbda0 C1 0xa99f95 C2 0x0 C3 0x0, pa0C0Adj 0x1fda C
1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1
0xc122cb4 pa1Adj 0x4779
[2015-01-13 08:04:26.808] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f00925 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
2476b C1 0x10ded7f C2 0x0 C3 0x0, pa0C0Adj 0x1fda
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1
0xc926ab6 pa1Adj 0x4779
[2015-01-13 08:04:27.812] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eff0ed C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8f
eea09 C1 0x21b0691 C2 0x0 C3 0x0, pa0C0Adj 0x1fda
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1
0xddb2bcb pa1Adj 0x4779
[2015-01-13 08:04:28.816] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f7aef2 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
0b4f7 C1 0x4e17164 C2 0x0 C3 0x0, pa0C0Adj 0x1fda
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1
0x1152e567 pa1Adj 0x4779
[2015-01-13 08:04:29.828] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efeee7 C1 0x10b54e4 C2 0x0 C3 0x0, pmPa0C
0 0x904a24d C1 0x30d6e0e C2 0x0 C3 0x0, pa0C0Adj 0
x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010,
pmPa1 0xf10627b pa1Adj 0x4779
[2015-01-13 08:04:30.832] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef86d4 C1 0x0 C2 0x758d70 C3 0x0, pmPa0C0
0x901d909 C1 0x3b1459f C2 0x21c1f59 C3 0x0, pa0C0
Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x
8010, pmPa1 0x1277fa0f pa1Adj 0x4779
[2015-01-13 08:04:31.836] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x202f1db C1 0xce8e09 C2 0x0 C3 0x0, pmPa0C0
0x8ff3371 C1 0x2508177 C2 0x2a3e047 C3 0x0, pa0C0
Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x
8010, pmPa1 0x1165e8ba pa1Adj 0x4779
[2015-01-13 08:04:32.840] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1effbab C1 0x8d8949 C2 0x0 C3 0x0, pmPa0C0
0x9101cf1 C1 0x1af6ef0 C2 0x10de17c C3 0x0, pa0C0
Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x
8010, pmPa1 0xebae175 pa1Adj 0x4779
[2015-01-13 08:04:33.648] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,

fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1fedb60 C1 0x42dcc1 C2 0x0 C3 0x0, pmPa0C0
0x91a08b7 C1 0xc058ae C2 0x6b6799 C3 0x0, pa0C0Ad
j 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x80
10, pmPa1 0xcd4ef39 pa1Adj 0x4779
[2015-01-13 08:04:34.652] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x218ac15 C1 0x685acb C2 0x0 C3 0x0, pmPa0C0
0x8ffbb9c C1 0x2276b90 C2 0x87b6e1 C3 0x0, pa0C0A
dj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8
010, pmPa1 0xe960195 pa1Adj 0x4779
[2015-01-13 08:04:35.664] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f02023 C1 0x8ae27 C2 0x2271ea C3 0x0, pmP
a0C0 0x8efb36b C1 0x12d7d0c C2 0x162161c C3 0x0, p
a0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C
3 0x8010, pmPa1 0xe5b2f4c pa1Adj 0x4779
[2015-01-13 08:04:36.668] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eff965 C1 0x10987c C2 0x31ab4c C3 0x0, pm
Pa0C0 0x8fe11b9 C1 0x1a55028 C2 0x1c8f055 C3 0x0,
pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010
C3 0x8010, pmPa1 0xf82d55f pa1Adj 0x4779
[2015-01-13 08:04:37.672] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efda26 C1 0x6b2b5 C2 0x0 C3 0x0, pmPa0C0
0x91e4893 C1 0xad9c0f C2 0x2550fb6 C3 0x0, pa0C0Ad
j 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x80
10, pmPa1 0xf24e10f pa1Adj 0x4779
[2015-01-13 08:04:38.676] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef9034 C1 0x3ef86e C2 0x77c87 C3 0x0, pmP
a0C0 0x8dd7048 C1 0x8341e9 C2 0x1bd6f31 C3 0x0, pa
0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3
0x8010, pmPa1 0xde18e93 pa1Adj 0x4779
[2015-01-13 08:04:39.680] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x2046179 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8f
3886c C1 0x27470bf C2 0x2456503 C3 0x0, pa0C0Adj 0
x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010,
pmPa1 0x11118ba0 pa1Adj 0x4779
[2015-01-13 08:04:40.684] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1df9da7 C1 0x1289ff C2 0x1c4db58 C3 0x0, p
mPa0C0 0x9051409 C1 0xbe5c13 C2 0x235310a C3 0x0,
pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010
C3 0x8010, pmPa1 0xef25d2a pa1Adj 0x4779
[2015-01-13 10:02:10.992] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 793
[2015-01-13 10:02:10.992] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:25, clientId:102
[2015-01-13 10:02:10.996] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:02:11.000] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:11.000] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte

r 1
[2015-01-13 10:02:11.000] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=793, carrierConf.carrierRfPort=B
[2015-01-13 10:02:11.000] trDcProc rxGainComp.cc:225 INFO:rx4A4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=910700, carrierFreqMax=910900
[2015-01-13 10:02:11.000] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:11.004] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:25, clientId:102
[2015-01-13 10:02:11.004] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:25
[2015-01-13 10:02:11.016] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 794
[2015-01-13 10:02:11.016] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:26, clientId:102
[2015-01-13 10:02:11.020] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 7
[2015-01-13 10:02:11.024] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:11.024] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.024] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=794, carrierConf.carrierRfPort=B
[2015-01-13 10:02:11.024] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=910700, carrierFreqMax=910900
[2015-01-13 10:02:11.024] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:11.028] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:26, clientId:102
[2015-01-13 10:02:11.028] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:26
[2015-01-13 10:02:11.032] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:02:11.032] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0xf
[2015-01-13 10:02:11.052] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 1; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 955800, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFre
q: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800, sta
te: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: ON; dev: 8

, txFreq: 0, state: OFF;


[2015-01-13 10:02:11.052] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 792
[2015-01-13 10:02:11.056] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = 0 (gainOffset:0 + gainMargin:122)
[2015-01-13 10:02:11.056] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:11.056] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:24, clientId:102
[2015-01-13 10:02:11.060] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:02:11.060] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:02:11.060] trDcProc commonCsc.cc:498 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:02:11.060] trDcProc commonCsc.cc:498 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:02:11.060] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:02:11.060] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 792 event :4
[2015-01-13 10:02:11.060] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 1, txLo: 955840, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 955800, state: OFF; dev: 2, txFreq: 0, state:
OFF; dev: 3, txFreq: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, t
xFreq: 955800, state: ON; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800,
state: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:02:11.128] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:11.128] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:11.128] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:02:11.128] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm

[2015-01-13 10:02:11.176] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib


rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:02:11.176] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 53 deg
[2015-01-13 10:02:11.176] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25384
[2015-01-13 10:02:11.176] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 47466 us.
[2015-01-13 10:02:11.176] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 0 deg.
[2015-01-13 10:02:11.040] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 62666 us. IntegerDelay: 0x1d3 FracDela
y: 0x37
[2015-01-13 10:02:11.040] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fb
[2015-01-13 10:02:11.044] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2742, currentDpdDelay[1]=1713 (0.1 ns)
[2015-01-13 10:02:11.044] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.044] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.044] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298910 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1713
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi

lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298910 + vldbSize_0_1


ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.048] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.064] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298910 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1713
[2015-01-13 10:02:11.068] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30431[ns] = salCarrierReportedDelay:298910 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.068] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)

[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga


Delay:3659 [0.1ns]
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.080] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298910 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1713
[2015-01-13 10:02:11.084] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30431[ns] = salCarrierReportedDelay:298910 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.084] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:02:11.096] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955840, (result: true)
[2015-01-13 10:02:11.160] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 792, event: 4
[2015-01-13 10:02:11.160] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 318, event :4
[2015-01-13 10:02:11.160] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:02:11.180] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:02:11.184] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(0), invalidCarrierId=(128)

DL releas

[2015-01-13 10:02:11.184] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:02:11.184] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.188] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:11.192] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:11.192] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f

or carrierId:24, clientId:102
[2015-01-13 10:02:11.192] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:24
[2015-01-13 10:02:11.196] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:02:11.196] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:02:11.224] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 5; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 95
5800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800, state: O
FF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: ON; dev: 8, tx
Freq: 0, state: OFF;
[2015-01-13 10:02:11.224] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 798
[2015-01-13 10:02:11.228] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:11.228] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:30, clientId:102
[2015-01-13 10:02:11.228] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 2
[2015-01-13 10:02:11.228] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:02:11.228] trDcProc commonCsc.cc:498 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:02:11.228] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:02:11.228] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 798 event :4
[2015-01-13 10:02:11.232] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 5, txLo: 955840, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq
: 955800, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, sta
te: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:11.232] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:02:11.296] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.

[2015-01-13 10:02:11.300] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq


= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:11.300] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:02:11.300] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:02:11.328] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:02:11.328] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 53 deg
[2015-01-13 10:02:11.328] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25426
[2015-01-13 10:02:11.328] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29199 us.
[2015-01-13 10:02:11.328] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 0 deg.
[2015-01-13 10:02:11.356] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24400 us. IntegerDelay: 0x1d3 FracDela
y: 0x37
[2015-01-13 10:02:11.356] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fe
[2015-01-13 10:02:11.356] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2742, currentDpdDelay[1]=1713 (0.1 ns)
[2015-01-13 10:02:11.356] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.356] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.356] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)

[2015-01-13 10:02:11.360] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.360] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298910 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1713
[2015-01-13 10:02:11.360] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298910 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.360] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:02:11.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:02:11.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:02:11.376] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.376] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298910 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1713
[2015-01-13 10:02:11.380] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30431[ns] = salCarrierReportedDelay:298910 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.380] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns

[2015-01-13 10:02:11.392] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr


lAtRelease antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955840, (result: true)
[2015-01-13 10:02:11.444] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 798, event: 4
[2015-01-13 10:02:11.444] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31e, event :4
[2015-01-13 10:02:11.444] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:02:11.464] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:02:11.464] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(2), invalidCarrierId=(128)

DL releas

[2015-01-13 10:02:11.464] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:02:11.464] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.468] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:11.472] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:11.472] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:30, clientId:102
[2015-01-13 10:02:11.472] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:30
[2015-01-13 10:02:11.476] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:02:11.476] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:02:11.504] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 7; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 95
5800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF; dev: 8, txFreq
: 0, state: OFF;
[2015-01-13 10:02:11.504] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 801
[2015-01-13 10:02:11.504] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:11.504] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:33, clientId:102

[2015-01-13 10:02:11.508] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi


ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 1
[2015-01-13 10:02:11.508] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:02:11.508] trDcProc commonCsc.cc:498 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:02:11.508] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 801 event :4
[2015-01-13 10:02:11.508] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 7, txLo: 955840, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq
: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: O
FF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:11.508] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:02:11.576] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:11.576] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:11.576] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:02:11.576] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:02:11.600] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xc,
fabEnCd 0xc, fabForce 0xd, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x2014 C2 0x0 C3 0
x2014, ncoC0 0x0 C1 0x8010 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:11.628] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:02:11.628] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 53 deg
[2015-01-13 10:02:11.628] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 25461
[2015-01-13 10:02:11.628] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 51866 us.
[2015-01-13 10:02:11.628] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase

correction versus flash: 0 deg.


[2015-01-13 10:02:11.656] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 25999 us. IntegerDelay: 0x1d3 FracDela
y: 0x36
[2015-01-13 10:02:11.656] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fd
[2015-01-13 10:02:11.660] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2743, currentDpdDelay[1]=1714 (0.1 ns)
[2015-01-13 10:02:11.660] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:02:11.660] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:11.660] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.660] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:02:11.660] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:11.660] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.664] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298910 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3658 + DpdDelay:1714
[2015-01-13 10:02:11.664] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298910 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.664] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:02:11.676] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955840, (result: true)
[2015-01-13 10:02:11.712] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 801, event: 4

[2015-01-13 10:02:11.712] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd


ateEvent, carrierId (hex): 321, event :4
[2015-01-13 10:02:11.712] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:02:11.728] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:02:11.728] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(3), invalidCarrierId=(128)

DL releas

[2015-01-13 10:02:11.728] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:02:11.728] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:11.732] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:11.736] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:02:11.748] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:02:11.748] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:02:11.752] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:02:11.752] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:02:11.752] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:02:11.768] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:02:11.772] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:02:11.772] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:11.772] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.772] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]

[2015-01-13 10:02:11.772] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD


elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:11.772] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:11.772] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298945 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3658 + DpdDelay:1749
[2015-01-13 10:02:11.776] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30435[ns] = salCarrierReportedDelay:298945 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:11.776] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 10:02:11.852] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:02:11.852] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:02:11.852] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:02:11.876] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:02:11.876] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:02:11.876] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:02:11.876] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:02:11.876] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 10:02:12.080] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:12.084] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:02:12.084] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955800

[2015-01-13 10:02:12.084] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq


= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:12.084] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955840 (result: true)
[2015-01-13 10:02:12.084] trDcProc dlCtrl.cc:228 INFO:Carrier id 795, FilterBran
ch id 1 is added into reEnabledCarrierFBList
[2015-01-13 10:02:12.084] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnPendEvent
[2015-01-13 10:02:12.084] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:02:12.084] trDcProc dlCtrl.cc:385 INFO:1 enabled carriers, re ena
ble started!
[2015-01-13 10:02:12.084] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:02:12.084] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 3, ccData.filterBranch 1, carrierConf.carrierId 795
[2015-01-13 10:02:12.084] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:02:12.084] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 3; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955
800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:02:12.084] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:02:12.084] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 10:02:12.084] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:02:12.096] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:02:12.176] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:12.176] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:02:12.176] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in

put enabled
[2015-01-13 10:02:12.176] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 10:02:12.176] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-i[-42.55 -8.00], DpdPma:-i[-i -i], Pmb:-i, TorPmb:-58.13[-i -8.00] d
B)
[2015-01-13 10:02:12.180] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 10:02:12.180] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:02:12.180] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:33, clientId:102
[2015-01-13 10:02:12.180] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:33
[2015-01-13 10:02:12.180] trDcProc dlCtrl.cc:261 INFO:DlCtrl::carrierUpdateEvent
: remove the filter branch id 1 from the reEnabledCarrierFBList upon receipt of
event CR_SUBSCRIPTION_EVENT_CARRIER_DISABLED
[2015-01-13 10:02:12.180] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 799
[2015-01-13 10:02:12.180] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:31, clientId:102
[2015-01-13 10:02:12.184] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 1
[2015-01-13 10:02:12.188] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:12.188] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:12.188] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=799, carrierConf.carrierRfPort=B
[2015-01-13 10:02:12.188] trDcProc rxGainComp.cc:225 INFO:rx4A2 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:02:12.188] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:12.188] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:31, clientId:102
[2015-01-13 10:02:12.188] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:31
[2015-01-13 10:02:12.188] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 802
[2015-01-13 10:02:12.188] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:34, clientId:102

[2015-01-13 10:02:12.192] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi


nk, fb 0
[2015-01-13 10:02:12.196] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:12.196] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:12.196] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=802, carrierConf.carrierRfPort=B
[2015-01-13 10:02:12.196] trDcProc rxGainComp.cc:225 INFO:rx4A1 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:02:12.196] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:12.196] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:34, clientId:102
[2015-01-13 10:02:12.196] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:34
[2015-01-13 10:02:12.200] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 796
[2015-01-13 10:02:12.200] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:28, clientId:102
[2015-01-13 10:02:12.204] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:02:12.204] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:12.204] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:12.204] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=796, carrierConf.carrierRfPort=B
[2015-01-13 10:02:12.204] trDcProc rxGainComp.cc:225 INFO:rx4A3 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:02:12.204] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:12.204] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:28, clientId:102
[2015-01-13 10:02:12.204] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:28
[2015-01-13 10:02:12.268] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state RAMPING
, de off, ga on; dev: 1, txFreq: 0, state: OFF; de
v: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: INIT; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d

ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s


tate: OFF;
[2015-01-13 10:02:12.268] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:02:12.268] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955800
[2015-01-13 10:02:12.268] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:12.268] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955840 (result: true)
[2015-01-13 10:02:12.284] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-34.12[-61.50 -8.00] dB)
[2015-01-13 10:02:12.292] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 795, event: 512
[2015-01-13 10:02:12.292] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :512
[2015-01-13 10:02:12.292] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
58 [0.1ns]
[2015-01-13 10:02:12.292] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:12.292] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:02:12.292] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
58 [0.1ns]
[2015-01-13 10:02:12.292] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:02:12.292] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:02:12.296] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298945 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3658 + DpdDelay:1749
[2015-01-13 10:02:12.296] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:1)tTrpToArp:30435[ns] = salCarrierReportedDelay:298945 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput

:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set


BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:12.296] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 10:02:12.308] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:02:12.320] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:02:12.320] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:02:12.708] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xc,
fabEnCd 0x0, fabForce 0xd, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x2014 C2 0x0 C3 0
x0, ncoC0 0x0 C1 0x8010 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:12.896] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.118837, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 10:02:13.072] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.47[-61.50 -8.00] dB)
[2015-01-13 10:02:13.072] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:13.072] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x04340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:02:13.072] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:02:13.100] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:02:13.100] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 53 deg
[2015-01-13 10:02:13.100] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24662
[2015-01-13 10:02:13.104] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29333 us.
[2015-01-13 10:02:13.104] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 0 deg.
[2015-01-13 10:02:13.132] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 25999 us. IntegerDelay: 0x1d3 FracDela
y: 0x35

[2015-01-13 10:02:13.132] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac


tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fd
[2015-01-13 10:02:13.132] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2744, currentDpdDelay[1]=1715 (0.1 ns)
[2015-01-13 10:02:13.132] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:02:13.132] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:13.132] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:13.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:02:13.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:13.136] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:13.136] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298927 = tRuInternalDlDb:292940 + tDlFreqCompDelay:616 + tInter
nalBfnDelay:3656 + DpdDelay:1715
[2015-01-13 10:02:13.136] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30433[ns] = salCarrierReportedDelay:298927 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:13.136] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 262 ns
[2015-01-13 10:02:13.148] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 10:02:13.148] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 95640
0 (kHz), compensatedFreq = 956400 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:02:13.156] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=795
[2015-01-13 10:02:13.156] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w

ith frequency hopping enabled found


[2015-01-13 10:02:13.160] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 7 iteration
[2015-01-13 10:02:13.212] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 956400, txLo: 956400, Status: dpd on, state TUNED, d
e on, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: ON; dev: 4, txFreq: 0, s
tate: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7,
txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:02:13.212] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:02:13.212] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 956400
[2015-01-13 10:02:13.212] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 956400, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:13.280] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 956400, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:13.280] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 956400, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:02:13.280] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:02:13.280] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:02:13.308] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:02:13.308] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 53 deg
[2015-01-13 10:02:13.308] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24665
[2015-01-13 10:02:13.312] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29733 us.
[2015-01-13 10:02:13.312] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 0 deg.
[2015-01-13 10:02:13.344] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 29866 us. IntegerDelay: 0x1d3 FracDela
y: 0x28

[2015-01-13 10:02:13.344] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac


tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fb
[2015-01-13 10:02:13.344] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2757, currentDpdDelay[1]=1723 (0.1 ns)
[2015-01-13 10:02:13.344] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:02:13.344] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:13.344] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:13.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:02:13.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:13.348] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:02:13.348] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298935 = tRuInternalDlDb:292940 + tDlFreqCompDelay:616 + tInter
nalBfnDelay:3656 + DpdDelay:1723
[2015-01-13 10:02:13.348] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30434[ns] = salCarrierReportedDelay:298935 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:13.348] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 261 ns
[2015-01-13 10:02:13.360] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 956400 (result: true)
[2015-01-13 10:02:13.432] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 795, event: 512
[2015-01-13 10:02:13.432] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :512
[2015-01-13 10:02:13.432] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36

56 [0.1ns]
[2015-01-13 10:02:13.432] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:13.432] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:02:13.432] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
56 [0.1ns]
[2015-01-13 10:02:13.432] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:02:13.432] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:02:13.432] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298935 = tRuInternalDlDb:292940 + tDlFreqCompDelay:616 + tInternalBfnDe
lay:3656 + DpdDelay:1723
[2015-01-13 10:02:13.436] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:1)tTrpToArp:30434[ns] = salCarrierReportedDelay:298935 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:02:13.436] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 261 ns
[2015-01-13 10:02:13.448] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:02:13.452] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 7 iteration
[2015-01-13 10:02:13.456] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 956400 and vector width to 1400
[2015-01-13 10:02:13.456] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 800
[2015-01-13 10:02:13.456] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:32, clientId:102
[2015-01-13 10:02:13.460] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 5
[2015-01-13 10:02:13.460] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true

[2015-01-13 10:02:13.460] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte


r 1
[2015-01-13 10:02:13.460] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=800, carrierConf.carrierRfPort=B
[2015-01-13 10:02:13.464] trDcProc rxGainComp.cc:225 INFO:rx4B2 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:02:13.464] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 956400 and vector width to 1400
[2015-01-13 10:02:13.464] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:32, clientId:102
[2015-01-13 10:02:13.464] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:32
[2015-01-13 10:02:13.464] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 803
[2015-01-13 10:02:13.464] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:35, clientId:102
[2015-01-13 10:02:13.468] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 4
[2015-01-13 10:02:13.468] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:13.468] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:13.468] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=803, carrierConf.carrierRfPort=B
[2015-01-13 10:02:13.468] trDcProc rxGainComp.cc:225 INFO:rx4B1 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:02:13.472] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 956400 and vector width to 1400
[2015-01-13 10:02:13.472] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:35, clientId:102
[2015-01-13 10:02:13.472] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:35
[2015-01-13 10:02:13.472] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 797
[2015-01-13 10:02:13.472] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:29, clientId:102
[2015-01-13 10:02:13.476] trDcProc carrierListHandler.cc:474 INFO:CarrierListHan
dler::rxLoUpdated() CR_SUBSCRIPTION_EVENT_UL_RXLO carrierId=797
[2015-01-13 10:02:13.476] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found

[2015-01-13 10:02:13.476] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre


quency hopping end for range:1 after 13 iteration
[2015-01-13 10:02:13.476] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(29), fb=(6), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:02:13.476] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi


nk, fb 6
[2015-01-13 10:02:13.480] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:02:13.480] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:13.480] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=797, carrierConf.carrierRfPort=B
[2015-01-13 10:02:13.480] trDcProc rxGainComp.cc:225 INFO:rx4B3 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:02:13.480] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 956400 and vector width to 1400
[2015-01-13 10:02:13.480] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:29, clientId:102
[2015-01-13 10:02:13.480] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:29
[2015-01-13 10:02:13.480] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:02:13.480] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:02:13.480] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:02:13.480] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:02:13.488] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:02:13.488] trxCtrlDpdProc_0 dpdController.cc:2808 INFO:Since TX-o
n the DPD has restarted 0 times.
[2015-01-13 10:02:13.488] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 3; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 95
6400, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF;
dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:02:13.488] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 795

[2015-01-13 10:02:13.488] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin


g #####: PAR = 0
[2015-01-13 10:02:13.488] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOffEvent. Current state is paOnPendEvent
[2015-01-13 10:02:13.488] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:02:13.492] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:02:13.492] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:27, clientId:102
[2015-01-13 10:02:13.492] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 0
[2015-01-13 10:02:13.492] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:02:13.492] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 795 event :4
[2015-01-13 10:02:13.496] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 94250
0 (kHz), compensatedFreq = 942480 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:02:13.500] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 3, txLo: 942480, Status: dpd off, state OFF, de off, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 956400, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFre
q: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:02:13.500] trxCtrlDpdProc_0 dpdController.cc:2564 INFO:TX_RELEASE
resets TxRealSynthFreq
[2015-01-13 10:02:13.500] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 942480, (result: true)
[2015-01-13 10:02:13.512] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 795, event: 4
[2015-01-13 10:02:13.512] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :4
[2015-01-13 10:02:13.512] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(1), invalidCarrierId=(128)

DL releas

[2015-01-13 10:02:13.512] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:02:13.512] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:02:13.516] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:02:13.536] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD

delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)


[2015-01-13 10:02:13.600] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:02:13.600] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:02:13.600] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:02:13.624] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:02:13.624] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:02:13.624] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:02:13.624] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:02:13.628] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 3, paIdInternal: 0
[2015-01-13 10:02:13.828] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOffEvent. Current state is paOffEvent
[2015-01-13 10:02:13.828] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:02:13.828] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:27, clientId:102
[2015-01-13 10:02:13.828] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:27
[2015-01-13 10:02:13.836] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O DEPENDENT RESOURCE MISSING
[2015-01-13 10:02:13.840] ledProc erciMmi.cc:221 INFO:Vii: 0x00000010
[2015-01-13 10:02:14.084] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:15.100] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:16.104] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:17.112] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0

C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,


ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:18.116] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:19.124] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:20.128] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:21.148] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:21.956] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:22.960] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:23.968] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:24.972] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:25.980] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:26.984] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:27.988] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:28.992] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0

C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,


ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:29.996] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:31.000] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:31.808] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:32.812] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:33.816] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:34.820] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:02:35.824] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:17:32.712] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O DEPENDENT RESOURCE MISSING END
[2015-01-13 10:17:32.712] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:17:32.712] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:17:32.712] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O BUSY
[2015-01-13 10:17:32.712] ledProc erciMmi.cc:221 INFO:Vii: 0x00000004
[2015-01-13 10:18:42.128] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:42.132] trDcProc carrierListHandler.cc:474 INFO:CarrierListHan
dler::rxLoUpdated() CR_SUBSCRIPTION_EVENT_UL_RXLO carrierId=793
[2015-01-13 10:18:42.132] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:42.132] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte

r 1
[2015-01-13 10:18:42.136] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=793, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.136] trDcProc rxGainComp.cc:225 INFO:rx4A4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=910700, carrierFreqMax=910900
[2015-01-13 10:18:42.136] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:18:42.136] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.140] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:18:42.140] trDcProc delayCommHandler.cc:312 INFO:carrier:0x319 tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:18:42.140] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:42.140] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:42.140] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.140] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
3 tRuReportedDelayUl:121741[0.1 ns] = tRuUl:125400 - tInternalBfnDelay:3659
[2015-01-13 10:18:42.140] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.144] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:18:42.144] trDcProc delayCommHandler.cc:312 INFO:carrier:0x319 tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:18:42.144] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
3 tRuProcDelayUl:151660[0.1 ns] = tRuUl:125400 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:42.144] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:42.144] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:42.144] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 10:18:42.144] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi


lterBranch:3):calc_tArpToTrp:-140141[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121741 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:42.144] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14014,filterBranch:3
[2015-01-13 10:18:42.148] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:42.148] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:42.148] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:42.148] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:18:42.148] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
[2015-01-13 10:18:42.148] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 3, value 438
[2015-01-13 10:18:42.148] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:3 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:42.148] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2075 ns
[2015-01-13 10:18:42.148] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:42.176] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
[2015-01-13 10:18:42.176] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 3, CPRI port 0
[2015-01-13 10:18:42.176] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:25, clientId:102
[2015-01-13 10:18:42.192] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:42.192] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:42.192] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.200] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=794, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.200] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=20

0, signalBW=200, carrierFreqMin=910700, carrierFreqMax=910900


[2015-01-13 10:18:42.200] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:18:42.200] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.204] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:18:42.204] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31a tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:18:42.204] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:42.204] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:42.204] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.204] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
4 tRuReportedDelayUl:121721[0.1 ns] = tRuUl:125380 - tInternalBfnDelay:3659
[2015-01-13 10:18:42.204] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.204] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:18:42.204] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31a tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:18:42.204] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
4 tRuProcDelayUl:151640[0.1 ns] = tRuUl:125380 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:42.208] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:7):calc_tArpToTrp:-139951[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121721 - tAnpUl:780 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:42.208] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13995,filterBranch:7
[2015-01-13 10:18:42.212] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:42.212] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:42.212] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)

[2015-01-13 10:18:42.212] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi


nk, fb 7
[2015-01-13 10:18:42.212] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 7, data 0
[2015-01-13 10:18:42.212] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 7, value 438
[2015-01-13 10:18:42.212] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:7 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:42.212] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2094 ns
[2015-01-13 10:18:42.212] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:42.240] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 7, data 0
[2015-01-13 10:18:42.240] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 7, CPRI port 0
[2015-01-13 10:18:42.240] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:26, clientId:102
[2015-01-13 10:18:42.264] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 793
[2015-01-13 10:18:42.264] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:25, clientId:102
[2015-01-13 10:18:42.268] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 794
[2015-01-13 10:18:42.268] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:26, clientId:102
[2015-01-13 10:18:42.316] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O BUSY END
[2015-01-13 10:18:42.316] ledProc erciMmi.cc:221 INFO:Vii: 0x00040000
[2015-01-13 10:18:42.316] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:18:42.508] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:42.512] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:42.512] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:18:42.512] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(28), fb=(2), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:42.512] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =

true
[2015-01-13 10:18:42.512] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.516] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=796, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.516] trDcProc rxGainComp.cc:225 INFO:rx4A3 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:18:42.520] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:18:42.520] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.520] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:18:42.520] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31c tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:18:42.524] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:42.524] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:42.524] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.524] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
6 tRuReportedDelayUl:121741[0.1 ns] = tRuUl:125400 - tInternalBfnDelay:3659
[2015-01-13 10:18:42.524] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.524] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:18:42.524] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31c tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:18:42.524] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
6 tRuProcDelayUl:151660[0.1 ns] = tRuUl:125400 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:42.528] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:2):calc_tArpToTrp:-140141[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121741 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:42.528] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14014,filterBranch:2

[2015-01-13 10:18:42.528] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0


), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:42.532] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:42.532] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:42.532] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:18:42.532] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:18:42.532] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 2, value 438
[2015-01-13 10:18:42.532] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:2 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:42.532] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2075 ns
[2015-01-13 10:18:42.532] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:42.560] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:18:42.560] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 2, CPRI port 0
[2015-01-13 10:18:42.560] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:28, clientId:102
[2015-01-13 10:18:42.584] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:42.588] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:42.588] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:18:42.588] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(29), fb=(6), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:42.588] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:42.588] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.592] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=797, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.596] trDcProc rxGainComp.cc:225 INFO:rx4B3 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100

[2015-01-13 10:18:42.596] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven


t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:18:42.596] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.600] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:18:42.600] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31d tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:18:42.600] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:42.600] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:42.600] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.600] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
7 tRuReportedDelayUl:121721[0.1 ns] = tRuUl:125380 - tInternalBfnDelay:3659
[2015-01-13 10:18:42.600] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.600] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:18:42.600] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31d tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:18:42.600] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
7 tRuProcDelayUl:151640[0.1 ns] = tRuUl:125380 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:42.604] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:6):calc_tArpToTrp:-139951[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121721 - tAnpUl:780 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:42.604] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13995,filterBranch:6
[2015-01-13 10:18:42.604] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:42.608] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:42.608] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)

[2015-01-13 10:18:42.608] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi


nk, fb 6
[2015-01-13 10:18:42.608] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:18:42.608] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 6, value 438
[2015-01-13 10:18:42.608] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:6 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:42.608] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2094 ns
[2015-01-13 10:18:42.608] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:42.636] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:18:42.636] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 6, CPRI port 0
[2015-01-13 10:18:42.636] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:29, clientId:102
[2015-01-13 10:18:42.664] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 796
[2015-01-13 10:18:42.664] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:28, clientId:102
[2015-01-13 10:18:42.668] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 797
[2015-01-13 10:18:42.668] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:29, clientId:102
[2015-01-13 10:18:42.732] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=1
[2015-01-13 10:18:42.732] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:42.736] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(31), fb=(1), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:42.736] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:42.736] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.740] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=799, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.740] trDcProc rxGainComp.cc:225 INFO:rx4A2 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100

[2015-01-13 10:18:42.740] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven


t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:18:42.744] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.744] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:18:42.744] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31f tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:18:42.744] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:42.748] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:42.748] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.748] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
9 tRuReportedDelayUl:121741[0.1 ns] = tRuUl:125400 - tInternalBfnDelay:3659
[2015-01-13 10:18:42.748] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.748] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:18:42.748] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31f tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:18:42.748] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
9 tRuProcDelayUl:151660[0.1 ns] = tRuUl:125400 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:42.752] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:1):calc_tArpToTrp:-140141[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121741 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:42.752] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14014,filterBranch:1
[2015-01-13 10:18:42.752] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:42.756] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:42.756] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:42.756] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi

nk, fb 1
[2015-01-13 10:18:42.756] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:18:42.756] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 1, value 438
[2015-01-13 10:18:42.756] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:1 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:42.756] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2075 ns
[2015-01-13 10:18:42.756] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:42.784] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:18:42.784] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 1, CPRI port 0
[2015-01-13 10:18:42.784] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:31, clientId:102
[2015-01-13 10:18:42.800] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=3
[2015-01-13 10:18:42.804] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:42.804] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(32), fb=(5), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:42.804] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:42.804] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.808] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=800, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.812] trDcProc rxGainComp.cc:225 INFO:rx4B2 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:18:42.812] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:18:42.812] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.816] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:18:42.816] trDcProc delayCommHandler.cc:312 INFO:carrier:0x320 tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:18:42.816] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36

59 [0.1ns]
[2015-01-13 10:18:42.816] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:42.816] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.816] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:80
0 tRuReportedDelayUl:121721[0.1 ns] = tRuUl:125380 - tInternalBfnDelay:3659
[2015-01-13 10:18:42.816] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.816] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:18:42.816] trDcProc delayCommHandler.cc:312 INFO:carrier:0x320 tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:18:42.820] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:80
0 tRuProcDelayUl:151640[0.1 ns] = tRuUl:125380 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:42.820] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:5):calc_tArpToTrp:-139951[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121721 - tAnpUl:780 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:42.820] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13995,filterBranch:5
[2015-01-13 10:18:42.824] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:42.824] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:42.824] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:42.824] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 5
[2015-01-13 10:18:42.824] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 5, data 0
[2015-01-13 10:18:42.824] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 5, value 438
[2015-01-13 10:18:42.824] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:5 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:42.824] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2094 ns

[2015-01-13 10:18:42.824] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg


Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:42.852] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 5, data 0
[2015-01-13 10:18:42.852] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 5, CPRI port 0
[2015-01-13 10:18:42.852] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:32, clientId:102
[2015-01-13 10:18:42.876] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 799
[2015-01-13 10:18:42.876] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:31, clientId:102
[2015-01-13 10:18:42.880] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 800
[2015-01-13 10:18:42.880] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:32, clientId:102
[2015-01-13 10:18:42.916] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=0
[2015-01-13 10:18:42.920] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:42.924] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(34), fb=(0), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:42.924] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:42.924] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.928] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=802, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.928] trDcProc rxGainComp.cc:225 INFO:rx4A1 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:18:42.928] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:18:42.932] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.932] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:18:42.932] trDcProc delayCommHandler.cc:312 INFO:carrier:0x322 tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:18:42.932] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]

[2015-01-13 10:18:42.932] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20


), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:42.932] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:42.932] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:80
2 tRuReportedDelayUl:121741[0.1 ns] = tRuUl:125400 - tInternalBfnDelay:3659
[2015-01-13 10:18:42.932] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:42.936] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:18:42.936] trDcProc delayCommHandler.cc:312 INFO:carrier:0x322 tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:18:42.936] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:80
2 tRuProcDelayUl:151660[0.1 ns] = tRuUl:125400 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:42.936] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:0):calc_tArpToTrp:-140141[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121741 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:42.936] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14014,filterBranch:0
[2015-01-13 10:18:42.940] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:42.940] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:42.940] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:42.940] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 0
[2015-01-13 10:18:42.940] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:18:42.940] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 0, value 438
[2015-01-13 10:18:42.940] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:0 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:42.940] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2075 ns

[2015-01-13 10:18:42.940] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg


Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:42.968] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:18:42.968] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 0, CPRI port 0
[2015-01-13 10:18:42.968] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:34, clientId:102
[2015-01-13 10:18:42.984] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=2
[2015-01-13 10:18:42.988] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:42.992] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(35), fb=(4), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:18:42.992] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:18:42.992] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:42.996] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=803, carrierConf.carrierRfPort=B
[2015-01-13 10:18:42.996] trDcProc rxGainComp.cc:225 INFO:rx4B1 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:18:42.996] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:18:43.000] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:18:43.000] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:18:43.000] trDcProc delayCommHandler.cc:312 INFO:carrier:0x323 tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:18:43.000] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:43.000] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:43.000] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:43.000] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:80
3 tRuReportedDelayUl:121721[0.1 ns] = tRuUl:125380 - tInternalBfnDelay:3659

[2015-01-13 10:18:43.000] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm


a =5330
[2015-01-13 10:18:43.004] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:18:43.004] trDcProc delayCommHandler.cc:312 INFO:carrier:0x323 tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:18:43.004] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:80
3 tRuProcDelayUl:151640[0.1 ns] = tRuUl:125380 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:18:43.004] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:4):calc_tArpToTrp:-139951[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121721 - tAnpUl:780 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:18:43.008] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13995,filterBranch:4
[2015-01-13 10:18:43.008] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:18:43.008] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:18:43.008] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:18:43.008] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 4
[2015-01-13 10:18:43.008] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 4, data 0
[2015-01-13 10:18:43.008] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 4, value 438
[2015-01-13 10:18:43.008] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:4 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:18:43.008] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2094 ns
[2015-01-13 10:18:43.008] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:18:43.036] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 4, data 0
[2015-01-13 10:18:43.036] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 4, CPRI port 0
[2015-01-13 10:18:43.036] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:35, clientId:102
[2015-01-13 10:18:43.060] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB

LED successful for carrier 802


[2015-01-13 10:18:43.060] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:34, clientId:102
[2015-01-13 10:18:43.064] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 803
[2015-01-13 10:18:43.064] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:35, clientId:102
[2015-01-13 10:18:44.116] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpA_mcr registe
rs: --------------------[2015-01-13 10:18:44.116] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x10000 C1 0x10000 C2 0x10000 C3 0x10000
[2015-01-13 10:18:44.116] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpB_mcr registe
rs: --------------------[2015-01-13 10:18:44.116] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x10000 C1 0x10000 C2 0x10000 C3 0x10000
[2015-01-13 10:18:44.116] timeOutSrv rxTraceWarp1x.cc:149 INFO:CF_CGB_UL_TEST 0x
ff
[2015-01-13 10:18:44.116] timeOutSrv rxTraceWarp1x.cc:168 INFO:CF_CPRI_UL_FB_X_C
FG C0 0x94000002, C1 0x91000002, C2 0x94000001, C3 0x91000001, C4 0x98000002, C5
0x92000002, C6 0x98000001, C7 0x92000001
[2015-01-13 10:18:44.116] timeOutSrv rxTraceWarp1x.cc:93 INFO:endTrace
[2015-01-13 10:18:48.164] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:18:48.168] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:48.168] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:18:48.180] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:48.180] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:48.196] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:18:48.268] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:18:48.268] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:18:48.268] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:18:48.292] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData

information isWarp: 0x1, isClassic 0x0


[2015-01-13 10:18:48.292] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:18:48.292] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:18:48.292] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:18:48.292] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 1, paIdInternal: 0
[2015-01-13 10:18:48.496] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4780 (closest actual 4780)
[2015-01-13 10:18:48.496] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:18:48.496] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 0
[2015-01-13 10:18:48.500] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 1
[2015-01-13 10:18:48.500] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:18:48.500] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 792 event :8
[2015-01-13 10:18:48.504] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 95580
0 (kHz), compensatedFreq = 955840 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:18:48.508] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=792
[2015-01-13 10:18:48.512] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:48.512] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:18:48.512] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955800
[2015-01-13 10:18:48.512] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:18:48.512] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955840 (result: true)

[2015-01-13 10:18:48.540] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr


ierUpdateEvent successful for carrier: 792, event: 8
[2015-01-13 10:18:48.540] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 318, event :8
[2015-01-13 10:18:48.540] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:48.540] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:48.544] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 200
[2015-01-13 10:18:48.544] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 318, event :1024
[2015-01-13 10:18:48.548] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:48.548] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.548] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.548] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.548] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 318, event :128
[2015-01-13 10:18:48.552] trDcProc dlDelayEventSubscriber.cc:783 INFO:isBfnAdvan
cerSetAtFirstCarrier: ON, rfPort 1
[2015-01-13 10:18:48.552] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]

[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20


), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.552] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.556] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.556] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:0)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:1,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:48.556] trDcProc platformXDlDelayAdjust.cc:104 INFO:BFN_ADVANC
E bfnAdvanceAdjustedDelay[0] = 30436.197917
[2015-01-13 10:18:48.556] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 10:18:48.568] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:24, clientId:102
[2015-01-13 10:18:48.576] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:18:48.584] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:18:48.584] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 1
[2015-01-13 10:18:48.584] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 2
[2015-01-13 10:18:48.584] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter

[2015-01-13 10:18:48.584] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri


erUpdateEvent successful for carrier: 795 event :8
[2015-01-13 10:18:48.588] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:18:48.588] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7
, txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:18:48.588] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:18:48.588] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 10:18:48.588] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:18:48.588] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 10:18:48.588] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:18:48.588] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955840 (result: true)
[2015-01-13 10:18:48.632] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 795, event: 8
[2015-01-13 10:18:48.632] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :8
[2015-01-13 10:18:48.632] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:48.648] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:18:48.652] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:48.652] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:48.656] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:18:48.656] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :1024
[2015-01-13 10:18:48.660] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]

[2015-01-13 10:18:48.660] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20


), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.660] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.660] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.660] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :128
[2015-01-13 10:18:48.660] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 10:18:48.660] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:18:48.664] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:48.664] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.664] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.664] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:48.664] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.664] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.664] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.668] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:1)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1

[2015-01-13 10:18:48.668] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe


lay set vldb to 260 ns
[2015-01-13 10:18:48.680] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:27, clientId:102
[2015-01-13 10:18:48.688] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:18:48.696] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:18:48.696] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 2
[2015-01-13 10:18:48.696] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:18:48.696] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:18:48.696] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 798 event :8
[2015-01-13 10:18:48.700] - fault_manager.cc:1901 INFO:Event TX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:48.700] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 10:18:48.700] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 10:18:48.700] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 10:18:48.700] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:18:48.700] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 10:18:48.700] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:18:48.704] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955840 (result: true)
[2015-01-13 10:18:48.756] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 798, event: 8

[2015-01-13 10:18:48.756] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd


ateEvent, carrierId (hex): 31e, event :8
[2015-01-13 10:18:48.756] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:48.776] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:18:48.776] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:48.776] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:48.780] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:18:48.784] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31e, event :1024
[2015-01-13 10:18:48.784] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:48.784] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.784] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.788] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.788] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31e, event :128
[2015-01-13 10:18:48.788] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 10:18:48.788] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:18:48.788] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:48.788] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.788] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 10:18:48.792] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36


59 [0.1ns]
[2015-01-13 10:18:48.792] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.792] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:48.792] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.792] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:2)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:48.792] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 10:18:48.808] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:30, clientId:102
[2015-01-13 10:18:48.816] trDcProc powerClassCtrl.cc:487 INFO:totGsmCarrierPwrDb
m :4892 is higher than selected higherPowerClass:4780, maxPowerClass:4900 will b
e set
[2015-01-13 10:18:48.816] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4900
[2015-01-13 10:18:48.824] - fault_manager.cc:1901 INFO:Event TX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:18:48.824] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:18:48.836] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:48.836] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:48.852] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:18:48.856] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:48.856] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)

[2015-01-13 10:18:48.856] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.856] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:48.856] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.856] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.860] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.860] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:48.860] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 10:18:48.872] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:48.872] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.872] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.872] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:48.872] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.872] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.872] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter

nalBfnDelay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.876] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:48.876] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 10:18:48.888] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:48.888] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.888] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.888] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:48.888] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:48.888] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:48.888] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1749
[2015-01-13 10:18:48.892] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:48.892] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 10:18:48.972] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:18:48.972] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:18:48.972] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0

[2015-01-13 10:18:48.992] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData


information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:18:48.992] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:18:48.992] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:18:48.996] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:18:48.996] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 10:18:49.200] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.200] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:18:49.200] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955800
[2015-01-13 10:18:49.200] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:18:49.200] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955840 (result: true)
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7
, txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x

7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak


New = 0x72913B00.
[2015-01-13 10:18:49.204] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955840 (result: true)
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:18:49.204] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 10:18:49.208] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:18:49.208] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955840 (result: true)
[2015-01-13 10:18:49.208] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 10:18:49.208] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:18:49.208] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 3
[2015-01-13 10:18:49.208] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 4
[2015-01-13 10:18:49.208] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:18:49.208] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 801 event :8
[2015-01-13 10:18:49.212] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 7, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 955800, state: OFF; dev: 6, txFreq: 0, state: O
FF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq:
0, state: OFF;

[2015-01-13 10:18:49.212] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of


configured carriers: tx: 3, rx: 0
[2015-01-13 10:18:49.216] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:4 carrier
configuration
[2015-01-13 10:18:49.216] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:18:49.216] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 10:18:49.216] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:18:49.216] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955840 (result: true)
[2015-01-13 10:18:49.284] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 801, event: 8
[2015-01-13 10:18:49.284] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :8
[2015-01-13 10:18:49.284] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:18:49.308] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:18:49.308] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:18:49.308] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:18:49.312] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:18:49.316] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :1024
[2015-01-13 10:18:49.316] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:49.316] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:49.316] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:49.316] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe

lay:3659 + DpdDelay:1749
[2015-01-13 10:18:49.320] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :128
[2015-01-13 10:18:49.320] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 10:18:49.320] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:18:49.320] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:49.320] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:49.320] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:49.324] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:18:49.324] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:49.324] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:18:49.324] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:18:49.324] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:3)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:18:49.324] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 10:18:49.336] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:33, clientId:102
[2015-01-13 10:18:49.360] - fault_manager.cc:1910 INFO:Set event PA_ON_EVENT to
time: 20000[ms], from 0x10097
[2015-01-13 10:18:49.360] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOffEvent

[2015-01-13 10:18:49.360] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta


te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:18:49.364] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:18:49.364] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:18:49.364] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:18:49.364] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 792
[2015-01-13 10:18:49.364] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:18:49.364] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 1; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 955800, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 955800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800, sta
te: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF; dev:
8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.364] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:18:49.364] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 10:18:49.372] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:18:49.452] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:18:49.456] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:18:49.456] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:49.456] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 10:18:49.456] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-i[-42.55 -8.00], DpdPma:-i[-i -i], Pmb:-i, TorPmb:-58.19[-i -8.00] d
B)
[2015-01-13 10:18:49.456] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 792 ENABLE ev
ent
[2015-01-13 10:18:49.456] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 792 ENABLE ev

ent
[2015-01-13 10:18:49.456] trDcProc commonCsc.cc:130 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:18:49.456] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 792
[2015-01-13 10:18:49.460] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin
g #####: PAR = 750
[2015-01-13 10:18:49.460] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:24, clientId:102
[2015-01-13 10:18:49.464] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:18:49.464] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:18:49.464] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 3, ccData.filterBranch 1, carrierConf.carrierId 795
[2015-01-13 10:18:49.464] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:18:49.544] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 3; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800
, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.544] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:49.544] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:18:49.544] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 795 ENABLE ev
ent
[2015-01-13 10:18:49.544] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 795 ENABLE ev
ent
[2015-01-13 10:18:49.544] trDcProc commonCsc.cc:130 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:18:49.544] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 795
[2015-01-13 10:18:49.548] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:27, clientId:102
[2015-01-13 10:18:49.552] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0

[2015-01-13 10:18:49.552] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000


1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:18:49.552] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 5, ccData.filterBranch 2, carrierConf.carrierId 798
[2015-01-13 10:18:49.552] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:18:49.560] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-34.55[-61.50 -8.00] dB)
[2015-01-13 10:18:49.560] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 5; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955800, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95580
0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF
; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.560] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:49.560] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:18:49.560] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 10:18:49.564] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 798 ENABLE ev
ent
[2015-01-13 10:18:49.564] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 798 ENABLE ev
ent
[2015-01-13 10:18:49.564] trDcProc commonCsc.cc:130 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:18:49.564] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 798
[2015-01-13 10:18:49.568] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:30, clientId:102
[2015-01-13 10:18:49.576] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:18:49.576] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:18:49.576] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 7, ccData.filterBranch 3, carrierConf.carrierId 801

[2015-01-13 10:18:49.576] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas


ed with time: 10000[ms], from 0x10097
[2015-01-13 10:18:49.576] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 7; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955800, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95580
0, state: INIT; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OF
F; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:18:49.576] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:18:49.580] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:18:49.580] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 10:18:49.580] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
2 already unblocked.
[2015-01-13 10:18:49.580] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 801 ENABLE ev
ent
[2015-01-13 10:18:49.580] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 801 ENABLE ev
ent
[2015-01-13 10:18:49.580] trDcProc commonCsc.cc:130 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:18:49.580] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 801
[2015-01-13 10:18:49.584] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = -2 (gainOffset:0 + gainMargin:-2)
[2015-01-13 10:18:49.584] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:33, clientId:102
[2015-01-13 10:18:49.700] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0x0 pa1Adj 0x4779
[2015-01-13 10:18:50.140] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.074054, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 10:18:50.268] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.42[-61.50 -8.00] dB)
[2015-01-13 10:18:50.268] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.

[2015-01-13 10:18:50.268] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced


idle prior to peak-phase calibration. dpdIrqStat: 0x04340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:18:50.268] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:18:50.296] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:18:50.296] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 54 deg
[2015-01-13 10:18:50.296] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24932
[2015-01-13 10:18:50.300] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 29333 us.
[2015-01-13 10:18:50.300] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 1 deg.
[2015-01-13 10:18:50.332] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 29999 us. IntegerDelay: 0x1d3 FracDela
y: 0x39
[2015-01-13 10:18:50.332] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fa
[2015-01-13 10:18:50.332] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2740, currentDpdDelay[1]=1712 (0.1 ns)
[2015-01-13 10:18:50.332] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:50.332] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:50.332] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:50.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:50.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)

[2015-01-13 10:18:50.336] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR


uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1712
[2015-01-13 10:18:50.336] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.336] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:18:50.352] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:50.352] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:50.352] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.352] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:50.352] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:50.352] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.352] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1712
[2015-01-13 10:18:50.356] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.356] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]

[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD


elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.368] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1712
[2015-01-13 10:18:50.372] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.372] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)

[2015-01-13 10:18:50.384] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR


uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1712
[2015-01-13 10:18:50.388] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:18:50.388] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:18:50.400] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 10:18:50.400] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 10:18:50.400] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id5
[2015-01-13 10:18:50.400] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id7
[2015-01-13 10:18:50.704] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef3765 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
23ca7 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0xb41
c991 pa1Adj 0x4779
[2015-01-13 10:18:51.708] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efc883 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
4b647 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0xb44
e142 pa1Adj 0x4779
[2015-01-13 10:18:52.720] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f02209 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8f
e8cdf C1 0x1377725 C2 0x0 C3 0x0, pa0C0Adj 0x1fda
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1
0xcc18686 pa1Adj 0x4779
[2015-01-13 10:18:53.724] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f01c5f C1 0x1a9d1c4 C2 0x0 C3 0x0, pmPa0C
0 0x904fc45 C1 0x10de2e3 C2 0x0 C3 0x0, pa0C0Adj 0
x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010,
pmPa1 0xc951da5 pa1Adj 0x4779
[2015-01-13 10:18:54.728] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef3546 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8f
fbd7d C1 0x4bf8d60 C2 0x0 C3 0x0, pa0C0Adj 0x1fda
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1
0x1125819c pa1Adj 0x4779
[2015-01-13 10:18:55.740] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eff435 C1 0x1f087e9 C2 0x0 C3 0x0, pmPa0C

0 0x902102d C1 0x59646b6 C2 0x0 C3 0x0, pa0C0Adj 0


x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010,
pmPa1 0x123aae92 pa1Adj 0x4779
[2015-01-13 10:18:56.744] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec4995 C1 0x0 C2 0x34fd4f C3 0x0, pmPa0C0
0x8ff9071 C1 0x396923d C2 0x5f4bae3 C3 0x1927f17,
pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010
C3 0x8010, pmPa1 0x19170eb7 pa1Adj 0x4779
[2015-01-13 10:18:57.748] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efb59a C1 0x74044 C2 0x1d2cc5a C3 0x0, pm
Pa0C0 0x9020c49 C1 0x2f8e69b C2 0x4646e72 C3 0x0,
pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010
C3 0x8010, pmPa1 0x146d78ec pa1Adj 0x4779
[2015-01-13 10:18:58.628] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efb1d5 C1 0x333ea6 C2 0xba1c22 C3 0x1cdb8
7, pmPa0C0 0x902f409 C1 0x2190e61 C2 0x5d4496e C3
0x21baeac, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010
C2 0x8010 C3 0x8010, pmPa1 0x17c21885 pa1Adj 0x4779
[2015-01-13 10:18:59.636] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec411d C1 0x37d81d C2 0x15e8d88 C3 0x15fe
397, pmPa0C0 0x900b27d C1 0x12e8abc C2 0x53584b6 C
3 0x32a7c04, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x80
10 C2 0x8010 C3 0x8010, pmPa1 0x1728845c pa1Adj 0x4779
[2015-01-13 10:19:00.640] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec28c2 C1 0x124da0 C2 0x2dff06 C3 0x181a3
4d, pmPa0C0 0x8ef3ab6 C1 0x2046e65 C2 0x2929ba9 C3
0x6a06dba, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x801
0 C2 0x8010 C3 0x8010, pmPa1 0x1921307c pa1Adj 0x4779
[2015-01-13 10:19:01.644] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1e328ab C1 0x2c0283 C2 0x7bc47b C3 0x15347
d, pmPa0C0 0x8c87bd7 C1 0xf461a7 C2 0x2236786 C3 0
x449c770, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010
C2 0x8010 C3 0x8010, pmPa1 0x142aac74 pa1Adj 0x4779
[2015-01-13 10:19:02.648] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efb4cd C1 0x15743b C2 0x307616 C3 0x4e7ef
9, pmPa0C0 0x8d88819 C1 0x1ef1e26 C2 0x32a53f1 C3
0x26c8231, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010
C2 0x8010 C3 0x8010, pmPa1 0x146c23c8 pa1Adj 0x4779
[2015-01-13 10:19:03.672] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f3cdef C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x8f
9ae37 C1 0x27c55ec C2 0x2f0c942 C3 0x1180912, pa0C
0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0
x8010, pmPa1 0x1353d662 pa1Adj 0x4779
[2015-01-13 10:19:04.684] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f0b4b0 C1 0xd91b9 C2 0xf8248 C3 0xf9997,
pmPa0C0 0x8feeabd C1 0x3052fb8 C2 0x281ad31 C3 0x1
7e3d93, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2
0x8010 C3 0x8010, pmPa1 0x13fa1399 pa1Adj 0x4779
[2015-01-13 10:19:05.688] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1cc072c C1 0x147034c C2 0x56596f C3 0x2c51

60, pmPa0C0 0x8f7efdb C1 0x2d50b78 C2 0x127e5ed C3


0x14f5eff, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x801
0 C2 0x8010 C3 0x8010, pmPa1 0x11cd750c pa1Adj 0x4779
[2015-01-13 10:19:06.692] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef4baf C1 0xcf13a C2 0x52cac C3 0x836b7,
pmPa0C0 0x903fe00 C1 0x254c9ea C2 0x1e90d57 C3 0x8
1fc85, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2
0x8010 C3 0x8010, pmPa1 0x112dde62 pa1Adj 0x4779
[2015-01-13 10:19:07.700] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1b4d32a C1 0x4bc06d C2 0xd0a692 C3 0x34791
8, pmPa0C0 0x8edbf8d C1 0x18e58aa C2 0x2cd581d C3
0x1528bec, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010
C2 0x8010 C3 0x8010, pmPa1 0x12383aff pa1Adj 0x4779
[2015-01-13 10:19:08.524] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efba7b C1 0x8d9306 C2 0xb0a1f6 C3 0x1617f
f6, pmPa0C0 0x902aadb C1 0x25b77ce C2 0x2a1da49 C3
0x1b45a50, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x801
0 C2 0x8010 C3 0x8010, pmPa1 0x13976c44 pa1Adj 0x4779
[2015-01-13 10:40:34.136] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:40:34.136] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0xf
[2015-01-13 10:40:34.136] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 5; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 955800, state:
ON; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800, stat
e: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: ON; dev: 8
, txFreq: 0, state: OFF;
[2015-01-13 10:40:34.136] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 798
[2015-01-13 10:40:34.140] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = 0 (gainOffset:0 + gainMargin:122)
[2015-01-13 10:40:34.140] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.140] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:30, clientId:102
[2015-01-13 10:40:34.144] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:40:34.144] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:34.144] trDcProc commonCsc.cc:498 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:40:34.144] trDcProc commonCsc.cc:498 INFO:filterBranchId 1 alread

y unblocked.
[2015-01-13 10:40:34.144] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:40:34.144] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 798 event :4
[2015-01-13 10:40:34.148] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x4, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x5cddc1b
C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2014 C2
0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x0 C3 0x8010, pmPa1 0x747657a pa1A
dj 0x47a4
[2015-01-13 10:40:34.172] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 5, txLo: 955840, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 955800, state: ON; dev: 2, txFreq: 0, state: O
FF; dev: 3, txFreq: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, tx
Freq: 955800, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800,
state: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:34.172] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:40:34.240] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:40:34.240] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:40:34.240] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x80340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:40:34.240] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:40:34.268] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:40:34.272] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 54 deg
[2015-01-13 10:40:34.272] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24859
[2015-01-13 10:40:34.272] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 30399 us.
[2015-01-13 10:40:34.272] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 1 deg.
[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 25866 us. IntegerDelay: 0x1d3 FracDela
y: 0x35

[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac


tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fc
[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2744, currentDpdDelay[1]=1715 (0.1 ns)
[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:40:34.300] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.304] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:40:34.304] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:40:34.304] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.304] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3656 + DpdDelay:1715
[2015-01-13 10:40:34.304] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.304] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:40:34.320] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:40:34.320] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:40:34.320] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor

tDelay:(80)
[2015-01-13 10:40:34.320] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:40:34.320] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:40:34.320] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.320] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3656 + DpdDelay:1715
[2015-01-13 10:40:34.324] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.324] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:40:34.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:40:34.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:40:34.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3656 [0.1ns]
[2015-01-13 10:40:34.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:40:34.336] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.336] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3656 + DpdDelay:1715

[2015-01-13 10:40:34.340] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi


lterBranch:3)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.340] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:40:34.352] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955840, (result: true)
[2015-01-13 10:40:34.416] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 798, event: 4
[2015-01-13 10:40:34.416] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31e, event :4
[2015-01-13 10:40:34.416] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:40:34.440] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:40:34.440] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(2), invalidCarrierId=(128)

DL releas

[2015-01-13 10:40:34.440] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:34.440] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:34.444] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:40:34.452] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.452] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:30, clientId:102
[2015-01-13 10:40:34.452] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:30
[2015-01-13 10:40:34.452] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:40:34.452] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x3
[2015-01-13 10:40:34.476] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 1; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 955800, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFre
q: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: O
FF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: ON; dev: 8, tx
Freq: 0, state: OFF;

[2015-01-13 10:40:34.476] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA


BLED successful for carrier 792
[2015-01-13 10:40:34.480] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.480] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:24, clientId:102
[2015-01-13 10:40:34.480] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 2
[2015-01-13 10:40:34.480] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:34.480] trDcProc commonCsc.cc:498 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:40:34.480] trDcProc commonCsc.cc:498 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:40:34.480] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 792 event :4
[2015-01-13 10:40:34.484] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 1, txLo: 955840, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 955800, state: OFF; dev: 2, txFreq: 0, state:
OFF; dev: 3, txFreq: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, t
xFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, sta
te: ON; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:34.484] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:40:34.552] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:40:34.552] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:40:34.552] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:40:34.552] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:40:34.584] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:40:34.584] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 53 deg

[2015-01-13 10:40:34.584] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib


rate_result_value: 24843
[2015-01-13 10:40:34.584] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 31599 us.
[2015-01-13 10:40:34.584] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 0 deg.
[2015-01-13 10:40:34.608] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 24533 us. IntegerDelay: 0x1d3 FracDela
y: 0x36
[2015-01-13 10:40:34.608] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
f9
[2015-01-13 10:40:34.612] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2743, currentDpdDelay[1]=1714 (0.1 ns)
[2015-01-13 10:40:34.612] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:40:34.612] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:40:34.612] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.616] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:40:34.616] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:40:34.616] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.616] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298911 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1714
[2015-01-13 10:40:34.616] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298911 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.616] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se

tTotalDelay set vldb to 264 ns


[2015-01-13 10:40:34.628] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:40:34.628] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:40:34.628] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.628] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:40:34.628] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:40:34.628] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.628] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298911 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1714
[2015-01-13 10:40:34.632] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30431[ns] = salCarrierReportedDelay:298911 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.632] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:40:34.644] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955840, (result: true)
[2015-01-13 10:40:34.696] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 792, event: 4
[2015-01-13 10:40:34.696] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 318, event :4
[2015-01-13 10:40:34.696] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:40:34.716] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:40:34.716] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(0), invalidCarrierId=(128)

DL releas

[2015-01-13 10:40:34.716] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:34.720] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:34.720] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:40:34.728] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.728] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:24, clientId:102
[2015-01-13 10:40:34.728] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:24
[2015-01-13 10:40:34.728] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA
[2015-01-13 10:40:34.728] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:34.756] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 7; Status: dpd on, state TUNED, de on, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 95
5800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF; dev: 8, txFreq
: 0, state: OFF;
[2015-01-13 10:40:34.756] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 801
[2015-01-13 10:40:34.756] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:34.756] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:33, clientId:102
[2015-01-13 10:40:34.760] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 1
[2015-01-13 10:40:34.760] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:34.760] trDcProc commonCsc.cc:498 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:40:34.760] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 801 event :4
[2015-01-13 10:40:34.764] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 7, txLo: 955840, Status: dpd on, state TUNED, de on, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 955800, state: ON; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq
: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: O

FF; dev: 8, txFreq: 0, state: OFF;


[2015-01-13 10:40:34.764] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:40:34.828] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:40:34.832] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:40:34.832] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x00340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:40:34.832] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:40:34.876] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:40:34.876] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 53 deg
[2015-01-13 10:40:34.876] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24869
[2015-01-13 10:40:34.880] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 47600 us.
[2015-01-13 10:40:34.880] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 1 deg.
[2015-01-13 10:40:34.908] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed
Delay estimation with training signal in 26266 us. IntegerDelay: 0x1d3 FracDela
y: 0x38
[2015-01-13 10:40:34.908] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fd
[2015-01-13 10:40:34.908] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2741, currentDpdDelay[1]=1713 (0.1 ns)
[2015-01-13 10:40:34.908] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:40:34.908] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:40:34.908] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela

y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor


tDelay:(80)
[2015-01-13 10:40:34.912] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:40:34.912] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:40:34.912] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:34.912] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298910 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1713
[2015-01-13 10:40:34.912] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298910 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:34.912] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:40:34.928] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955840, (result: true)
[2015-01-13 10:40:34.968] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 801, event: 4
[2015-01-13 10:40:34.968] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :4
[2015-01-13 10:40:34.968] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:40:34.988] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:40:34.988] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(3), invalidCarrierId=(128)

DL releas

[2015-01-13 10:40:34.988] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:34.988] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:34.992] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:40:35.044] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable

[2015-01-13 10:40:35.056] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal


led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:40:35.056] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:40:35.060] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:40:35.060] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:40:35.060] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:40:35.076] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:40:35.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:40:35.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:40:35.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:35.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:40:35.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:40:35.080] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:40:35.084] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1749
[2015-01-13 10:40:35.084] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:40:35.084] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 10:40:35.160] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA

Hardcopy device
[2015-01-13 10:40:35.160] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:40:35.160] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:40:35.184] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:40:35.184] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:40:35.184] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:40:35.184] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:40:35.184] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955800
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:40:35.392] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955840 (result: true)
[2015-01-13 10:40:35.392] trDcProc dlCtrl.cc:228 INFO:Carrier id 795, FilterBran
ch id 1 is added into reEnabledCarrierFBList
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnPendEvent
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:40:35.392] trDcProc dlCtrl.cc:385 INFO:1 enabled carriers, re ena
ble started!
[2015-01-13 10:40:35.392] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
0, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB

3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:35.392] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 3, ccData.filterBranch 1, carrierConf.carrierId 795
[2015-01-13 10:40:35.392] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 3; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955
800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; d
ev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:40:35.392] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 10:40:35.396] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:40:35.404] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:40:35.480] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:40:35.484] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:40:35.484] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:40:35.484] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 10:40:35.484] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-i[-42.55 -8.00], DpdPma:-i[-i -i], Pmb:-i, TorPmb:-58.15[-i -8.00] d
B)
[2015-01-13 10:40:35.484] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 10:40:35.484] trDcProc paConfig.cc:136 INFO:Not allowed to turn off
PA: 1 since there is carrier setup in carrierList
[2015-01-13 10:40:35.484] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:33, clientId:102
[2015-01-13 10:40:35.484] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:33
[2015-01-13 10:40:35.484] trDcProc tx.cc:447 INFO:TX_OFF: Start txTrace instance
: TxTracerA

[2015-01-13 10:40:35.484] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000


0, dlFbA1Cfg:0x80020001, dlFbA2Cfg:0x80040000, dlFbA3Cfg:0x80080000,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:40:35.488] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOnEvent
[2015-01-13 10:40:35.488] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:40:35.492] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:40:35.492] trxCtrlDpdProc_0 dpdController.cc:2808 INFO:Since TX-o
n the DPD has restarted 0 times.
[2015-01-13 10:40:35.492] trxCtrlDpdProc_0 dpdController.cc:2820 INFO:TX_OFF: de
v = 3; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 0, state: OFF;
dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 95
5800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 0, state: OFF;
dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0,
state: OFF;
[2015-01-13 10:40:35.492] trDcProc dlCtrl.cc:261 INFO:DlCtrl::carrierUpdateEvent
: remove the filter branch id 1 from the reEnabledCarrierFBList upon receipt of
event CR_SUBSCRIPTION_EVENT_CARRIER_DISABLED
[2015-01-13 10:40:35.492] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent DISA
BLED successful for carrier 795
[2015-01-13 10:40:35.492] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin
g #####: PAR = 0
[2015-01-13 10:40:35.492] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOffEvent. Current state is paOnPendEvent
[2015-01-13 10:40:35.492] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:40:35.496] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:40:35.496] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:27, clientId:102
[2015-01-13 10:40:35.500] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 0
[2015-01-13 10:40:35.500] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:40:35.500] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 795 event :4
[2015-01-13 10:40:35.504] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 94250
0 (kHz), compensatedFreq = 942480 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:40:35.508] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan

dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=795


[2015-01-13 10:40:35.508] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:40:35.524] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:40:35.528] trxCtrlDpdProc_0 dpdController.cc:2499 INFO:TX_RELEASE
: dev = 3, txLo: 942480, Status: dpd off, state OFF, de off, ga on; dev: 1, txFr
eq: 0, state: OFF; dev: 2, txFreq: 0, state: OFF;
dev: 3, txFreq: 955800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFre
q: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 0, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:40:35.528] trxCtrlDpdProc_0 dpdController.cc:2564 INFO:TX_RELEASE
resets TxRealSynthFreq
[2015-01-13 10:40:35.528] trDcProc warpBasedDlFreqConfig.cc:49 INFO:updateTrxCtr
lAtRelease antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 942480, (result: true)
[2015-01-13 10:40:35.540] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 795, event: 4
[2015-01-13 10:40:35.540] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :4
[2015-01-13 10:40:35.544] trDcProc warp17DlFreqHopBlock.cc:241 INFO:
eFreqHopCarrierId, fb=(1), invalidCarrierId=(128)

DL releas

[2015-01-13 10:40:35.544] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:40:35.544] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.544] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.568] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:40:35.636] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:40:35.636] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:40:35.636] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:40:35.656] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:40:35.656] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:40:35.656] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.

[2015-01-13 10:40:35.656] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N


O, dgbEnable: NO
[2015-01-13 10:40:35.660] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 3, paIdInternal: 0
[2015-01-13 10:40:35.680] timeOutSrv channelSupervision.cc:490 INFO:"IDpa2" chan
nel supervision. Read value (2) below exceptional low limit (10).
[2015-01-13 10:40:35.680] timeOutSrv channelSupervision.cc:490 INFO:"IDpa0" chan
nel supervision. Read value (2) below exceptional low limit (100).
[2015-01-13 10:40:35.788] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:35.864] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOffEvent. Current state is paOffEvent
[2015-01-13 10:40:35.864] trxCtrlDpdProc_0 dpdPaController.cc:115 INFO:TRX_CTRL_
ACT_REQ: Current state and new state is the same, no action requierd.
[2015-01-13 10:40:35.864] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:27, clientId:102
[2015-01-13 10:40:35.864] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:27
[2015-01-13 10:40:35.864] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 799
[2015-01-13 10:40:35.868] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:31, clientId:102
[2015-01-13 10:40:35.872] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 1
[2015-01-13 10:40:35.872] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.872] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.872] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=799, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.872] trDcProc rxGainComp.cc:225 INFO:rx4A2 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:40:35.872] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.876] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:31, clientId:102
[2015-01-13 10:40:35.876] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:31
[2015-01-13 10:40:35.876] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA

BLED successful for carrier 802


[2015-01-13 10:40:35.876] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:34, clientId:102
[2015-01-13 10:40:35.880] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 0
[2015-01-13 10:40:35.884] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.884] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.884] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=802, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.884] trDcProc rxGainComp.cc:225 INFO:rx4A1 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:40:35.884] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.884] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:34, clientId:102
[2015-01-13 10:40:35.884] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:34
[2015-01-13 10:40:35.884] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 793
[2015-01-13 10:40:35.884] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:25, clientId:102
[2015-01-13 10:40:35.888] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O DEPENDENT RESOURCE MISSING
[2015-01-13 10:40:35.888] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:40:35.892] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.892] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.892] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=793, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.892] trDcProc rxGainComp.cc:225 INFO:rx4A4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=910700, carrierFreqMax=910900
[2015-01-13 10:40:35.892] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.892] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:25, clientId:102
[2015-01-13 10:40:35.892] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli

entId:102 carrierId:25
[2015-01-13 10:40:35.896] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 796
[2015-01-13 10:40:35.896] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:28, clientId:102
[2015-01-13 10:40:35.900] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:40:35.900] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.900] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.900] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=796, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.900] trDcProc rxGainComp.cc:225 INFO:rx4A3 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:40:35.900] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.904] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:28, clientId:102
[2015-01-13 10:40:35.904] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:28
[2015-01-13 10:40:35.904] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 800
[2015-01-13 10:40:35.904] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:32, clientId:102
[2015-01-13 10:40:35.908] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 5
[2015-01-13 10:40:35.908] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.908] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.908] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=800, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.908] trDcProc rxGainComp.cc:225 INFO:rx4B2 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:40:35.908] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.908] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:32, clientId:102
[2015-01-13 10:40:35.908] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli

entId:102 carrierId:32
[2015-01-13 10:40:35.912] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 803
[2015-01-13 10:40:35.912] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:35, clientId:102
[2015-01-13 10:40:35.912] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 4
[2015-01-13 10:40:35.916] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.916] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.916] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=803, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.916] trDcProc rxGainComp.cc:225 INFO:rx4B1 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:40:35.916] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.916] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:35, clientId:102
[2015-01-13 10:40:35.916] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:35
[2015-01-13 10:40:35.916] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 794
[2015-01-13 10:40:35.916] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:26, clientId:102
[2015-01-13 10:40:35.920] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 7
[2015-01-13 10:40:35.920] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.920] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.920] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=794, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.920] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=910700, carrierFreqMax=910900
[2015-01-13 10:40:35.924] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.924] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:26, clientId:102
[2015-01-13 10:40:35.924] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli

entId:102 carrierId:26
[2015-01-13 10:40:35.924] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent DISA
BLED successful for carrier 797
[2015-01-13 10:40:35.924] trDcProc trDcHandler.cc:1613 INFO:Device state: BUSY/D
EACTIVATE for carrierId:29, clientId:102
[2015-01-13 10:40:35.924] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 6
[2015-01-13 10:40:35.928] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:40:35.928] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:40:35.928] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=797, carrierConf.carrierRfPort=B
[2015-01-13 10:40:35.928] trDcProc rxGainComp.cc:225 INFO:rx4B3 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:40:35.928] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:40:35.928] trDcProc trDcHandler.cc:1620 INFO:Device state: IDLE f
or carrierId:29, clientId:102
[2015-01-13 10:40:35.928] trDcProc trDcHandler.cc:1644 INFO:Carrier released cli
entId:102 carrierId:29
[2015-01-13 10:40:35.940] ledProc erciMmi.cc:221 INFO:Vii: 0x00000010
[2015-01-13 10:40:36.792] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:37.796] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:38.800] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:39.808] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:40.620] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:41.632] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,

fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:42.636] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:43.636] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:44.644] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:45.648] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:46.652] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:47.656] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:48.660] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:49.664] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:50.476] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:51.484] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:52.488] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:53.492] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,

fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:54.500] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:55.504] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:56.508] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:57.512] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:40:58.516] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0x0,
fabEnCd 0x0, fabForce 0xf, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x0 C1 0x0 C2 0x0 C3 0x0,
ncoC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa1 0x0 pa1Adj 0x47a4
[2015-01-13 10:41:19.420] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O DEPENDENT RESOURCE MISSING END
[2015-01-13 10:41:19.420] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:41:19.420] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:41:19.420] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O BUSY
[2015-01-13 10:41:19.424] ledProc erciMmi.cc:221 INFO:Vii: 0x00000004
[2015-01-13 10:41:21.372] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:41:21.376] trDcProc carrierListHandler.cc:474 INFO:CarrierListHan
dler::rxLoUpdated() CR_SUBSCRIPTION_EVENT_UL_RXLO carrierId=799
[2015-01-13 10:41:21.376] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:21.380] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:41:21.380] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(31), fb=(3), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:21.380] trDcProc warp17UlFreqHopBlock.cc:36 INFO:


ierId, id=(31), fb=(3), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:21.380] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =

true
[2015-01-13 10:41:21.380] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:21.384] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=799, carrierConf.carrierRfPort=B
[2015-01-13 10:41:21.384] trDcProc rxGainComp.cc:225 INFO:rx4A4 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:41:21.384] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:21.388] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.388] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:41:21.388] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31f tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:41:21.388] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
56 [0.1ns]
[2015-01-13 10:41:21.388] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:21.388] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:21.388] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
9 tRuReportedDelayUl:121744[0.1 ns] = tRuUl:125400 - tInternalBfnDelay:3656
[2015-01-13 10:41:21.388] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.392] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:41:21.392] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31f tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:41:21.392] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
9 tRuProcDelayUl:151660[0.1 ns] = tRuUl:125400 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.392] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
56 [0.1ns]
[2015-01-13 10:41:21.392] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1257), hardDelay:(834)

[2015-01-13 10:41:21.392] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2


81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:21.392] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:3):calc_tArpToTrp:-140144[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121744 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:21.396] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14014,filterBranch:3
[2015-01-13 10:41:21.396] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:21.396] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:21.396] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:21.396] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 3
[2015-01-13 10:41:21.396] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
[2015-01-13 10:41:21.396] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 3, value 438
[2015-01-13 10:41:21.396] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:3 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:21.396] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2075 ns
[2015-01-13 10:41:21.396] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:21.424] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 3, data 0
[2015-01-13 10:41:21.424] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 3, CPRI port 0
[2015-01-13 10:41:21.424] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:31, clientId:102
[2015-01-13 10:41:21.440] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:21.444] trDcProc ulFreqHopHandler.cc:139 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:21.444] trDcProc ulFreqHopHandler.cc:230 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:41:21.444] trDcProc warp17UlFreqHopBlock.cc:36 INFO:

UL setCarr

ierId, id=(32), fb=(7), invalidCarrierId=(128)


[2015-01-13 10:41:21.444] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:21.444] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:21.448] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=800, carrierConf.carrierRfPort=B
[2015-01-13 10:41:21.448] trDcProc rxGainComp.cc:225 INFO:rx4B4 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:41:21.448] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:21.452] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.452] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:41:21.452] trDcProc delayCommHandler.cc:312 INFO:carrier:0x320 tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:41:21.452] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
56 [0.1ns]
[2015-01-13 10:41:21.452] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1257), hardDelay:(834)
[2015-01-13 10:41:21.456] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:21.456] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:80
0 tRuReportedDelayUl:121724[0.1 ns] = tRuUl:125380 - tInternalBfnDelay:3656
[2015-01-13 10:41:21.456] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.456] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:41:21.456] trDcProc delayCommHandler.cc:312 INFO:carrier:0x320 tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:41:21.456] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:80
0 tRuProcDelayUl:151640[0.1 ns] = tRuUl:125380 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.460] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:7):calc_tArpToTrp:-139954[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121724 - tAnpUl:780 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80

[2015-01-13 10:41:21.460] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame


ters tArpToTrp [ns] = -13995,filterBranch:7
[2015-01-13 10:41:21.460] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:21.460] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:21.460] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:21.460] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 7
[2015-01-13 10:41:21.460] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 7, data 0
[2015-01-13 10:41:21.464] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 7, value 438
[2015-01-13 10:41:21.464] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:7 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:21.464] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2094 ns
[2015-01-13 10:41:21.464] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:21.492] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 7, data 0
[2015-01-13 10:41:21.492] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 7, CPRI port 0
[2015-01-13 10:41:21.492] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:32, clientId:102
[2015-01-13 10:41:21.520] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 799
[2015-01-13 10:41:21.520] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:31, clientId:102
[2015-01-13 10:41:21.524] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 800
[2015-01-13 10:41:21.524] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:32, clientId:102
[2015-01-13 10:41:21.620] bcProc lteMmiResource.cc:152 INFO: EVT: ELIB_BC_SET_VI
SUAL_INDICATION_CFM: visualized state: O BUSY END
[2015-01-13 10:41:21.620] ledProc erciMmi.cc:221 INFO:Vii: 0x00040000
[2015-01-13 10:41:21.620] ledProc erciMmi.cc:221 INFO:Vii: 0x00100000
[2015-01-13 10:41:21.868] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpA_mcr registe

rs: --------------------[2015-01-13 10:41:21.868] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0


0x0 C1 0x0 C2 0x0 C3 0x10000
[2015-01-13 10:41:21.868] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpB_mcr registe
rs: --------------------[2015-01-13 10:41:21.868] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x0 C1 0x0 C2 0x0 C3 0x10000
[2015-01-13 10:41:21.868] timeOutSrv rxTraceWarp1x.cc:149 INFO:CF_CGB_UL_TEST 0x
88
[2015-01-13 10:41:21.868] timeOutSrv rxTraceWarp1x.cc:168 INFO:CF_CPRI_UL_FB_X_C
FG C0 0x84000000, C1 0x81000000, C2 0x84000000, C3 0x91000002, C4 0x88000000, C5
0x82000000, C6 0x88000000, C7 0x92000002
[2015-01-13 10:41:21.868] timeOutSrv rxTraceWarp1x.cc:93 INFO:endTrace
[2015-01-13 10:41:21.916] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:41:21.916] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:21.916] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:21.920] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=793, carrierConf.carrierRfPort=B
[2015-01-13 10:41:21.920] trDcProc rxGainComp.cc:225 INFO:rx4A3 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=910700, carrierFreqMax=910900
[2015-01-13 10:41:21.920] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:21.924] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.924] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:41:21.924] trDcProc delayCommHandler.cc:312 INFO:carrier:0x319 tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:41:21.928] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:21.928] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:21.928] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 10:41:21.928] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79


3 tRuReportedDelayUl:121741[0.1 ns] = tRuUl:125400 - tInternalBfnDelay:3659
[2015-01-13 10:41:21.928] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.928] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:41:21.928] trDcProc delayCommHandler.cc:312 INFO:carrier:0x319 tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:41:21.928] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
3 tRuProcDelayUl:151660[0.1 ns] = tRuUl:125400 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.932] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:2):calc_tArpToTrp:-140141[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121741 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:21.932] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14014,filterBranch:2
[2015-01-13 10:41:21.932] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:21.936] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:21.936] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:21.936] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 2
[2015-01-13 10:41:21.936] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:41:21.936] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 2, value 438
[2015-01-13 10:41:21.936] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:2 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:21.936] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2075 ns
[2015-01-13 10:41:21.936] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:21.964] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 2, data 0
[2015-01-13 10:41:21.964] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 2, CPRI port 0
[2015-01-13 10:41:21.964] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:25, clientId:102

[2015-01-13 10:41:21.980] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr


eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:21.984] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:21.984] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:21.988] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=794, carrierConf.carrierRfPort=B
[2015-01-13 10:41:21.988] trDcProc rxGainComp.cc:225 INFO:rx4B3 m_vectorWidth=20
0, signalBW=200, carrierFreqMin=910700, carrierFreqMax=910900
[2015-01-13 10:41:21.988] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:21.992] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.992] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:41:21.992] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31a tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:41:21.992] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:21.992] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:21.992] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:21.992] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
4 tRuReportedDelayUl:121721[0.1 ns] = tRuUl:125380 - tInternalBfnDelay:3659
[2015-01-13 10:41:21.992] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:21.996] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:41:21.996] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31a tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:41:21.996] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
4 tRuProcDelayUl:151640[0.1 ns] = tRuUl:125380 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:21.996] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:6):calc_tArpToTrp:-139951[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:

121721 - tAnpUl:780 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela


yDiff:80
[2015-01-13 10:41:21.996] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13995,filterBranch:6
[2015-01-13 10:41:22.000] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:22.000] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:22.000] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:22.000] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 6
[2015-01-13 10:41:22.000] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:41:22.000] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 6, value 438
[2015-01-13 10:41:22.000] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:6 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:22.000] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2094 ns
[2015-01-13 10:41:22.000] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:22.028] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 6, data 0
[2015-01-13 10:41:22.028] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 6, CPRI port 0
[2015-01-13 10:41:22.028] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:26, clientId:102
[2015-01-13 10:41:22.052] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 793
[2015-01-13 10:41:22.052] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:25, clientId:102
[2015-01-13 10:41:22.056] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 794
[2015-01-13 10:41:22.056] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:26, clientId:102
[2015-01-13 10:41:22.376] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpA_mcr registe
rs: --------------------[2015-01-13 10:41:22.376] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x0 C1 0x0 C2 0x10000 C3 0x10000

[2015-01-13 10:41:22.376] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpB_mcr registe


rs: --------------------[2015-01-13 10:41:22.376] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x0 C1 0x0 C2 0x10000 C3 0x10000
[2015-01-13 10:41:22.376] timeOutSrv rxTraceWarp1x.cc:149 INFO:CF_CGB_UL_TEST 0x
cc
[2015-01-13 10:41:22.376] timeOutSrv rxTraceWarp1x.cc:168 INFO:CF_CPRI_UL_FB_X_C
FG C0 0x84000000, C1 0x81000000, C2 0x91000001, C3 0x91000002, C4 0x88000000, C5
0x82000000, C6 0x92000001, C7 0x92000002
[2015-01-13 10:41:22.376] timeOutSrv rxTraceWarp1x.cc:93 INFO:endTrace
[2015-01-13 10:41:22.580] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=1
[2015-01-13 10:41:22.584] - fault_manager.cc:1910 INFO:Set event RX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:41:22.588] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(34), fb=(1), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:22.588] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:41:22.588] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:22.592] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=802, carrierConf.carrierRfPort=B
[2015-01-13 10:41:22.592] trDcProc rxGainComp.cc:225 INFO:rx4A2 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:41:22.592] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:22.596] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.596] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:41:22.596] trDcProc delayCommHandler.cc:312 INFO:carrier:0x322 tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:41:22.596] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:22.596] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:22.596] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 10:41:22.596] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:80


2 tRuReportedDelayUl:121741[0.1 ns] = tRuUl:125400 - tInternalBfnDelay:3659
[2015-01-13 10:41:22.596] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.600] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:41:22.600] trDcProc delayCommHandler.cc:312 INFO:carrier:0x322 tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:41:22.600] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:80
2 tRuProcDelayUl:151660[0.1 ns] = tRuUl:125400 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:22.600] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:1):calc_tArpToTrp:-140141[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121741 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:22.600] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14014,filterBranch:1
[2015-01-13 10:41:22.604] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:22.604] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:22.604] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:22.604] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 1
[2015-01-13 10:41:22.604] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:41:22.604] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 1, value 438
[2015-01-13 10:41:22.604] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:1 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:22.604] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2075 ns
[2015-01-13 10:41:22.604] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:22.632] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 1, data 0
[2015-01-13 10:41:22.632] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 1, CPRI port 0
[2015-01-13 10:41:22.632] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE

ACTIVATE for carrierId:34, clientId:102


[2015-01-13 10:41:22.656] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=3
[2015-01-13 10:41:22.660] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:22.660] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(35), fb=(5), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:22.664] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:41:22.664] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:22.668] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=803, carrierConf.carrierRfPort=B
[2015-01-13 10:41:22.668] trDcProc rxGainComp.cc:225 INFO:rx4B2 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:41:22.668] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:22.668] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.672] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:41:22.672] trDcProc delayCommHandler.cc:312 INFO:carrier:0x323 tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:41:22.672] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:22.672] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:22.672] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:22.672] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:80
3 tRuReportedDelayUl:121721[0.1 ns] = tRuUl:125380 - tInternalBfnDelay:3659
[2015-01-13 10:41:22.672] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.676] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:41:22.676] trDcProc delayCommHandler.cc:312 INFO:carrier:0x323 tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380

[2015-01-13 10:41:22.676] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:80


3 tRuProcDelayUl:151640[0.1 ns] = tRuUl:125380 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:22.676] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:5):calc_tArpToTrp:-139951[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121721 - tAnpUl:780 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:22.676] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13995,filterBranch:5
[2015-01-13 10:41:22.680] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:22.680] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:22.680] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:22.680] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 5
[2015-01-13 10:41:22.680] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 5, data 0
[2015-01-13 10:41:22.680] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 5, value 438
[2015-01-13 10:41:22.680] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:5 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:22.680] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2094 ns
[2015-01-13 10:41:22.680] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:22.708] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 5, data 0
[2015-01-13 10:41:22.708] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 5, CPRI port 0
[2015-01-13 10:41:22.708] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:35, clientId:102
[2015-01-13 10:41:22.740] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 802
[2015-01-13 10:41:22.740] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:34, clientId:102
[2015-01-13 10:41:22.760] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 803
[2015-01-13 10:41:22.760] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:35, clientId:102

[2015-01-13 10:41:22.832] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C


F_CGB_CTRL data=0 slotLength=1 gammIf=0
[2015-01-13 10:41:22.836] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:22.836] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(28), fb=(0), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:22.836] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true
[2015-01-13 10:41:22.836] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:22.840] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=796, carrierConf.carrierRfPort=B
[2015-01-13 10:41:22.844] trDcProc rxGainComp.cc:225 INFO:rx4A1 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:41:22.844] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:22.844] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.848] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:41:22.848] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31c tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:41:22.848] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
58 [0.1ns]
[2015-01-13 10:41:22.848] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:22.848] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:22.848] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
6 tRuReportedDelayUl:121742[0.1 ns] = tRuUl:125400 - tInternalBfnDelay:3658
[2015-01-13 10:41:22.848] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.848] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =66
0
[2015-01-13 10:41:22.852] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31c tR
uUl:125400[0.1 ns] = tRuInternalUlDb:125400
[2015-01-13 10:41:22.852] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79

6 tRuProcDelayUl:151660[0.1 ns] = tRuUl:125400 + vldbSize/2:20260 + tRuDigitalDe


layUl:6000
[2015-01-13 10:41:22.852] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:0):calc_tArpToTrp:-140142[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121742 - tAnpUl:950 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:22.852] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -14014,filterBranch:0
[2015-01-13 10:41:22.856] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0
), tAdvDiff = (-4), sampleRateInNs = (1041.67)
[2015-01-13 10:41:22.856] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:22.856] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:22.856] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 0
[2015-01-13 10:41:22.856] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:41:22.856] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 0, value 438
[2015-01-13 10:41:22.856] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:0 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:22.856] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2075 ns
[2015-01-13 10:41:22.856] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:22.884] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 0, data 0
[2015-01-13 10:41:22.884] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 0, CPRI port 0
[2015-01-13 10:41:22.884] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:28, clientId:102
[2015-01-13 10:41:22.900] trDcProc cfpgaComUlCpriCtrlBlock.cc:82 INFO:Write to C
F_CGB_CTRL data=0 slotLength=1 gammIf=2
[2015-01-13 10:41:22.904] - fault_manager.cc:1901 INFO:Event RX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:22.908] trDcProc warp17UlFreqHopBlock.cc:36 INFO:
ierId, id=(29), fb=(4), invalidCarrierId=(128)

UL setCarr

[2015-01-13 10:41:22.908] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =


true

[2015-01-13 10:41:22.908] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte


r 1
[2015-01-13 10:41:22.912] trDcProc rxGainComp.cc:199 INFO:updateCarrierData() ca
rrierConf.carrierId=797, carrierConf.carrierRfPort=B
[2015-01-13 10:41:22.912] trDcProc rxGainComp.cc:225 INFO:rx4B1 m_vectorWidth=26
00, signalBW=200, carrierFreqMin=909500, carrierFreqMax=912100
[2015-01-13 10:41:22.912] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 942500 and vector width to 35000
[2015-01-13 10:41:22.916] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.916] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:41:22.916] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31d tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:41:22.916] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
58 [0.1ns]
[2015-01-13 10:41:22.916] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:22.916] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:22.916] trDcProc platformXUlDelayAdjust.cc:256 INFO:carrier:79
7 tRuReportedDelayUl:121722[0.1 ns] = tRuUl:125380 - tInternalBfnDelay:3658
[2015-01-13 10:41:22.916] trDcProc delayCommHandler.cc:301 INFO:tCpriUlDelayGamm
a =5330
[2015-01-13 10:41:22.920] trDcProc delayCommHandler.cc:329 INFO:delayMidFreq =56
0
[2015-01-13 10:41:22.920] trDcProc delayCommHandler.cc:312 INFO:carrier:0x31d tR
uUl:125380[0.1 ns] = tRuInternalUlDb:125380
[2015-01-13 10:41:22.920] trDcProc platformXUlDelayAdjust.cc:281 INFO:carrier:79
7 tRuProcDelayUl:151640[0.1 ns] = tRuUl:125380 + vldbSize/2:20260 + tRuDigitalDe
layUl:6000
[2015-01-13 10:41:22.920] trDcProc ulDelayEventSubscriber.cc:1317 INFO:gsm(ul fi
lterBranch:4):calc_tArpToTrp:-139952[0.1ns] = carrierFsOffset:0 + tTrptoRuInput:
0 + tRicrTrpToRuInput:2730 - carrierReportedDelay:
121722 - tAnpUl:780 - half-vldbSize:20260 - coarseDelayUlSize/2:0.0+ tExtBfnDela
yDiff:80
[2015-01-13 10:41:22.920] trDcProc ulDelayHandler.cc:56 INFO:setTotalDelayParame
ters tArpToTrp [ns] = -13995,filterBranch:4
[2015-01-13 10:41:22.924] trDcProc ulDelayHandler.cc:322 INFO:tVldbUlOffset = (0

), tAdvDiff = (-4), sampleRateInNs = (1041.67)


[2015-01-13 10:41:22.924] trDcProc platformXUlDelayAdjust.cc:313 INFO:cfdOffset
is not designed for this Platform
[2015-01-13 10:41:22.924] trDcProc platformXUlDelayAdjust.cc:236 INFO:calculated
Fbuf=438(bfnAdvanceUl=-54, sampleRateInBBClkCycles=4, smgOffset=6)
[2015-01-13 10:41:22.924] trDcProc cfpgaComUlCpriCtrlBlock.cc:135 INFO:disableLi
nk, fb 4
[2015-01-13 10:41:22.924] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 4, data 0
[2015-01-13 10:41:22.924] trDcProc cfpgaComUlCpriCtrlBlock.cc:403 INFO:setSmg, f
b 4, value 438
[2015-01-13 10:41:22.924] trDcProc platformXUlDelayAdjust.cc:208 INFO:Set Bfn Ad
vancer for filterBranch:4 = -14062 ns, fBuf=0x1b6, smgOffset=6
[2015-01-13 10:41:22.924] trDcProc platformXUlDelayAdjust.cc:124 INFO:setDelay s
et tVldbUl to 2094 ns
[2015-01-13 10:41:22.924] trDcProc ulDelayHandler.cc:101 INFO:data portNo:0 tSmg
Offset[bbclk]=6 tVldbUlOffset=0
[2015-01-13 10:41:22.952] trDcProc cfpgaComUlCpriCtrlBlock.cc:173 INFO:isLinkEna
bled fb 4, data 0
[2015-01-13 10:41:22.952] trDcProc cfpgaComUlCpriCtrlBlock.cc:114 INFO:enableLin
k, fb 4, CPRI port 0
[2015-01-13 10:41:22.952] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:29, clientId:102
[2015-01-13 10:41:22.976] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 796
[2015-01-13 10:41:22.976] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:28, clientId:102
[2015-01-13 10:41:22.980] trDcProc commonCsc.cc:275 INFO:carrierUpdateEvent ENAB
LED successful for carrier 797
[2015-01-13 10:41:22.980] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:29, clientId:102
[2015-01-13 10:41:23.540] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpA_mcr registe
rs: --------------------[2015-01-13 10:41:23.540] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x10000 C1 0x10000 C2 0x10000 C3 0x10000
[2015-01-13 10:41:23.540] timeOutSrv rxTraceWarp1x.cc:114 INFO:warpB_mcr registe
rs: --------------------[2015-01-13 10:41:23.540] timeOutSrv rxTraceWarp1x.cc:129 INFO:UL_MIX_CTRL_x: C0
0x10000 C1 0x10000 C2 0x10000 C3 0x10000
[2015-01-13 10:41:23.540] timeOutSrv rxTraceWarp1x.cc:149 INFO:CF_CGB_UL_TEST 0x

ff
[2015-01-13 10:41:23.540] timeOutSrv rxTraceWarp1x.cc:168 INFO:CF_CPRI_UL_FB_X_C
FG C0 0x94000001, C1 0x94000002, C2 0x91000001, C3 0x91000002, C4 0x98000001, C5
0x98000002, C6 0x92000001, C7 0x92000002
[2015-01-13 10:41:23.540] timeOutSrv rxTraceWarp1x.cc:93 INFO:endTrace
[2015-01-13 10:41:24.368] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:41:24.372] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:41:24.372] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:41:24.384] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:24.384] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:24.400] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:41:24.472] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:41:24.472] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:41:24.472] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:41:24.496] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:41:24.496] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:41:24.496] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:41:24.496] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:41:24.496] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 1, paIdInternal: 0
[2015-01-13 10:41:24.700] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4780 (closest actual 4780)
[2015-01-13 10:41:24.700] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:24.700] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 0
[2015-01-13 10:41:24.704] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi

ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG


smCarrier = 1
[2015-01-13 10:41:24.704] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:24.704] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 792 event :8
[2015-01-13 10:41:24.708] trDcProc rusDlFreqConfig.cc:162 INFO:frequency = 95580
0 (kHz), compensatedFreq = 955840 (kHz), rasterkHz = 80 (kHz)
[2015-01-13 10:41:24.712] trDcProc carrierListHandler.cc:453 INFO:CarrierListHan
dler::txLoUpdated() CR_SUBSCRIPTION_EVENT_DL_TXLO carrierId=792
[2015-01-13 10:41:24.716] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:24.716] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 0, rx: 0
[2015-01-13 10:41:24.716] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955800
[2015-01-13 10:41:24.716] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:24.716] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955840 (result: true)
[2015-01-13 10:41:24.744] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 792, event: 8
[2015-01-13 10:41:24.744] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 318, event :8
[2015-01-13 10:41:24.744] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:24.744] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:24.748] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 200
[2015-01-13 10:41:24.748] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 318, event :1024
[2015-01-13 10:41:24.752] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:24.752] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20

), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.752] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.752] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:41:24.752] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 318, event :128
[2015-01-13 10:41:24.756] trDcProc dlDelayEventSubscriber.cc:783 INFO:isBfnAdvan
cerSetAtFirstCarrier: ON, rfPort 1
[2015-01-13 10:41:24.756] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:24.756] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:24.756] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.756] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.756] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:24.756] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.756] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.756] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:24.756] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.760] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 10:41:24.760] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte


dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:41:24.760] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:0)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:1,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:41:24.760] trDcProc platformXDlDelayAdjust.cc:104 INFO:BFN_ADVANC
E bfnAdvanceAdjustedDelay[0] = 30436.197917
[2015-01-13 10:41:24.760] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 10:41:24.772] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:24, clientId:102
[2015-01-13 10:41:24.780] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:41:24.788] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:24.788] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 1
[2015-01-13 10:41:24.788] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 2
[2015-01-13 10:41:24.788] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:24.788] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 801 event :8
[2015-01-13 10:41:24.792] - fault_manager.cc:1910 INFO:Set event TX_SETUP_EVENT
to time: 250[ms], from 0x10097
[2015-01-13 10:41:24.792] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7
, txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:41:24.792] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:41:24.792] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 10:41:24.792] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:41:24.796] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up

second carrier
[2015-01-13 10:41:24.796] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:24.796] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955840 (result: true)
[2015-01-13 10:41:24.836] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 801, event: 8
[2015-01-13 10:41:24.836] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :8
[2015-01-13 10:41:24.836] trDcProc dlFreqHopHandler.cc:111 INFO:1 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:24.852] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:41:24.856] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:24.856] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:24.856] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:41:24.860] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :1024
[2015-01-13 10:41:24.864] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:24.864] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.864] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.864] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:41:24.864] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 321, event :128
[2015-01-13 10:41:24.864] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 10:41:24.864] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0

[2015-01-13 10:41:24.868] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36


59 [0.1ns]
[2015-01-13 10:41:24.868] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.868] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.868] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:24.868] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.868] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.868] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:41:24.872] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:1)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:41:24.872] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 10:41:24.884] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:33, clientId:102
[2015-01-13 10:41:24.892] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4780
[2015-01-13 10:41:24.900] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:24.900] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 2
[2015-01-13 10:41:24.900] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 3
[2015-01-13 10:41:24.900] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:24.900] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri

erUpdateEvent successful for carrier: 798 event :8


[2015-01-13 10:41:24.904] - fault_manager.cc:1901 INFO:Event TX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:24.904] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 10:41:24.904] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 10:41:24.904] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 10:41:24.904] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:41:24.904] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 10:41:24.904] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:24.904] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955840 (result: true)
[2015-01-13 10:41:24.960] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 798, event: 8
[2015-01-13 10:41:24.960] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31e, event :8
[2015-01-13 10:41:24.960] trDcProc dlFreqHopHandler.cc:111 INFO:2 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:24.980] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:41:24.980] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:24.980] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:24.984] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:41:24.988] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31e, event :1024
[2015-01-13 10:41:24.988] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]

[2015-01-13 10:41:24.988] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20


), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.988] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.992] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:41:24.992] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31e, event :128
[2015-01-13 10:41:24.992] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 10:41:24.992] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:24.992] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:24.992] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.992] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.996] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:24.996] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:24.996] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:24.996] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:41:24.996] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:2)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1

[2015-01-13 10:41:24.996] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe


lay set vldb to 260 ns
[2015-01-13 10:41:25.012] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:30, clientId:102
[2015-01-13 10:41:25.020] trDcProc powerClassCtrl.cc:487 INFO:totGsmCarrierPwrDb
m :4892 is higher than selected higherPowerClass:4780, maxPowerClass:4900 will b
e set
[2015-01-13 10:41:25.020] trDcProc powerClassCtrl.cc:695 INFO:salPowerClassDbm b
ranch:1 updated to 4900
[2015-01-13 10:41:25.028] - fault_manager.cc:1901 INFO:Event TX_SETUP_EVENT incr
eased with time: 250[ms], from 0x10097
[2015-01-13 10:41:25.028] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:249 INFO:Zero
fill enable
[2015-01-13 10:41:25.040] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:25.040] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:25.056] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2799, currentDpdDelay[1]=1749 (0.1 ns)
[2015-01-13 10:41:25.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:41:25.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:41:25.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.060] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.064] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1749
[2015-01-13 10:41:25.064] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1

ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT


oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:25.064] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 10:41:25.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:41:25.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:41:25.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.076] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.076] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1749
[2015-01-13 10:41:25.080] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:25.080] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 10:41:25.092] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3659 [0.1ns]
[2015-01-13 10:41:25.092] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.092] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)

[2015-01-13 10:41:25.092] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga


Delay:3659 [0.1ns]
[2015-01-13 10:41:25.092] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.092] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:25.092] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3659 + DpdDelay:1749
[2015-01-13 10:41:25.096] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:25.096] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 260 ns
[2015-01-13 10:41:25.176] trxCtrlDpdProc_0 dpdController.cc:327 INFO:Not a RUWA
Hardcopy device
[2015-01-13 10:41:25.176] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x33,txId=0
[2015-01-13 10:41:25.176] trxEvtProc eventHandler.cc:1003 INFO:Fault already sub
scribed for faultId=0x37,txId=0
[2015-01-13 10:41:25.200] trxCtrlDpdProc_0 dpdController.cc:340 INFO:ConfigData
information isWarp: 0x1, isClassic 0x0
[2015-01-13 10:41:25.200] trxCtrlDpdProc_0 dpdController.cc:2153 INFO:DGB main/p
eak swap inactive.
[2015-01-13 10:41:25.200] trxCtrlDpdProc_0 dpdController.cc:2172 INFO:DAC main/p
eak swap inactive.
[2015-01-13 10:41:25.200] trxCtrlDpdProc_0 dpdController.cc:357 INFO:dgbExist: N
O, dgbEnable: NO
[2015-01-13 10:41:25.200] trDcProc vddComp.cc:208 INFO:VddComp:tempCompInit: get
ting "/pa/table/id6" from DB, powerClassIndex: 0, paIdInternal: 0
[2015-01-13 10:41:25.408] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 1, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 0, state: OFF; dev: 2
, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0, state
: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txF
req: 0, state: OFF; dev: 8, txFreq: 0, state: OFF;

[2015-01-13 10:41:25.408] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of


configured carriers: tx: 0, rx: 0
[2015-01-13 10:41:25.408] trxCtrlDpdProc_0 dpdController.cc:3601 INFO:1 carrier
configuration, freqSetup: 955800
[2015-01-13 10:41:25.408] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:25.408] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 1, txLoFreq: 955840 (result: true)
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 5, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7
, txFreq: 0, state: OFF; dev: 8, txFreq: 0, state:
OFF;
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 1, rx: 0
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:2 carrier
configuration
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:25.412] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 5, txLoFreq: 955840 (result: true)
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 3, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 0, state: OFF; dev: 4, txFreq: 0,
state: OFF; dev: 5, txFreq: 955800, state: OFF; dev: 6, txFreq: 0, state: OFF; d
ev: 7, txFreq: 0, state: OFF; dev: 8, txFreq: 0, s
tate: OFF;
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 2, rx: 0
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:3 carrier
configuration
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up

second carrier
[2015-01-13 10:41:25.412] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:25.412] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 3, txLoFreq: 955840 (result: true)
[2015-01-13 10:41:25.416] trDcProc powerClassCtrl.cc:356 INFO:salPowerClassDbm o
n branch 1 calculated to 4900 (closest actual 4900)
[2015-01-13 10:41:25.416] trDcProc platformXDlDataInterface.cc:406 INFO:sampleFr
equency 6 , radioAccessType 0 , samplesPerBasicFrame 1
[2015-01-13 10:41:25.416] trDcProc platformXDlDataInterface.cc:410 INFO:currentI
qPosition 0 , filterBranch 3
[2015-01-13 10:41:25.416] trDcProc dlPwrClippingHandler.cc:126 INFO:configClippi
ng: carrTypeCombination = 1, noOfWcdmaCarrier = 0, noOfLteCdmaCarrier = 0, noOfG
smCarrier = 4
[2015-01-13 10:41:25.416] trDcProc dlClippingHalWarpImpl.cc:521 INFO:Does not su
pport filter
[2015-01-13 10:41:25.416] trDcProc dlPwrClippingEventSubscriber.cc:77 INFO:carri
erUpdateEvent successful for carrier: 795 event :8
[2015-01-13 10:41:25.420] trxCtrlDpdProc_0 dpdController.cc:2375 INFO:TX_SETUP:
dev = 7, carrierFrequency = 955800, txLo: 955840, Status: dpd off, state OFF, de
off, ga on; dev: 1, txFreq: 955800, state: OFF; d
ev: 2, txFreq: 0, state: OFF; dev: 3, txFreq: 955800, state: OFF; dev: 4, txFreq
: 0, state: OFF; dev: 5, txFreq: 955800, state: OFF; dev: 6, txFreq: 0, state: O
FF; dev: 7, txFreq: 0, state: OFF; dev: 8, txFreq:
0, state: OFF;
[2015-01-13 10:41:25.420] trxCtrlDpdProc_0 dpdController.cc:2391 INFO:Number of
configured carriers: tx: 3, rx: 0
[2015-01-13 10:41:25.424] trxCtrlDpdProc_0 dpdController.cc:3614 INFO:4 carrier
configuration
[2015-01-13 10:41:25.424] trxCtrlDpdProc_0 dpdDeviceSetHandler.cc:300 INFO:Tx fr
equencies: HiFreq = 955800, LoFreq = 955800
[2015-01-13 10:41:25.424] trxCtrlDpdProc_0 dpdController.cc:4510 INFO:Setting up
second carrier
[2015-01-13 10:41:25.424] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:25.424] trDcProc warpBasedDlFreqConfig.cc:35 INFO:updateTrxCtr
lAtSetup antennaBranchId: 0, trxDeviceId: 7, txLoFreq: 955840 (result: true)
[2015-01-13 10:41:25.492] trDcProc dlCarrierPowerEventSubscriber.cc:81 INFO:Carr
ierUpdateEvent successful for carrier: 795, event: 8

[2015-01-13 10:41:25.492] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd


ateEvent, carrierId (hex): 31b, event :8
[2015-01-13 10:41:25.492] trDcProc dlFreqHopHandler.cc:111 INFO:3 GSM carriers w
ith frequency hopping enabled found
[2015-01-13 10:41:25.516] trDcProc dlFreqHopHandler.cc:205 INFO:GSM carriers fre
quency hopping end for range:1 after 13 iteration
[2015-01-13 10:41:25.516] trDcProc HAL_Interface.cc:1069 INFO:warp 17. filter =
true
[2015-01-13 10:41:25.516] trDcProc filterEventSubscriber.cc:80 INFO:supportFilte
r 1
[2015-01-13 10:41:25.520] trDcProc vddComp.cc:53 INFO:VddComp::carrierUpdateEven
t: setting center frequency to 955800 and vector width to 2600
[2015-01-13 10:41:25.524] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :1024
[2015-01-13 10:41:25.524] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:25.524] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.524] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.524] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:41:25.528] trDcProc dlDelayEventSubscriber.cc:233 INFO:carrierUpd
ateEvent, carrierId (hex): 31b, event :128
[2015-01-13 10:41:25.528] trDcProc dlDelayEventSubscriber.cc:777 INFO:isBfnAdvan
cerSetAtFirstCarrier: OFF, VldbReport a28, rfPort 1
[2015-01-13 10:41:25.528] trDcProc dlDelayEventSubscriber.cc:805 INFO:isBfnAdvan
cerSetAtEveryCarrier: ON. rfPort 0
[2015-01-13 10:41:25.528] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36
59 [0.1ns]
[2015-01-13 10:41:25.528] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.528] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)

[2015-01-13 10:41:25.532] trDcProc linkHalIfCpriFpga.cc:128 INFO:comFpgaDelay:36


59 [0.1ns]
[2015-01-13 10:41:25.532] trDcProc linkHalIfCpriFpga.cc:129 INFO:serdesDelay:(20
), jbDelay:(1260), hardDelay:(834)
[2015-01-13 10:41:25.532] trDcProc linkHalIfCpriFpga.cc:130 INFO:RfsDelay:(488.2
81250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPortDelay:(
80)
[2015-01-13 10:41:25.532] trDcProc platformXDlDelayAdjust.cc:324 INFO:tRuReporte
dDelayDl:298946 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInternalBfnDe
lay:3659 + DpdDelay:1749
[2015-01-13 10:41:25.532] trDcProc dlDelayHandler.cc:106 INFO:gsm (dl filterBran
ch:3)tTrpToArp:30435[ns] = salCarrierReportedDelay:298946 + vldbSize_0_1ns/2:259
0 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpToRuInput
:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.1ns],set
BfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:1
[2015-01-13 10:41:25.532] trDcProc platformXDlDelayAdjust.cc:154 INFO:setTotalDe
lay set vldb to 260 ns
[2015-01-13 10:41:25.544] trDcProc trDcHandler.cc:643 INFO:Device state: BUSY/DE
ACTIVATE for carrierId:27, clientId:102
[2015-01-13 10:41:25.568] - fault_manager.cc:1910 INFO:Set event PA_ON_EVENT to
time: 20000[ms], from 0x10097
[2015-01-13 10:41:25.568] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnPendEvent. Current state is paOffEvent
[2015-01-13 10:41:25.568] trxCtrlDpdProc_0 dpdPaController.cc:96 INFO:new pa sta
te: TRX_PA_ON_PEND_EVENT or TRX_PA_OFF_EVENT for txBranch 0
[2015-01-13 10:41:25.572] trxCtrlDpdProc_0 paHalIf.cc:79 INFO:PA_OFF: paA SET TO
STATUS OFF
[2015-01-13 10:41:25.572] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:41:25.572] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80080001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80020001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:41:25.572] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 3, ccData.filterBranch 1, carrierConf.carrierId 801
[2015-01-13 10:41:25.572] - fault_manager.cc:1910 INFO:Set event TX_ON_EVENT to
time: 10000[ms], from 0x10097
[2015-01-13 10:41:25.576] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 3; Status: dpd off, state OFF, de off, ga on; dev: 1, txFreq: 955800, state:
OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, txFreq
: 955800, state: OFF; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800, sta

te: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF; dev:
8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.576] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:228 INFO:Tx in
put disabled
[2015-01-13 10:41:25.576] trxCtrlDpdProc_0 dpdPaController.cc:66 INFO:paCtrl cal
led with newState = paOnEvent. Current state is paOnPendEvent
[2015-01-13 10:41:25.584] trxCtrlDpdProc_0 paHalIf.cc:108 INFO:PA_ON: paA SET TO
STATUS ON
[2015-01-13 10:41:25.664] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:25.664] trxCtrlDpdProc_0 dpdController.cc:2676 INFO:m_commonCo
nf.m_isPeakBranchPresent= 1, m_commonConf.m_isWarp= 1, pTrx->hasRuwaHardcopy= 0
[2015-01-13 10:41:25.664] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:41:25.668] trxCtrlDpdProc_0 dpdStateHandler.cc:662 INFO:Training
signals. (attTuning:true dpdStart:false delEst:true)
[2015-01-13 10:41:25.668] trxCtrlDpdProc_0 dpdStateHandler.cc:664 INFO:Wait for
data. (Pma:-i[-42.55 -8.00], DpdPma:-i[-i -i], Pmb:-i, TorPmb:-58.15[-i -8.00] d
B)
[2015-01-13 10:41:25.668] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 801 ENABLE ev
ent
[2015-01-13 10:41:25.668] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 801 ENABLE ev
ent
[2015-01-13 10:41:25.668] trDcProc commonCsc.cc:130 INFO:filterBranchId 1 alread
y unblocked.
[2015-01-13 10:41:25.668] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 801
[2015-01-13 10:41:25.672] trDcProc dlPerfCtrlHandler.cc:1011 INFO:##### Reportin
g #####: PAR = 750
[2015-01-13 10:41:25.672] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:33, clientId:102
[2015-01-13 10:41:25.676] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:41:25.676] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80080001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80020001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:41:25.676] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 1, ccData.filterBranch 0, carrierConf.carrierId 792

[2015-01-13 10:41:25.676] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas


ed with time: 10000[ms], from 0x10097
[2015-01-13 10:41:25.760] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 1; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: OFF; dev: 2, txFreq: 0, state: OFF; dev: 3, tx
Freq: 955800, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 955800
, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF;
dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.760] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:41:25.760] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 10:41:25.760] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 792 ENABLE ev
ent
[2015-01-13 10:41:25.760] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 792 ENABLE ev
ent
[2015-01-13 10:41:25.760] trDcProc commonCsc.cc:130 INFO:filterBranchId 0 alread
y unblocked.
[2015-01-13 10:41:25.760] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 792
[2015-01-13 10:41:25.764] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:24, clientId:102
[2015-01-13 10:41:25.768] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:41:25.768] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80080001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80020001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:41:25.768] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 7, ccData.filterBranch 3, carrierConf.carrierId 795
[2015-01-13 10:41:25.768] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:41:25.776] trxCtrlDpdProc_0 dpdStateRamping.cc:56 INFO:Start Ramp
ing. (Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb
:-34.68[-61.50 -8.00] dB)
[2015-01-13 10:41:25.776] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 7; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955800, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95580
0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: OFF
; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.776] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in

put enabled
[2015-01-13 10:41:25.776] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:41:25.776] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 10:41:25.780] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 795 ENABLE ev
ent
[2015-01-13 10:41:25.780] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 795 ENABLE ev
ent
[2015-01-13 10:41:25.780] trDcProc commonCsc.cc:130 INFO:filterBranchId 3 alread
y unblocked.
[2015-01-13 10:41:25.780] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 795
[2015-01-13 10:41:25.784] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:27, clientId:102
[2015-01-13 10:41:25.792] trxEvtProc eventHandler.cc:1028 INFO:Event already sub
scribed,eventId=0x80, txId=0
[2015-01-13 10:41:25.792] trDcProc txTraceWarp1x.cc:172 INFO:dlFbA0Cfg:0x8001000
1, dlFbA1Cfg:0x80080001, dlFbA2Cfg:0x80040001, dlFbA3Cfg:0x80020001,dlFbB0Cfg:0x
f0000, dlFbB1Cfg:0xf0000, dlFbB2Cfg:0xf0000, dlFbB
3Cfg:0xf0000, cgbDlTest:0x0
[2015-01-13 10:41:25.792] trDcProc tx.cc:388 INFO:carrierUpdateEvent: ENABLED cc
Data.deviceId 5, ccData.filterBranch 2, carrierConf.carrierId 798
[2015-01-13 10:41:25.792] - fault_manager.cc:1901 INFO:Event TX_ON_EVENT increas
ed with time: 10000[ms], from 0x10097
[2015-01-13 10:41:25.792] trxCtrlDpdProc_0 dpdController.cc:2592 INFO:TX_ON: dev
= 5; Status: dpd off, state RAMPING, de off, ga on; dev: 1, txFreq: 955800, sta
te: INIT; dev: 2, txFreq: 0, state: OFF; dev: 3, t
xFreq: 955800, state: INIT; dev: 4, txFreq: 0, state: OFF; dev: 5, txFreq: 95580
0, state: OFF; dev: 6, txFreq: 0, state: OFF; dev: 7, txFreq: 955800, state: INI
T; dev: 8, txFreq: 0, state: OFF;
[2015-01-13 10:41:25.792] trxCtrlDpdProc_0 trxCtrl11HandlerPf4.cc:233 INFO:Tx in
put enabled
[2015-01-13 10:41:25.796] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
0 already unblocked.
[2015-01-13 10:41:25.796] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
3 already unblocked.
[2015-01-13 10:41:25.796] trxCtrlDpdProc_0 commonCsc.cc:498 INFO:filterBranchId
1 already unblocked.
[2015-01-13 10:41:25.796] trDcProc internalGammaCtrl.cc:371 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpA_mcr, reason: Carrier 798 ENABLE ev

ent
[2015-01-13 10:41:25.796] trDcProc internalGammaCtrl.cc:377 INFO:internalGammaCt
rl: Requesting BFN resynchronization on warpB_mcr, reason: Carrier 798 ENABLE ev
ent
[2015-01-13 10:41:25.796] trDcProc commonCsc.cc:130 INFO:filterBranchId 2 alread
y unblocked.
[2015-01-13 10:41:25.796] trDcProc commonCsc.cc:254 INFO:carrierUpdateEvent ENAB
LED successful for carrier 798
[2015-01-13 10:41:25.800] trDcProc dlPerfCtrlHandler.cc:1004 INFO:##### Reportin
g #####: GAIN_OFFSET = -2 (gainOffset:0 + gainMargin:-2)
[2015-01-13 10:41:25.800] trDcProc trDcHandler.cc:663 INFO:Device state: BUSY/AC
TIVATE for carrierId:30, clientId:102
[2015-01-13 10:41:25.804] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0x0 pa1Adj 0x4779
[2015-01-13 10:41:26.372] trxCtrlDpdProc_0 dpdStateTuning.cc:68 INFO:gainAdjust:
0.120554, gainAdjustValue: true, maxDiffAddr: 1, diffAddrLimit: 0, gainAdjustme
ntLoopChanged: 0
[2015-01-13 10:41:26.500] trxCtrlDpdProc_0 dpdStateTuning.cc:152 INFO:Start DPD.
(Pma:-26.50[-42.55 -8.00], DpdPma:-29.50[-30.00 -29.00], Pmb:-26.50, TorPmb:-26
.48[-61.50 -8.00] dB)
[2015-01-13 10:41:26.500] trxCtrlDpdProc_0 dpdController.cc:1605 INFO:boardFreq
= 955840, mgnOffsetPeakDig = 0, dpdIqGiPeakOld = 0x7197C900, dpdIqGiPeakNew = 0x
7197C900, dpdIqGqPeakOld = 0x72913B00, dpdIqGqPeak
New = 0x72913B00.
[2015-01-13 10:41:26.500] trxCtrlDpdProc_0 dpdController.cc:3757 INFO:DPD forced
idle prior to peak-phase calibration. dpdIrqStat: 0x04340008, dpdStat: 0x001400
00, dpdStatusPd0: 0x00000000, dpdStatusPd1: 0x0000
0000
[2015-01-13 10:41:26.500] trxCtrlDpdProc_0 dpdController.cc:3785 INFO:Using stan
dard peak-phase calibration algorithm
[2015-01-13 10:41:26.528] trxCtrlDpdProc_0 dpdController.cc:3846 INFO:Peak_calib
rate_result_phase status ok: step 0: 54 deg
[2015-01-13 10:41:26.528] trxCtrlDpdProc_0 dpdController.cc:3915 INFO:Peak_calib
rate_result_phase: 54 deg
[2015-01-13 10:41:26.528] trxCtrlDpdProc_0 dpdController.cc:3916 INFO:Peak_calib
rate_result_value: 24588
[2015-01-13 10:41:26.528] trxCtrlDpdProc_0 dpdController.cc:4017 INFO:Performed
peak phase calibration in 28799 us.
[2015-01-13 10:41:26.528] trxCtrlDpdProc_0 dpdController.cc:4018 INFO:Peak-phase
correction versus flash: 2 deg.
[2015-01-13 10:41:26.556] trxCtrlDpdProc_0 dpdController.cc:4260 INFO:Performed

Delay estimation with training signal in 24400 us. IntegerDelay: 0x1d3 FracDela
y: 0x37
[2015-01-13 10:41:26.556] trxCtrlDpdProc_0 dpdController.cc:4293 INFO:First frac
tional delay ok. dpdIrqStat: 0x00140000, dpdStat = 0x00140000, dpdMode = 0x08410
610, dpdTxSurMaxAddr = 0x00000749, dpdDelEstFracDe
ltaInt = 0x00000000, dpdDelEstIntCorr = 0x00000000, dpdDelEstFracCorr = 0x00001f
fb
[2015-01-13 10:41:26.556] trxCtrlDpdProc_0 dlDpdDelayCompHandler.cc:84 INFO:DPD
delay update, dpdDelay = 2742, currentDpdDelay[1]=1713 (0.1 ns)
[2015-01-13 10:41:26.560] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:41:26.560] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:26.560] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.560] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:41:26.560] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:26.560] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.564] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3658 + DpdDelay:1713
[2015-01-13 10:41:26.564] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:0)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.564] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:41:26.576] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:41:26.576] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)

[2015-01-13 10:41:26.576] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela


y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.576] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:41:26.576] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:26.576] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.576] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3658 + DpdDelay:1713
[2015-01-13 10:41:26.580] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:3)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.580] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:41:26.592] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:41:26.592] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:26.592] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.592] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:41:26.592] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:26.592] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.592] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter

nalBfnDelay:3658 + DpdDelay:1713
[2015-01-13 10:41:26.596] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:2)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.596] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:41:26.608] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:41:26.608] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:26.608] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.608] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:128 INFO:comFpga
Delay:3658 [0.1ns]
[2015-01-13 10:41:26.608] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:129 INFO:serdesD
elay:(20), jbDelay:(1259), hardDelay:(834)
[2015-01-13 10:41:26.608] trxCtrlDpdProc_0 linkHalIfCpriFpga.cc:130 INFO:RfsDela
y:(488.281250 + 162.760417), BfnDelay:(813.802083 + 0.000000), tBfnFabToCalibPor
tDelay:(80)
[2015-01-13 10:41:26.608] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:324 INFO:tR
uReportedDelayDl:298909 = tRuInternalDlDb:292940 + tDlFreqCompDelay:598 + tInter
nalBfnDelay:3658 + DpdDelay:1713
[2015-01-13 10:41:26.612] trxCtrlDpdProc_0 dlDelayHandler.cc:106 INFO:gsm (dl fi
lterBranch:1)tTrpToArp:30431[ns] = salCarrierReportedDelay:298909 + vldbSize_0_1
ns/2:2590 + tAnpDl:0 + tTRpToRuInput:0 + tRicrTRpT
oRuInput:2730 + tExtBFNDelayDiff:80 + tFrameOffset:0.00,tFrameOffsetFrac:0.00[0.
1ns],setBfnAdvancerAtFirstCarrier:0,setBfnAdvanceAtEveryCarrier:0
[2015-01-13 10:41:26.612] trxCtrlDpdProc_0 platformXDlDelayAdjust.cc:154 INFO:se
tTotalDelay set vldb to 264 ns
[2015-01-13 10:41:26.624] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id1
[2015-01-13 10:41:26.624] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id3
[2015-01-13 10:41:26.624] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I
ND sent for device id5

[2015-01-13 10:41:26.624] trxCtrlDpdProc_0 dpdController.cc:5585 INFO:RU_TX_ON_I


ND sent for device id7
[2015-01-13 10:41:26.808] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x0 C1 0x0
C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2014 C2 0x201
4 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0x0 pa1Adj 0x4779
[2015-01-13 10:41:27.812] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x203ad80 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
25b91 C1 0x0 C2 0x0 C3 0x0, pa0C0Adj 0x1fda C1 0x2
014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1 0xb41
f0a1 pa1Adj 0x4779
[2015-01-13 10:41:28.816] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef3ec0 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
2db63 C1 0x0 C2 0x0 C3 0x16912f4, pa0C0Adj 0x1fda
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1
0xd05aecf pa1Adj 0x4779
[2015-01-13 10:41:29.820] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec2906 C1 0x0 C2 0x0 C3 0x0, pmPa0C0 0x90
2c5e4 C1 0x0 C2 0x0 C3 0x10e18bb, pa0C0Adj 0x1fda
C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010, pmPa1
0xc933ebd pa1Adj 0x4779
[2015-01-13 10:41:30.824] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ecb7bf C1 0x0 C2 0x0 C3 0x1e8f61b, pmPa0C
0 0x904fb68 C1 0x0 C2 0x0 C3 0x21b69e9, pa0C0Adj 0
x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0x8010,
pmPa1 0xde48f84 pa1Adj 0x4779
[2015-01-13 10:41:35.624] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1f58fb8 C1 0x0 C2 0x0 C3 0x1f57a99, pmPa0C
0 0x9010b3a C1 0x0 C2 0x3da3445 C3 0x71a4504, pa0C
0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C3 0
x8010, pmPa1 0x18e11e0c pa1Adj 0x4779
[2015-01-13 10:41:36.628] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eae9b7 C1 0x0 C2 0x8c49f4 C3 0x37c200, pm
Pa0C0 0x8ff6007 C1 0x0 C2 0x56fafac C3 0x36fce0c,
pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010
C3 0x8010, pmPa1 0x16473c95 pa1Adj 0x4779
[2015-01-13 10:41:37.632] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef92e0 C1 0x1ecdc51 C2 0x1ef6768 C3 0xee6
996, pmPa0C0 0x902dcbd C1 0x56f78b2 C2 0x5100b20 C
3 0x1d6255d, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x80
10 C2 0x8010 C3 0x8010, pmPa1 0x1a9a7835 pa1Adj 0x4779
[2015-01-13 10:41:38.636] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec7495 C1 0x1b74ea4 C2 0xaeb4df C3 0x1b6b
3a8, pmPa0C0 0x9004a5d C1 0x921af0e C2 0x10c81ce C
3 0x20e5e51, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x80
10 C2 0x8010 C3 0x8010, pmPa1 0x1a74586b pa1Adj 0x4779
[2015-01-13 10:41:39.640] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efbd22 C1 0x1f0cadd C2 0x126d12e C3 0xc55
827, pmPa0C0 0x9037c88 C1 0x668ead3 C2 0x2033896 C

3 0x1e51322, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x80


10 C2 0x8010 C3 0x8010, pmPa1 0x181e6eda pa1Adj 0x4779
[2015-01-13 10:41:40.644] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efb323 C1 0x69fe2b C2 0x2a3ca0 C3 0x10a4f
e2, pmPa0C0 0x9010df1 C1 0x252ebed C2 0x12c5368 C3
0x246867e, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x801
0 C2 0x8010 C3 0x8010, pmPa1 0x127015d1 pa1Adj 0x4779
[2015-01-13 10:41:41.648] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef9c78 C1 0xc53acf C2 0xad11b4 C3 0xa7708
f, pmPa0C0 0x9039cb8 C1 0x1f78984 C2 0xd864b7 C3 0
x40d2301, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010
C2 0x8010 C3 0x8010, pmPa1 0x13d0acb7 pa1Adj 0x4779
[2015-01-13 10:41:42.652] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ed048d C1 0x37135b C2 0x0 C3 0x127d65, pm
Pa0C0 0x901a440 C1 0x1844d12 C2 0x14ff64a C3 0x224
587e, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0
x8010 C3 0x8010, pmPa1 0x1171ea10 pa1Adj 0x4779
[2015-01-13 10:41:43.656] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1effbdd C1 0x726d52 C2 0x0 C3 0xaaaec0, pm
Pa0C0 0x903479d C1 0x1346bd1 C2 0x2b9ed5c C3 0x3ee
00d9, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0
x8010 C3 0x8010, pmPa1 0x150c9bc0 pa1Adj 0x4779
[2015-01-13 10:41:44.660] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efce11 C1 0x0 C2 0x1174fa3 C3 0x224724, p
mPa0C0 0x8ff09a1 C1 0x7c94d3 C2 0x367dd5c C3 0x476
cb6b, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0
x8010 C3 0x8010, pmPa1 0x15a579cf pa1Adj 0x4779
[2015-01-13 10:41:45.468] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ef7437 C1 0x0 C2 0x0 C3 0x33b998, pmPa0C0
0x903b2f9 C1 0xbc6e41 C2 0x2518f71 C3 0x1415d3f,
pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010
C3 0x8010, pmPa1 0x109ebe56 pa1Adj 0x4779
[2015-01-13 10:41:46.476] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1ec34e0 C1 0x0 C2 0x0 C3 0x4c10bc, pmPa0C0
0x8ffcf78 C1 0x6b87e3 C2 0x6b740f C3 0x11070d6, p
a0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8010 C
3 0x8010, pmPa1 0xd9e25e0 pa1Adj 0x4779
[2015-01-13 10:41:47.476] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1eee05b C1 0x3dd643 C2 0x3dff03 C3 0x0, pm
Pa0C0 0x9034a97 C1 0xfbaef4 C2 0x6b86a5 C3 0x13faa
dd, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x8
010 C3 0x8010, pmPa1 0xe8f4ceb pa1Adj 0x4779
[2015-01-13 10:41:48.480] timeOutSrv txTraceWarp1x.cc:141 INFO:warpA:fabEn 0xf,
fabEnCd 0xf, fabForce 0x0, mplPwrC0 0x1efd09e C1 0x0 C2 0x2c4b0d C3 0x1177753, p
mPa0C0 0x90066b3 C1 0x7c82d4 C2 0x2abcbc C3 0x3903
8b7, pa0C0Adj 0x1fda C1 0x2014 C2 0x2014 C3 0x2014, ncoC0 0x8010 C1 0x8010 C2 0x
8010 C3 0x8010, pmPa1 0x1082b502 pa1Adj 0x4779
[2015-01-13 11:53:00.328] antpServerProc_ ruAntpDevice.cc:811 INFO:setVoltage 10
3 1

[2015-01-13 11:53:00.328] antpServerProc_ voltagePowerCtrl.cc:357 INFO:antSetVol


tage client=103 voltage=170
[2015-01-13 11:53:00.328] antpServerProc_ voltagePowerCtrl.cc:364 INFO:Setting r
eserved voltage
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:71 INFO:antSetPowe
r ClientId 103
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:101 INFO:Port A au
x power on
[2015-01-13 11:53:00.332] antpServerProc_ currentSv.cc:251 INFO:Current Limits(l
ow,high): [50, 1600] on antenna port A
[2015-01-13 11:53:00.332] antpServerProc_ ANUSupervisionService.cc:900 INFO:AnpT
ot ON and Turned it On
[2015-01-13 11:53:00.332] antpServerProc_ ANUSupervisionService.cc:904 INFO:AnpT
ot ON
[2015-01-13 11:53:00.332] antpServerProc_ lrciAntsysImpl.cc:327 INFO:LRCI: Port
A set power on
[2015-01-13 11:53:00.332] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxSupplyPow
[2015-01-13 11:53:00.332] antpServerProc_ ANUSupervisionService.cc:531 INFO:ANUS
upervisionService::postSetAntennaPower attempt to set antenna power on port A to
ON
[2015-01-13 11:53:00.332] antpServerProc_ ruAntp.cc:530 INFO:Volt Req errorCode=
0
[2015-01-13 11:53:00.332] antpServerProc_ ruAntpDevice.cc:1052 INFO:Current Meas
urement started
[2015-01-13 11:53:00.332] antpServerProc_ ruAntpDevice.cc:811 INFO:setVoltage 10
3 1
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:357 INFO:antSetVol
tage client=103 voltage=170
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:374 INFO:Voltage n
ot set but OK. (Current Voltage Level or 0==released)
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:71 INFO:antSetPowe
r ClientId 103
[2015-01-13 11:53:00.332] antpServerProc_ voltagePowerCtrl.cc:101 INFO:Port B au
x power on
[2015-01-13 11:53:00.332] antpServerProc_ currentSv.cc:251 INFO:Current Limits(l
ow,high): [50, 1600] on antenna port B
[2015-01-13 11:53:00.332] antpServerProc_ ANUSupervisionService.cc:904 INFO:AnpT
ot ON

[2015-01-13 11:53:00.332] antpServerProc_ lrciAntsysImpl.cc:327 INFO:LRCI: Port


B set power on
[2015-01-13 11:53:00.336] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxSupplyPow
[2015-01-13 11:53:00.336] antpServerProc_ ANUSupervisionService.cc:531 INFO:ANUS
upervisionService::postSetAntennaPower attempt to set antenna power on port B to
ON
[2015-01-13 11:53:00.336] antpServerProc_ ruAntp.cc:530 INFO:Volt Req errorCode=
0
[2015-01-13 11:53:00.336] antpServerProc_ ruAntpDevice.cc:1052 INFO:Current Meas
urement started
[2015-01-13 11:53:03.416] currentSvProc currentSv.cc:175 INFO:Current (0) too lo
w detected on port A
[2015-01-13 11:53:03.416] currentSvProc currentSv.cc:175 INFO:Current (0) too lo
w detected on port B
[2015-01-13 11:53:06.452] antpServerProc_ ruAntpDevice.cc:1078 INFO:Current Meas
urement stopped
[2015-01-13 11:53:06.452] antpServerProc_ ruAntpDevice.cc:811 INFO:setVoltage 10
3 0
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:71 INFO:antSetPowe
r ClientId 103
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:101 INFO:Port A au
x power off
[2015-01-13 11:53:06.452] antpServerProc_ lrciAntsysImpl.cc:331 INFO:LRCI: Port
A set power off
[2015-01-13 11:53:06.452] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxNoResistanceSvPow
[2015-01-13 11:53:06.452] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxNoSupplyPow
[2015-01-13 11:53:06.452] antpServerProc_ ANUSupervisionService.cc:531 INFO:ANUS
upervisionService::postSetAntennaPower attempt to set antenna power on port A to
OFF
[2015-01-13 11:53:06.452] antpServerProc_ ANUSupervisionService.cc:953 INFO:AnpT
ot OFF
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:357 INFO:antSetVol
tage client=103 voltage=0
[2015-01-13 11:53:06.452] antpServerProc_ voltagePowerCtrl.cc:374 INFO:Voltage n
ot set but OK. (Current Voltage Level or 0==released)
[2015-01-13 11:53:06.452] antpServerProc_ ruAntp.cc:530 INFO:Volt Req errorCode=
0

[2015-01-13 11:53:06.456] antpServerProc_ ruAntpDevice.cc:1078 INFO:Current Meas


urement stopped
[2015-01-13 11:53:06.456] antpServerProc_ ruAntpDevice.cc:811 INFO:setVoltage 10
3 0
[2015-01-13 11:53:06.456] antpServerProc_ voltagePowerCtrl.cc:71 INFO:antSetPowe
r ClientId 103
[2015-01-13 11:53:06.456] antpServerProc_ voltagePowerCtrl.cc:101 INFO:Port B au
x power off
[2015-01-13 11:53:06.456] antpServerProc_ lrciAntsysImpl.cc:331 INFO:LRCI: Port
B set power off
[2015-01-13 11:53:06.456] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxNoResistanceSvPow
[2015-01-13 11:53:06.456] antpServerProc_ antenna.cc:1244 INFO:AuxPowerState cha
nged to: eAuxNoSupplyPow
[2015-01-13 11:53:06.456] antpServerProc_ ANUSupervisionService.cc:531 INFO:ANUS
upervisionService::postSetAntennaPower attempt to set antenna power on port B to
OFF
[2015-01-13 11:53:06.456] antpServerProc_ ANUSupervisionService.cc:946 INFO:AnpT
ot OFF and Turned it OFF
[2015-01-13 11:53:06.456] antpServerProc_ ANUSupervisionService.cc:953 INFO:AnpT
ot OFF
[2015-01-13 11:53:06.456] antpServerProc_ voltagePowerCtrl.cc:357 INFO:antSetVol
tage client=103 voltage=0
[2015-01-13 11:53:06.456] antpServerProc_ voltagePowerCtrl.cc:374 INFO:Voltage n
ot set but OK. (Current Voltage Level or 0==released)
[2015-01-13 11:53:06.456] antpServerProc_ ruAntp.cc:530 INFO:Volt Req errorCode=
0
[2015-01-13 11:53:06.912] trDcProc dynamicRfSignalCapabilityImpl.cc:121 INFO:noT
xPorts= 1, m_rfSignalId.ordinal()= 1
[2015-01-13 11:53:06.912] trDcProc trDcCapabilities.cc:352 INFO:ABN: No amountFr
eePower for port 1 , capabilityNoTx= 1

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