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D
D
D
D
D
D
D
D
D
SN54HC164 . . . J OR W PACKAGE
SN74HC164 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
A
B
QA
QB
QC
QD
GND
description/ordering information
14
13
12
11
10
VCC
QH
QG
QF
QE
CLR
CLK
SN54HC164 . . . FK PACKAGE
(TOP VIEW)
B
A
NC
VCC
QH
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
QG
NC
QF
NC
QE
QD
GND
NC
CLK
CLR
QA
NC
QB
NC
QC
NC No internal connection
ORDERING INFORMATION
PACKAGE
TA
PDIP N
SN74HC164N
Tube of 50
SN74HC164D
Reel of 2500
SN74HC164DR
Reel of 250
SN74HC164DT
Reel of 2000
SN74HC164NSR
Tube of 90
SN74HC164PW
Reel of 2000
SN74HC164PWR
Reel of 250
SN74HC164PWT
CDIP J
Tube of 25
SNJ54HC164J
SNJ54HC164J
CFP W
Tube of 150
SNJ54HC164W
SNJ54HC164W
LCCC FK
Tube of 55
SNJ54HC164FK
SOP NS
TSSOP PW
55C
125C
55 C to 125
C
TOP-SIDE
MARKING
Tube of 25
SOIC D
40 C to 85
40C
85C
C
ORDERABLE
PART NUMBER
SN74HC164N
HC164
HC164
HC164
SNJ54HC164FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115D DECEMBER 1982 REVISED AUGUST 2003
FUNCTION TABLE
OUTPUTS
INPUTS
CLR
CLK
QA
QB . . . QH
QA0
QB0
QH0
QAn
QGn
QAn
QGn
QAn
QGn
A
B
CLR
1
2
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
9
3
QA
QB
QC
QD
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
C1
1D
R
10
QE
11
QF
12
QG
13
QH
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115D DECEMBER 1982 REVISED AUGUST 2003
Serial Inputs
CLR
A
B
CLK
QA
QB
Outputs
QC
QD
QE
QF
QG
QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, JA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115D DECEMBER 1982 REVISED AUGUST 2003
Supply voltage
VIH
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
MAX
NOM
MAX
1.5
3.15
3.15
4.2
4.2
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
VCC = 2 V
VCC = 4.5 V
MIN
1.5
Output voltage
t/v
t/ v
NOM
VCC = 4.5 V
VCC = 6 V
Input voltage
SN74HC164
MIN
VCC
VCC
1000
1000
500
500
V
V
V
ns
VCC = 6 V
400
400
TA
Operating free-air temperature
55
125
40
85
C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
TEST CONDITIONS
IOH = 20 A
A
VOH
VI = VIH or VIL
IOH = 4 mA
IOH = 5.2 mA
VOL
II
ICC
Ci
MIN
TA = 25C
TYP
MAX
SN54HC164
MIN
MAX
SN74HC164
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
MAX
UNIT
5.34
2V
0.002
0.1
0.1
0.1
IOL = 20 A
A
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
IOL = 4 mA
IOL = 5.2 mA
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
0.1
100
1000
1000
nA
160
80
10
10
10
pF
VI = VIH or VIL
VI = VCC or 0
VI = VCC or 0,
VCC
IO = 0
6V
2 V to 6 V
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115D DECEMBER 1982 REVISED AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
CLR low
tw
Pulse duration
CLK high or low
Data
tsu
th
TA = 25C
MIN
MAX
SN54HC164
MIN
MAX
SN74HC164
MIN
MAX
2V
4.2
4.5 V
31
21
25
6V
36
25
28
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
80
120
100
4.5 V
16
24
20
6V
14
20
18
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
4.5 V
6V
UNIT
MHz
ns
ns
ns
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPHL
tpd
CLR
CLK
Any Q
Any Q
tt
VCC
TA = 25C
MIN
TYP
MAX
SN54HC164
MIN
MAX
SN74HC164
MIN
2V
10
4.2
4.5 V
31
54
21
25
6V
36
62
25
28
MAX
UNIT
MHz
2V
140
205
295
255
4.5 V
28
41
59
51
6V
24
35
51
46
2V
115
175
265
220
4.5 V
23
35
53
44
6V
20
30
45
38
2V
38
75
110
95
4.5 V
15
22
19
6V
13
19
16
ns
ns
TEST CONDITIONS
TYP
UNIT
No load
135
pF
SN54HC164, SN74HC164
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS115D DECEMBER 1982 REVISED AUGUST 2003
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
90%
90%
tr
th
90%
50%
10%
tPHL
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
tPLH
50%
10%
tf
tf
VOH
50%
10%
VOL
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
MECHANICAL DATA
MCFP002A JANUARY 1995 REVISED FEBRUARY 2002
W (R-GDFP-F14)
0.260 (6,60)
0.235 (5,97)
0.045 (1,14)
0.026 (0,66)
0.008 (0,20)
0.004 (0,10)
0.080 (2,03)
0.045 (1,14)
0.019 (0,48)
0.015 (0,38)
14
0.050 (1,27)
0.390 (9,91)
0.335 (8,51)
0.005 (0,13) MIN
4 Places
8
0.360 (9,14)
0.250 (6,35)
0.360 (9,14)
0.250 (6,35)
4040180-2 / C 02/02
NOTES: A.
B.
C.
D.
E.
MECHANICAL DATA
MLCC006B OCTOBER 1996
FK (S-CQCC-N**)
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
22
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
26
27
28
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
MECHANICAL
MPDI002C JANUARY 1995 REVISED DECEMBER 20002
N (R-PDIP-T**)
16 PINS SHOWN
PINS **
14
16
18
20
A MAX
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
1.060
(26,92)
A MIN
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
MS-100
VARIATION
AA
BB
AC
DIM
A
16
0.260 (6,60)
0.240 (6,10)
AD
8
0.070 (1,78)
0.045 (1,14)
0.045 (1,14)
0.030 (0,76)
0.325 (8,26)
0.300 (7,62)
0.015 (0,38)
Gauge Plane
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M
D
4040049/E 12/2002
MECHANICAL DATA
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
0.010 (0,25)
0 8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
7
0 8
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
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