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http://analog.ece.utk.edu/ece491.htm
Final Project
Designing a 4-bit Counter or Flip-Flop
The final design project will require you to design a moderately complex VLSI design
circuit. For this class we choose to design a Flip-flop for the Undergrad student and a 4bit counter for Graduated Student. This project will be done individually.
Presentation will include all the simulation results. Rise time, Fall time,
Propagation delay, plot of delay vs Load will also include in your presentation slide.
SAMPLE REPORT:
I.
Objective:
The objective of this project is to design a 4-bit counter and implement it with the help of
Cadence (custom IC design tool) following necessary steps and rules dependent on
selected process technology.
Synchronous counter is considered as one of the most popular and widely used
counter.
Since same clock signal is given to all the fundamental blocks (Flip Flop) of the
counter, no interrupt can occur in the middle of a state transition.
The output level of the counter is free from glitch, which ensures us about the
reliability of digital logic control.
We can easily implement set and reset logic of the counter by using set and reset
mode of JK flip-flop.
Cadence is one of the most popular, efficient and commercial custom IC design tool.
There are some sequential steps that we have to follow strictly for fruitful IC design.
These steps are mentioned belowDesign Specification
Schematic Capture
Create Symbol
Simulation
Layout
Extraction
V.
JK Filp Flop:
Master salve edge triggered flip flop is more preferable in IC design due to its reliable
output. The characteristics table of JK flip-flop is:
Table 1: Truth table of JK flip flop
J
0
0
1
1
K
0
1
0
1
Qn+1
Qn
0
1
Qn
Schematic:
Count
10
11
12
13
14
15
According to the truth table, it can be noted that A must change state with every input
clock pulse. This can be easily implemented by using a T flip-flop. But even with JK flipflops, all we need to do here is to connect both the J and K inputs of this flip-flop to logic
1 in order to get the correct activity. B must change state only when output A is a logic 1,
but not when A is a logic 0. So, if we connect output A to the J and K inputs of flip-flop
B, we will see output B behaving correctly. Again, C must change state only when both A
and B are logic 1. We can't use only output B as the control for flip-flop C; that will allow
C to change state when the counter is in state 2, causing it to switch directly from a count
of 2 to a count of 7, and again from a count of 10 to a count of 15 not a good way to
count. Therefore we will need a two-input AND gate at the inputs to flip-flop C. The state
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of D will change only when the logic level of A, B and C are high. So we can use same
method for D flip flop.
An additional pin for serial carry look ahead is implemented for cascading purpose.
Sometimes we may need to construct a 8bit synchronous counter by using two 4 bit
counter. Then we will need the serial carry bit generated from previous counter.
Schematic:
Layout:
The layout of the counter has been tried to make as small as possible using few
interconnection. Four flip flops are placed at four corners and 3 and gates are placed in
the middle. I have used up to metal2 layer for interconnection. The layout would have
been more compact if I would use metal3 layer. The final size of the layout is 114.45 m
by 83 m, which can be considered as a usual size of a 4bit counter.
Figure 12: Waveform of counter at 10 MHz clock with 4pf load capacitance
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Delay (ps)
D
329.41 221.22 190.29 197.69 220.72 157.27 133.91 136.95 631.71 522.66 489.98 495.63
10
323.83 217.49 189.45 196.48 217.96 155.65 132.94 134.57 628.58 522.96 489.23 495.61
50
329.48 218.41 189.13 195.65 225.56 155.08 132.89 134.21 631.74 522.64 489.97 495.29
100
324.49 218.44 189.33 195.67 218.83 154.93 133.04 134.73 628.55 523.03 488.86 495.68
Delay (ns)
3.16
3.06
3.03
3.05
3.42
3.34
3.32
3.31
4.84
4.7
4.69
4.72
5.85
5.72
5.73
5.75
6.57
6.46
6.51
6.51
8.92
8.79
8.76
8.77
8.53
8.41
8.37
8.42
9.76
9.69
9.68
9.67
12.95
12.81
12.81
12.83
11.21
11.06
11.03
11.02
12.95
12.88
12.86
12.86
16.97
16.83
16.81
16.85
Cload (pF)
Above tables show the loading effect on the output node of the counter. There is
negligible variation in rise time, fall time and propagation delay, if we increase the clock
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frequency at no load condition. But there is almost linear increment of these values with
the increase of capacitive load.
Following figures show the variation of rise time, fall time and propagation delay with
frequency at no load condition:
Time (ps)
300
250
200
150
C
D
100
50
0
1
10
50
100
Time (ps)
200
A
150
100
C
D
50
0
1
10
50
100
14
Time (ps)
600
500
400
300
200
100
0
1
10
50
100
Time (ns)
10
A
2
0
1
15
Time (ns)
12
10
2
0
1
Time (ns)
A
B
C
D
IX. Application:
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Counter can be considered as a heart of different digital and analog circuit. There are vast
applications of counter in the field of electronics. Only few of them are mentioned below
Some times we need different clock frequencies for the operation of different
parts of a large circuit. In that case counter can be efficiently used as a frequency
divider. From a 4 bit synchronous counter we can get four different frequencies
with a multiple of two.
Digital counter acts as a key part in the implementation of time dependent digital
logic control circuit. Coffee vending machine, microwave oven etc.- are some
very good example of such kind of circuits
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Layout 2
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Layout 3
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Layout 4
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Layout 5
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Layout 6
22
Layout 7
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Layout 8
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Layout 9
25
Layout 10
26
27
Layout 11
Layout 12
28
Layout 13
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