IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO.

4, APRIL 2014

961

A Time-Based Pipelined ADC Using Both

Voltage and Time Domain Information
Taehwan Oh, Member, IEEE, Hariprasath Venkatram, Member, IEEE, and Un-Ku Moon, Fellow, IEEE

AbstractIn this paper, a Nyquist ADC with a time-based

pipelined TDC is proposed. In the proposed ADC, the first
pipeline stage incorporates both residue amplification and a V-T
conversion with high accuracy, efficiently realized by a low gain
amplifier with only 24 dB dc gain. Furthermore, adding to power
efficiency, a hybrid time-domain pipeline stage based on simple
charge pump and capacitor DAC in its backend stages is also
proposed. Using the right combination of voltage and time domain information, the proposed ADC architecture benefits from
improved resolution and power efficiency, with MSBs resolved in
voltage domain and LSBs in time domain. The measured results of
the prototype ADC implemented in a 0.13 m CMOS demonstrate
peak SNDR of 69.3 dB at 6.38 mW power and 70 MHz sampling
frequency. The FOM based on peak SNDR is 38.2 fJ/conversion-step.
Index TermsPipelined analog-to-digital converters, time domain, time-to-digital converters, voltage domain, voltage-to-time
conversion.

I. INTRODUCTION

IGH resolution and wide signal bandwidth with low

power consumption are preferred specifications of
ADCs used in a variety of applications. For high resolution
and wide bandwidth, the pipelined ADCs, which employ a
residue amplifier with high open loop gain in a conventional
voltage domain, have been widely used for many decades.
However, it is more challenging to design a pipelined ADC in
the advanced deep sub-micron processes due to the reduced
supply voltage and intrinsic gain of the device. It is difficult to
reduce the power consumption of the pipelined ADC due to the
need for an accurate amplifier, which consumes large power in
general. The SAR architecture is a good alternative to achieve
a better power efficiency, but it still needs a power hungry

Manuscript received August 17, 2013; revised October 21, 2013; accepted
November 19, 2013. Date of publication December 18, 2013; date of current
version March 24, 2014. This paper was approved by Guest Editor Hideyuki
Kabuo. This work is supported by CDADIC and partly by SRC.
T. Oh was with the School of Electrical Engineering and Computer Science,
Oregon State University, Corvallis, OR 97331 USA, and is now with Tektronix,
Inc., Beaverton, OR 97077 USA.
H. Venkatram was with the School of Electrical Engineering and Computer
Science, Oregon State University, Corvallis, OR 97331 USA, and is now with
Intel Corporation, Hillsboro, OR 97124 USA.
U. Moon is with the School of Electrical Engineering and Computer Science,
Oregon State University, Corvallis, OR 97331 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2013.2293019

residue amplifier to achieve high resolution (in a multi-stage

architecture) [1], which is less power efficient and difficult to
design in reduced supply voltage. While there are many ways
to reduce power consumption of the ADC by using a simple
low gain amplifier with relatively low power consumption, it
is not easy to correct nonlinear amplifier errors. Furthermore,
the nonlinear error becomes worse with process scaling, due to
the difficulty in maintaining a moderate signal swing at lower
supply voltage.
Recently, time-domain quantizers have drawn attention in
advanced CMOS processes as a viable candidate for power
efficient ADC architecture [2][4]. In order to increase the
resolution in time domain, a time amplifier is employed in
multi-stage architectures [5][7]. However, these approaches
need complex calibration to correct the time amplifier nonlinearity. Other approaches using a linear current source for the
time amplification have been reported in [8][10]. Although
these designs show power-efficient data conversion utilizing
time-domain signal processing without an expensive residue
amplifier, they are restricted in performance, offering either
low bandwidth [8] or limited resolution [9], [10]. The accuracy
of the TDC can be improved with time amplification, but the
resolution solely in time domain is limited in general and not
comparable to the resolution of the state of the art ADC in
voltage domain.
In this paper, a hybrid pipelined ADC which uses both voltage
and time domain information is proposed [11]. The proposed
ADC employs a new voltage-to-time conversion scheme using a
scalable, power efficient, residue amplifier with minimal dc gain
in its first stage while maintaining high linearity. This scheme
not only reduces the power consumption of the ADC but also
relaxes the design trade-off of the amplifier in a low supply
voltage deep sub-micron process without sacrificing bandwidth.
Also, the power efficiency and linearity of the proposed ADC
are further improved by the hybrid time-domain pipeline stage,
which employs a simple charge pump and capacitor DAC for
the time residue amplification and quantization in the backend
pipeline stages.
This paper is organized as follows. In Section II, utilization
of time domain information in a high resolution pipelined ADC
is briefly discussed. Section III presents the proposed pipelined
ADC incorporating a new - conversion scheme and a hybrid
time-based pipeline stage. The implementation details and design considerations of non-idealities are followed in Sections IV
and V, respectively. Finally, measurement results are provided
in Section VI, followed by conclusions in Section VII.

0018-9200 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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Fig. 2. Pipelined TDC example with time-domain pipeline stage.

Fig. 1. Example of the time amplification and quantization using charge pump.

II. UTILIZING TIME DOMAIN INFORMATION

FOR HIGH RESOLUTION ADC
Efficiently resolving bits and pipelining the quantization error
requires robust and accurate residue amplification in time domain. Fig. 1 shows one possible way to achieve such residue
amplification similar to the time amplification in [8]. Based on
a simple charge pump design, the time input can be amplified by
using different slopes applied for charging and discharging. By
measuring the discharging time for the zero-crossing, utilizing
current sources with different ratio, the input time can be amplified. In this example, the amplified output time with the gain of
4 is calculated as the following equation:

Fig. 3. Time residue amplification and quantization of the time-domain

pipeline stage.

(1)
The amplified time input signal is quantized based on a time reference and the time-domain quantization error can be generated.
Similar to a conventional pipelined ADC in a voltage domain,
this amplification scheme can be applied to process a time-domain signal in a pipelined architecture as shown in Fig. 2. After
) is quantized by the subthe reset phase, the time input (
)
TDC, which generates the digital output and DAC pulse (
is generfor residue generation. As shown in Fig. 3,
from the time reference (
) during
ated according to
) is
the quantization. Then, the time-domain residue (
amplified by 4 with a different current ratio of 4:1 for charging
and discharging in this example. After the zero-crossing com) is generated
parison, the time-domain residue output (
for further quantization in the next pipeline stage. With time-domain residue amplification and its simple open loop configuration, further quantization is possible to extract higher resolution
with relatively low power consumption.

III. PROPOSED HYBRID VOLTAGE AND TIME DOMAIN

PIPELINED ADC
A. Proposed ADC Architecture
Shown in Fig. 4 is the proposed hybrid voltage and timebased pipelined ADC. It consists of a conventional 4 bit MDAC
and a FLASH in voltage domain, a zero-crossing comparator
for - conversion, four time-domain pipeline stages (TSTGs)
and a 2.5 bit TDC for backend pipelined stage, and other supporting blocks. With a 1 bit redundancy between the pipeline
stages, the ADC generates a 14 bit digital output. - tracking
block, which provides a coarse current reference to the - converter in the MDAC and TSTGs, tracks the relation between
the voltage and time domain gain. - gain is also tuned externally in analog domain and the finite gain error in each stage
is corrected by a simple off-chip radix calibration in digital domain. It is instructive to note that the linear gain error correction
is enabled by the proposed - converter despite the use of a

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963

Fig. 4. Proposed time-based pipelined ADC.

Fig. 5. Conventional

conversion employed in noise-shaped two-step integration quantizer in [12].

low gain nonlinear amplifier. For sub-TDCs time reference, a

voltage controlled delay line (VCDL) is employed.
The key features of the proposed ADC are as follows: First, a
high resolution and wide signal bandwidth can be attained with
the pipelined Nyquist ADC architecture. Second, a low gain
power-efficient and nonlinear amplifier can be used for linear
- conversion in the first stage based on the proposed conversion. Third, a simple charge pump based pipelined architecture is employed for low power consumption. Finally, the
accuracy requirement of the backend pipelined TDC in time domain is significantly relaxed by the resolution of the first stage
in voltage domain, where high accuracy is easier to achieve than
a conventional TDC only architecture in time domain. As a result, this architecture takes advantage of the unique benefits of
utilizing both the voltage and the time domains, by processing
MSBs in voltage domain and LSBs in time domain with this
proposed architecture.
B.

Conversion

To process the signal in time domain, the initial input to the

first stage of the ADC in voltage should be converted to a timedomain signal. An example of a conventional - conversion
employed in a two-step quantizer is shown in Fig. 5 [12]. Since
the transferred residue charge on the feedback capacitor
is used for measuring the discharging time, the accuracy of

this charge transfer affects this - conversion process (charge

transfer is based on the amplifier characteristic). The residue
output in voltage domain after the amplification phase is given
by the following equation:
(2)
is a nonlinear open loop dc gain of the ampliwhere
fier which is affected by the signal swing and is the feedback factor. Therefore, the time-domain output at zero-crossing
is given by (3):
(3)
As a result, any nonlinear error from the amplifier directly affects the time-domain output in this - conversion. Therefore,
a high gain and linear amplifier is required and output swing is
limited in this case.
Fig. 6 shows the proposed - conversion, which alleviates the stringent amplifier requirements on gain, output swing,
and linearity. In the proposed solution, which operates in three
phases, the charge stored in both sampling and feedback capacitors is discharged together. Because there is no charge loss
on both capacitors and discharged together to measure the time

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Fig. 6. Proposed

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 4, APRIL 2014

conversion which operates in three phases.

for zero-crossing, the time-domain output at zero-crossing is always linear regardless of the amplifier non-idealities, as long as
the current source meets linearity requirement [13]. The residue
output after the amplification phase in this case is derived in the
following equation:
(4)
As reflected in (4), the residue output in voltage domain is still
affected by the amplifier characteristics. However, the time-domain output at zero-crossing in the discharging phase is independent of the amplifier characteristics as shown in (5):
(5)
is linear regardless of the amplifier
As a result, the output
characteristics in the proposed - conversion. An intuitive
way to understand (5) is to realize that the zero-crossing detection by the comparator is always detected at the same voltage
(for the differential zero). There is no signal dependent amplifier error in the time-domain output at the zero-crossing detection. Therefore, a low gain nonlinear amplifier can be used in
the proposed - conversion. The bandwidth of the amplifier
affects the time delay during the discharging phase, which is
largely signal independent in a relatively high bandwidth amplifier. Despite being a three phase operation, the time required
for the voltage domain residue amplification can be minimized.
The amplification phase does not require a fully settled residue
output in voltage domain. Fig. 7 shows the linearity simulation
of the proposed - conversion which compares the linearity

Fig. 7. Linearity simulation of the proposed - conversion using a residue

amplifier with 24 dB open loop dc gain (time domain output is converted to
voltage domain signal with an ideal time-to-voltage converter for measuring
the spectrum using FFT simulation).

of the residue output in voltage domain and time domain. In

this transistor level simulation with a 1.2
signal at 1.2-V
supply, a single stage common source amplifier, which has an
open loop dc gain of 24 dB, is used. As shown in Fig. 7, the
time-domain output after the discharging phase shows a superior linearity compared to the voltage output of the amplifier
after amplification (prior to discharging) with a simple nonlinear
amplifier with minimal gain.
This simple method for a - conversion provides significant advantages as follows. First, the output swing of the amplifier (input swing of comparator) can be maximized, which
makes it easy to design the zero-crossing comparator for low
power. This provides scalability of design and portability in

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965

Fig. 9. Proposed hybrid time-domain stage.

Fig. 8. Examples for time reference generation.

the recent CMOS processes with low supply voltage. Second,

a simple (small area and low power) amplifier with very low
gain could be employed for - conversion. Even though the
amplifier sees a reduced feedback factor in this case and less
time for settling because of three-phase operation (needs more
bandwidth), it benefits from a significant net improvement from
being able to use much simpler amplifier architecture. Thanks to
the proposed - conversion, the most power hungry block of
the residue amplifier in the first pipeline stage can be designed
without the conventional stringent requirements such as gain,
linearity, and power. This results in a scalable, low voltage, low
power ADC architecture amenable towards deep sub-micron
process.
C. Hybrid Time Domain Stage
Even though the pipelined TDC example based on the timedomain pipeline stage in the previous section is a suitable candidate for low power consumption, it also has several error sources
such as the nonlinearity of the current source, the noise of the
comparator, and the jitter of the time reference. In particular,
jitter of the time reference will be the limiting factor for a given
process, speed, resolution and power of the pipelined TDC. The
linearity of the DAC pulse in the time-domain quantization is
also critical in achieving high accuracy, similar to DAC linearity
in a conventional pipelined ADC.
Fig. 8 shows two possible methods to generate the time reference. Either a high frequency clock from an oscillator or a
delay line from DLL is typically employed as a time reference.
However both methods require high accuracy, which adds to
complexity. In general, the high frequency clock suffers from
the jitter and can consume a large amount of power. In order to
achieve -bit SNR, the required jitter tolerance in the time reference is less than 1
of the -bit TDC resolution, which is
not easy to achieve in high resolution cases with fine time reference [14]. Also DLL has a limited linearity due to its delay cell
mismatch [15]. Even though the jitter induced error or nonlinearity from the time reference can be calibrated, it requires complex calibration algorithm and extra power consumption [16].

Fig. 10. Basic operation of the proposed hybrid time-domain stage.

To solve the problem efficiently, a hybrid time-domain quantization stage is proposed as shown in Fig. 9. The proposed hybrid stage employs a capacitor DAC for charge subtraction instead of using a time-domain DAC pulse. The linearity of DAC
in this architecture only depends on capacitor matching, which
is not difficult to achieve. Time-domain error sources such as
jitter or delay cell mismatch now only affect the linearity of
sub-TDC and it is relaxed with the given redundancy between
stages. With a conventional error correction scheme which usually is employed to correct comparator error in a pipelined ADC,
the time reference error up to
can be corrected by
the 1 bit redundancy between the pipeline stages [17]. Fig. 10
illustrates the operation of the proposed stage. Initially, all capacitors are reset to the positive reference. In charging phase,
capacitors are charged by a fixed current (4I) based on the time
input. At the same time, sub-TDC quantizes the time input and
generates a corresponding thermometer code for the DAC operation, sequentially. In next phase, the stored charge on the capacitors (which represents the residue) is discharged by a different current ratio (I) for residue amplification. After the zerocrossing, the amplified time residue output is passed on to the
next pipelined stage.
The comparison of two different time amplification methods
is shown in Fig. 11. In case of the amplification using a dual
slope (charging and discharging), the linearity of the current
source is limited (or signal swing is reduced) and the residue
gain is not well defined due to the different type of current

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Fig. 12. Multiplying digital-to-analog converter (MDAC) incorporating the

proposed - conversion (drawn as single-ended for simplicity).
Fig. 11. Comparison of two different implementations of the time amplification: dual slope (charging and discharging) vs. single slope (two charging).

sources (PMOS and NMOS type) for the amplification. However in a single slope case (using two charging slopes) similar
to [8], the same type of current source is used for amplification.
As a result, the residue gain only depends on the matching of the
same type of current sources which is well defined with careful
layout. In this case, the linearity of the current source can be
maximized with a proper control of the output common mode.
Although twice the capacitors are required in the single slope
case, it provides many advantages in real implementation which
uses a low supply voltage. In case of the amplification using a
dual slope, it is difficult to get a required signal swing with high
linearity, which results in an increased capacitance for the same
SNR with a smaller signal swing. Therefore, the amplification
method using the single slope is employed in this work.

Fig. 13. Switched residue amplifier with a dc gain of 24 dB in MDAC.

IV. CIRCUIT IMPLEMENTATION

A. Multiplying Digital-to-Analog Converter (MDAC)
Fig. 12 shows the first stage MDAC in the proposed ADC.
The proposed MDAC is similar to the conventional MDAC except the additional blocks employed for discharging and conversion. It consists of capacitors and switches for sampling
and DAC operation, a residue amplifier, a discharging current
source, and a zero-crossing comparator. In this implementation,
the number of sampling capacitors for DAC operation is reduced by half, based on the merged capacitor switching technique (8 capacitors for 4 bit operation) [18]. Note that there is
an additional path providing a fixed offset up to half of MDAC
output swing, which guarantees that the MDAC output is always
larger than zero for the uni-directional discharging, similar to
the MDAC in the two-step quantizer in [12].
Thanks to the proposed - conversion scheme a simple
switched amplifier which has only 24 dB dc gain is employed
as shown in Fig. 13. The proposed amplifier only operates in
amplifying/discharging phase based on switched operation for
low power consumption. Also, it drives only a small load capacitance (zero-crossing comparator) in the proposed architecture.

Fig. 14. Implementation of the time-domain pipeline stage (TSTG).

Because the first stage residue amplifier is the most power consuming block in conventional pipelined architecture, this simple
amplifier structure incorporating small load capacitance reduces
ADC power consumption significantly. The power consumption
of the amplifier is further reduced by turning it off asynchronously after zero-crossing.

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967

Fig. 15. Switched charge pump (drawn PMOS current sources only for simplicity).

Fig. 16. Switched zero-crossing comparator.

B. Time Domain Pipeline Stage (TSTG)

Fig. 14 shows the implemented hybrid time-domain stage,
which adopts a pseudo differential configuration for better
supply noise immunity. It consists of capacitors and switches
for charging and DAC operation, current sources for two
charging slopes, sub-TDC with 2.5 bits, and a zero-crossing
comparator. Note that the comparator with four inputs is employed for a pseudo differential operation. The common mode
levels of current sources and comparator input are controlled
separately using the coupling capacitor,
, to maximize the
linearity of current source. Therefore, the current variation
of the current source, due to the switching operation of the
capacitor DAC during the first charging phase with
, is
minimized in this implementation. Because the parasitic capacitances on the output node of the current source and on the
input node of comparator are signal dependent, the linearity of
the proposed stage is mainly limited by these parasitic capacitances. Although the linearity can be improved by using a larger
charging capacitance over the parasitic capacitance, it would
consume more power. Therefore, it would be quite difficult to
attain a very high accuracy if we were to incorporate only such
TDC stages. In the proposed ADC architecture, the accuracy
requirement of this TDC stage is relaxed by the resolution of
the first stage processed in voltage domain.

C. Switched Charge Pump

The detailed schematic of the charge pump in TSTG is illustrated in Fig. 15. The time residue gain is simply defined by the
device ratio of two PMOS transistors as current sources. In the
proposed charge pump, the dedicated reset phase,
and
,
allows the current source to be settled to the bias point from
the turned-off condition before the actual charging. The current
source is switched-off completely after the charging to reduce
power consumption. Therefore, only the charge during the two
charging phases is used for the operation, without any static
charge in the charge pump. The power consumption is reduced
further by switching off asynchronously after zero-crossing.
D. Switched Zero-Crossing Comparator
Fig. 16 shows the proposed zero-crossing comparator employed in TSTG. Similar to the charge pump, the comparator
is completely turned off asynchronously after the zero-crossing
detection to minimize power consumption. In the proposed
time-domain pipeline stage, the linearity is limited by the signal
dependant parasitic capacitance on the comparator input node.
During the first charging phase, the comparator is turned-off
because the comparator is not used for comparison. However,
any voltage change on the floating node from the turned-off
transistor causes the parasitic capacitance to change, which
results in a nonlinear error during the charging operation. This

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 4, APRIL 2014

Fig. 17.

gain tracking circuit.

problem is relaxed by adopting additional switches as shown

in the dotted box in Fig. 16, which make the input parasitic
capacitance constant.
E.

Gain Tracking Circuit

In the proposed ADC, the equivalent voltage-to-time conversion gain depends on the capacitance and current value with
a given voltage reference and time reference for discharging.
However these values are not well defined in real implementation. The - tracking circuit shown in Fig. 17 provides a
coarse current reference for MDAC and TSTGs. With a same
voltage and time reference, the tracking circuit tracks the correct current value for discharging for a replica capacitor used in
MDAC and TSTG1. However due to the limited matching accuracy of this replica path, the - gain is also tuned externally,
and the finite gain error after tuning is corrected by a simple
off-chip radix-based calibration in digital domain [19].

Fig. 18. Integrated noise model from the current source in MDAC.

In (7), the current value for the discharging in a given time

window is fixed based on the ADC reference voltage and sampling capacitance (
), the input-referred
noise can be derived as follows:
(8)

V. CONSIDERATION OF NON-IDEALITIES
A. Integrated Noise From Current Source
In the proposed ADC, the integrated noise from the current
source in the first stage MDAC dominates the noise performance, which is directly related to the ADC resolution. Fig. 18
shows the equivalent noise model to analyze the integrated noise
from the current source of MDAC. If we assume the bandwidth
of the amplifier is much higher than the switching time for discharging (
), the voltage accumulated on feedback
capacitor
is approximated as follows:

(6)
where the power spectral density of the current source is
. Therefore, the equivalent input-referred noise is
derived in following equation by dividing the signal gain:
(7)

and
is the residue gain of the
Because the ratio between
MDAC, this equation can be re-formulated as follows:
(9)
is
, is the residue gain (
),
where
and
is the effective voltage (or overdrive voltage) of the
current source. From (9), the input referred noise from current
source is affected by the sampling capacitance, the residue gain,
and the ratio between the ADC reference range (or signal range)
and the effective voltage of the current source. For given signal
swing, this noise can be minimized by maximizing effective
voltage of the current source for a given supply voltage. Also,
this noise can be reduced by increasing the residue gain (by resolving more bits from the first stage). Even though the proposed ADC requires a slightly larger sampling capacitance than
the conventional pipelined ADC for the same SNR performance
due to this additional noise from the discharging current source,
the benefits of the proposed architecture in terms of the power
consumption and linearity in real implementation are significant, especially under the condition with low supply voltage.

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969

Fig. 20. Chip photo of the prototype ADC in 0.13

mm
m by 460 m).
(

m CMOS process

Fig. 19. Residue plot of TSTG (a) with comparator delay and (b) with delay
correction by injecting time offset in time reference.

B. Delay From Zero-Crossing Comparator

The dynamic range of the proposed time-domain stage is
mainly limited by the delay from zero-crossing comparator.
Fig. 19(a) shows the residue plot of TSTG with a 2.5 bit
resolution (6 time comparators). With a conventional error
correction scheme based on 1 bit redundancy, the decision
error up to
from the sub-TDC can be corrected
in the proposed architecture. The error correction range is
in ideal case. However, the error correction range
is reduced due to the delay from the zero-crossing comparator
(in red curve). If this delay is larger than
, the residue
output will saturate the following pipeline stage, which could
be problematic in the proposed architecture. Only the delay
from the comparator is considered here for simplification,
which is the largest contributor in the proposed architecture.
Therefore the delay should be minimized compared to the time
reference or should be properly corrected (to maximize error
correction range). Fig. 19(b) compares two residue plots with
and without a delay correction, which compensate the delay
from the zero-crossing comparator. With the delay correction,
the delay can be corrected by subtracting the same amount of
delay from the time reference as a time offset (in blue curve).
By shifting the decision point of the sub-TDC, the time residue
output can be located in the nominal range, which allows the
same error correction range as the ideal case. As a result, the
entire error correction range (up to
) is used for
the error correction of the sub-TDC. In this implementation,
another adjustable delay cell is added to the time reference (in

Fig. 21. Measured DNL and INL.

VCDL) for this purpose. This time offset is adjusted externally

by monitoring the digital output code from the sub-TDC.
VI. MEASUREMENT RESULTS
The prototype ADC was implemented in a 0.13 m CMOS
process. Fig. 20 shows the chip photograph of the fabricated
prototype [11]. The active area is 0.5 mm (1095 m by
460 m). Fig. 21 shows the measured DNL and INL. In this
measurement, 11 bit MSBs are used for DNL and INL calculation. In this prototype, an adjustable delay cell is employed
in the time reference, which corrects each comparator delay
globally. However due to the limited delay correction range and
matching accuracy of the blocks in actual implementation, this
global delay correction does not completely correct the delay
in the LSB stage (TSTG3). This results in input saturation of
the next stage (TSTG4). Due to this saturation, the prototype
ADC still has a few missing codes even at 12 bit resolution.
Therefore, DNL and INL of the prototype ADC are measured
at 11 bit resolution, while the entire 14 bit output is used for
SNDR and SFDR measurements. The measured DNL and
INL at 11 bit accuracy are
and
,
respectively. Fig. 22 shows the measured output spectrum at
70 MS/s sampling rate and 1 MHz input frequency. The measured SNDR and SFDR are 69.3 dB and 80.6 dB, respectively,
while consuming 6.38 mW under 1.3-V supply. Due to the
proposed - conversion in the first stage of the pipelined

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Fig. 25. Power breakdown of the prototype ADC.

TABLE I
PERFORMANCE COMPARISON.
Fig. 22. Measured output spectrum (
factor of 4).

, downsampled by a

TABLE II
PERFORMANCE SUMMARY OF THE PROTOTYPE ADC.

Fig. 23. Measured SNDR vs. input frequency.

Fig. 24. Dynamic range of the proposed ADC.

ADC, the input range is maximized up to near rail-to-rail of

2.4
for the maximum SNR performance while achieving
high linearity of more than 80 dB SFDR at the same time.
The measured SNDR and SFDR with 20 MHz input frequency
are 65.2 dB and 75.9 dB, respectively. The measured SNDR
versus different input frequencies is shown in Fig. 23. The
measured dynamic range with 1 MHz input signal is shown
in Fig. 24, which is 72.6 dB with a
of the full scale
input. The calculated best FOM with a 1 MHz input frequency

is 38.2 fJ/conversion-step. Table I compares the recently published state of the art Nyquist ADC with maximum SNDR
above 65 dB, sampling rate above 50 MHz, and Walden FOM
below 100 fJ/C-S [20][24]. As shown in Table I, the proposed
ADC shows a competitive FOM among the recently published
ADCs with similar specifications. The FOM of the proposed
ADC can be improved further with a more advanced CMOS
process. Fig. 25 shows the power breakdown and Table II
summarizes the measured performance of the prototype ADC,
respectively.
VII. CONCLUSION
A pipelined ADC incorporating a time-based pipeline architecture is presented in this paper. The proposed ADC uses both

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time domain and voltage domain information in analog-to-digital conversion. By using the pipelined TDC as a backend stage
of the ADC, as well as a pipeline stage in voltage domain as
the first stage, the proposed architecture achieves power efficiency and the linearity. The proposed ADC is amenable to
process scaling and uses a scaling-friendly amplifier with minimum dc gain and maximum signal swing (in the first stage
MDAC for - conversion). The power efficiency and linearity of the ADC are further improved by the proposed hybrid
time-domain pipeline stage which uses a simple charge pump
and capacitor DAC for the time residue generation.
ACKNOWLEDGMENT
The authors would like to thank Texas Instruments for the
chip fabrication.
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Taehwan Oh (S09M14) received the B.S. and
M.S. degrees in electronic engineering from Sogang
University, Seoul, Korea, in 2000 and 2002, respectively, and the Ph.D. degree in electrical engineering
and computer science from Oregon State University,
Corvallis, OR, USA, in 2013.
He is currently an analog design engineer at
Tektronix, Inc., Beaverton, OR, USA. From 2002
to 2009, he was with Samsung Electronics, Yongin,
Korea, where he was working on analog-to-digital
converters and analog front-end for various applications. His research interests include high performance analog-to-digital
converters and analog front-end for signal interface in many applications.
Hariprasath Venkatram (S08M14) received the
B.Tech. and M.Tech. dual degrees in electrical engineering from Indian Institute of Technology, Madras,
India, in 2008, and the Ph.D. degree in electrical engineering and computer science from Oregon State
University, Corvallis, OR, USA, in 2013.
He is currently a research scientist at Intel Corporation, Hillsboro, OR, USA. He has received the
Professor Achim Bopp Award from IIT-Madras and
a finalist in the Broadcom Foundation University
Research competition. His research interests include
data converters, timing circuits, amplifiers, filters and mixed signal design. He
is a member of Solid-State Circuits and Circuits and Systems Society.
Un-Ku Moon (S92M94SM99F09) received
the B.S. degree from the University of Washington,
Seattle, WA, USA, in 1987, the M.Eng. degree from
Cornell University, Ithaca, NY, USA, in 1989, and
the Ph.D. degree from the University of Illinois,
Urbana-Champaign, IL, USA, in 1994.
He has been with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA, since 1998. Before joining
Oregon State University, he was with Bell Laboratories from 1988 to 1989, and from 1994 to 1998. His
technical contributions have been in the area of analog and mixed-signal circuits including high linearity filters, timing recovery, PLLs, data converters, and
low-voltage circuits for CMOS.
Dr. Moon served as the Editor-in-Chief of the IEEE JOURNAL OF SOLIDSTATE CIRCUITS and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II,
as a Distinguished Lecturer of the IEEE Solid-State Circuits Society, as an Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS II, and as the Deputy Editor-inChief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. He served on
governing boards of both the IEEE Solid-State Circuits Society (SSCS AdCom)
and the IEEE Circuits and Systems Society (CASS BoG) as the SSCS representative to CASS. He also served as a Technical Program Committee member of
the IEEE International Solid-State Circuits Conference, the IEEE VLSI Circuits
Symposium, and the IEEE Custom Integrated Circuits Conference. He currently
serves on the Executive Committee of the IEEE Symposia on VLSI Technology
and Circuits.