74122

MONOSTABLE MULTIVIBRATOR
(Single, Retriggerable)

\
Al

A2

Bl
TOP

B2

CLR

VIEW

This is a monostable multivibrator or pulse generator. The circuit must

be triggered.
In response to a trigger, the Q output goes high and the Q output
goes low, staying there for a predetermined time and then returning
to the initial state.
A capacitor connected between pins 11 and 13 determines the pulse
width in combination with a resistor between pin 13 and pin 14. Fig.
4-30 gives the time-constant curves. The resistor can range from 5K
to 25K and the capacitor from 10 pF upward.
There are several ways to trigger the monostable multivibrator, determined by what you do to the A l , A2, B l , B2, and Clear inputs.
If A l , A2, and B2 are high, a low-to-high transition
If A l , B l , and B2 are high, a high-to-low transition
The Clear input should remain high. If grounded, it
ing and returns the circuit to the state with Q low and

on Bl triggers.
on A2 triggers.
mhibits triggerQ high.

The circuit may be retriggered at any time. Be sure to properly terminate oil four trigger inputs. Certain forms of clip-on digital testers
can upset the operation of this stage, particularly on the resistor and
capacitor inputs.
Unless very short times or complementary outputs or retriggerability
is needed, the 555 is a better choice of monostable multivibrator.
Current per package

23 milliamperes typical

74123
MONOSTABLE MULTIVIBRATOR
(Dual, Retriggerable)

lA
TOP VIEW

This IS a dual monostable multivibrator or pulse generator. Each

half of the circuit must be triggered. Each half of the circuit may be
used separately.
In response to a trigger, the Q output goes high and the Q output
goes low, staying there for a predetermined time and then returning
to the initial state.
A capacitor and resistor connected as shown determine the pulse
width. Fig. 4-30 gives the time-constant curves. The resistor can range
from 5K to 25K and the capacitor from 10 pF upward.
There are two ways to trigger the monostable multivibrator. If input
A is held /ow, bringing B from low to high triggers. If input B is held
high, bringing input A from high to low triggers.
The Clear input should remain high. If grounded, it inhibits triggering
and returns the circuit to the state with Q low and Q high.
The circuit may be retriggered at any time. Be sure to properly ferminote all Trigger and Clear inputs. Certain forms of clip-on digital
testers can upset the operation of this stage, particularly on the
Resistor and Capacitor inputs.
Unless very short times or complementary outputs or retriggerability
is needed, the 555 is a better choice of monostable multivibrator.
Current per package

46 milliamperes typical

tors must be used in this circuit. The temperature range is from -30
to +50C with the probe shown. The resolution is 0.1 degree.
NEGATIVE-RECOVERY CIRCUITS

Ordinary monostable circuits need a certain time to recover after

triggering. If the recovery time is not completed, the next time cycle
OUTPUT PULSE WIDTH VERSUS TIMING RESISTOR

10 ms

10 n

7
10
20
R y - T I M I N G RESISTOR-KO

9+5V

4nT4l5
11
^-r

10

-o OUTPUT

74121

INPUT TRIGGER
o

+5V

ITGND

-G

OUTPUT

sir

(A) 74121.
Fig. 4-30. Monostable circuits

might be shortened, and an inaccuracy or jitter can result. As a general rule, monostable circuits operate best if the recovery time exceeds
the ON time, although you can operate with ON times of 90% if you
are careful and choose the right resistor values.
Some special circuits let us retrigger the monostable circuit at any
time. These are called negative-recovery monostable circuits. They are
used for missing-pulse detection, voice-controlled systems, code analOUTPUT PULSE WIDTH

TIMING CAPACITANCE

10000
7000

4000

2000

//

1000

700

i^
)

200

/
/

400

Q_

/
:^

/
i

/
^

a '

g
^

100

iMirwiliiiiiifiiiwiimmiMMnn

70

40

5V

20

\ \ - 2.

in
1

10

20

40

70 100

200

400

700 1000

C ^ y - - T I M I N G CAPACITANCE - pF

+5V
o 2,3,4, 5

Rl

"IT

14
13
o

11

"ITc

GND

15
TRIGI
o

-o

^
i

10.
11
16:

OUTPUT

ir IT

-oQ

using the 74121, 74122, and 74123.

-oQ

Ji
i
12

TRIG 2
+5V

-oQ

74123
(DUAL)

oWJHH
R2

(B) 74122.

13

2,

+5V(>

74122

INPUT
TRIGGER o +5V

OUTPUT

Cl

+5V

C2

(C) 74123.

-oQ

TYPES SN5446A WA '48, '49, SN54L46, 'L47, SN54LS47, 'LS48, LS49,

TYPES SNS'l'bA, ^ A ^0,
,
,^^7 SN74LS47, 1348, 1349
3N744BA, ' " J J P ' ^ ^ O I E V E N 3EGIV1ENT DEC0DER3/DRIVERS

iiiiMiiiiiiiiiJi iiMlTWIITMIMIIBillillllll 11

'"

ii*"i"i'"'W''"aa'MM'i^MM^""''"'*^^^^^^^"*M"M*a

'49, 'LS49
feature

'48, 'LS48
feature

'46A, '47A, X 4 6 , 'L47, TS47

feature

Open-Collector Outputs

Blanking Input

m Open-Collector Outputs
Drive Indicators Directly

Internal Pull-Ups Eliminate

Need for External Resistors

Lamp-Test Provision

Lamp-Test Provision

Leading/Trailing Zero
Leading/Trailing Zero
\
Suppression
Suppression
All Circuit Types Feature Lamp Intensity Modulation Capability

TYPE

ACTIVE
LEVEL
low

SN5446A
SN5447A
SN5448
SN5449
SN54L46
SN54L47
SN54LS47
SN54LS48
SN54LS49
SN7446A
SN7447A
SN7448
SN74L46
SN74L47
SN74LS47
SN74LS48
SN74LS49

low

high
high
low
low
low

high
high
low
low

high
low
low

MAX
VOLTAGE

OUTPUT
CONFIGURATION
_

open-collector
open-collector
2-kn pull-up
open-collector
open-col lector
open-co I lector
"
open-collector
2-kn pull-up
open-collector
open-collector
open-collector
2-kn pull-up
open-collector
open-collector

low

high
high

open-collector
2-kl2 pull-up
open-collector

TYPICAL
POWER
DISSIPATION
320 mW
320 mW
265 mW
165 mW
160 mW
160 mW
35 mW
125 mW
40 mW
320 mW
320 mW
265 mW
160 mW
160 mW
35 mW
125 mW
40 mW

PACKAGES

'49, 'LS49
(TOP VIEW)

'48, 'LS48
(TOP VIEW)

'46A, '47A, 'L46, 'L47, 'LS47

(TOP VIEW)

OUTPUTS

OUTPUTS

vcc

ft4iL[tuti|kjiHjjn4yu

Vcc

Jlsl

^^ES
B

Bl/
C LTRBORBI

] H [^UlTljriJaUTL

^s
g

C LTRBORBI

msj
nimruriinArtii y U
3T

LAMP
TEST

RB
OUT-

RB
IN-

.1/
.MOXTC

TEST

1^ [laJTLMJTLrrL

k ^
f

D A

IN-

PUT

PUT

D A

mi

OUT-

^'

s/

r
'Hminireninpig
"^

INPUTS

positive logic: see function tables

INPUTS

INPUTS.

TYPES SN5446A. '47A, 48, 49. SN54L46. 147. SN54LS47. 'LS48. 'LS49.
SN7446A. '47A. 48. SN74L46, 147. SN74LS47. 1S48. LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
description
The '46A, 'L46, '47A, 'L47, and 'LS47 feature active-low outputs designed for driving common-anode VLEDs or
incandescent indicators directly, and the '48, '49, 'LS48, 'LS49 feature active-high outputs for driving lamp buffers or
common-cathode VLEDs. All of the circuits except '49 and 'LS49 have full ripple-blanking input/output controls and a
lamp test input. The '49 and 'LS49 circuits incorporate a direct blanking input. Segment identification and resultant
displays are shown below. Display patterns for BCD input counts above 9 are unique symbols to authenticate input
conditions.
The '46A, '47A, '48, 'L46, ''L47, 'LS47, and 'LS48 circuits incorporate automatic leading and/or trailing-edge
zero-blanking control (RB! and RBO). Lamp test (LT) of these types may be performed at any time when the BI/RBO
node is at a high level. All types (including the '49 and 'LS49) contain an overriding blanking input (Bl) which can be
used to control the lamp intensity by pulsing or to inhibit the outputs. Inputs and outputs are entirely compatible for
use with TTL or DTL logic outputs.

The SN54246/SN74246 through '249 and the SN54LS247/SN74LS247 through 'Lsl49 compose the fil and
the 9 with tails and have been designed to offer the designer a choice between two indicator fonts. The
SN54249/SN74249 and SN54LS249/SN74LS249 are 16-pin versions of the 14-pin SN5449 and 'LS49. Included in the
'249 circuit and 'LS249 circuits are the full functional capability for lamp test and ripple blanking, which is
not available in the '49 or 'LS49 circuit.

IZI
2

IZII

l_

10

11

13

14

12

15

MUMERICAL DESIGNATIONS AND RESULTANT DISPLAYS

SEGMENT
IDENTIFICATION
DECIMAL

' 4 6 A / 4 7 A / L 4 6 , ' L47, 'LS47 FUNCTION TABLE

INPUTS

OR

OUTPUTS

BI/RBOf
c

ON

ON

ON

ON

ON

ON

OFF

OFF

ON

ON

OFF

OFF

OFF

OFF

ON

ON

OFF

ON

ON

OFF

ON

ON

ON

OFF

OFF

ON

RBI

ON

H
H

NOTE
e

LT

FUNCTION

OFF

ON

ON

OFF

OFF

ON

ON

ON

OFF

ON

ON

OFF

ON

ON

OFF

OFF

ON

ON

ON

ON

ON

ON

ON

ON

OFF

OFF

OFF

OFF

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

OFF

OFF

ON

ON

OFF

OFF

OFF

ON

ON

OFF

ON

OFF

OFF

ON

ON

OFF

OFF

ON

OFF

ON

OFF

OFF

OFF

ON

ON
ON

10
11

H
H

ON

OFF

OFF

ON

OFF

ON

OFF

OFF

OFF

ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

OFF

ON

ON

ON

ON

ON

ON

ON

13

14

15
Bl

LT

H
L

12

RBI

ON

H = high level, L = low level, X = irrelevant

NOTES: 1. The blanking input (Bl) must be open or held at a high logic level when output functions 0 through 15 are desired. The
ripple-blanking input (RBI) must be open or high if blanking of a decimal zero is not desired.
2. When a low logic level is applied directly to the blanking input (Bl), all segment outputs are off regardless of the level of any
other input,
3. When ripple-blanking input (RBI) and inputs A, B, C, and D are at a low level with the lamp test input high, all segment outputs
go off and the ripple-blanking output (RBO) goes to a low level (response condition).
4. When the blanking input/ripple blanking output (BI/RBO) is open or held high and a low is applied to the lamp-test input, all
segment outputs are on.
+ BI/RBO is wire-AND logic serving as blanking input (Bl) and/or ripple-blanking output (RBO).

TYPES SN54192. SN54193, SN54L192. SN54L193, SN54LS192, SN54LS193

SN74192, SN74193. SN74L192, SN74U93, SN74LS192, SN74LS193
SYNCHRONOUS 4-BIT UP/DOWN COUNTERS (OUAL CLOCK WITH CLEAR)

Cascading Circuitry Provided Internally

Synchronous Operation

Individual Preset to Each Flip-Flop

Fully Independent Clear Input

BULLETIN NO. DL-S 771 1828, DECEMBER 1972-REVISED AUGUST I977

SN54', SN54LS'. . . J OR W PACKAGE
SN54L'...J PACKAGE
SN74', SN74L', SN74LS'... J OR N PACKAGE
(TOP VIEW)
A
'nATAPifAW

TYPICAL MAXIMUM
TYPICAL
COUNT FREOUENCY POWER DISSIPATION
'192/193
32 MHz
325 mW
'L192/L193
7 MHz
43 mW
'LS192/LS193
32 MHz
95 mW
TYPES

OUTPUTS
A

'inAn

TJ

CLEAR BORROW CARRY LOAO

A
HAT A

HATA'

COUNT COUNT

description

^ ^

^^

Qc

Qp

iinjjiiJiiJLijiimir

These monolithic circuits are synchronous reversible

(up/down) counters having a complexity of 55
equivalent gates. The '192, 'L192, and 'LS192
logic: Low input to load sets Q^ = A,
circuits are BCD counters and the '193, 'L193 and
Q3 = B.Qc = C,andOo = D
'LSI93 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincidently with each other when so instructed by the
steering logic. This mode of operation eliminates the
output counting spikes which are normally associated with asynchronous (ripple-clock) counters.
DATA

'NPUT

Og

0^

COUNT COUNT

O^

Op

GNO

OUTPUTS

The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock)
input. The direction of counting is determined by which count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data
at the data inputs while the load input is low. The output will change to agree with the data inputs independently of
the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count
length with the preset inputs.

A clear input has been provided which forces all outputs to the low level when a high level is applied. The dear function
is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers, etc., required for long words.
These counters were designed to be cascaded without the need for external circuitry. Both borrow and carry outputs
are available to cascade both the up- and down-counting functions. The borrow output produces a pulse equal in width
to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to
the count-up input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow
and carry outputs to the count-down and count-up inputs respectively of the succeeding counter.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN54'
Supply voltage, Vcc (see Note 1)
Input voltage
Operating free-air temperature range
Storage temperature range

7
5.5

NOTE 1: Voltage values are with respect to network ground terminal.

SN54L'

SN54LS'

SN74'

8
5.5

7
7

7
5.5

- 5 5 to 125
- 6 5 to 150

SN74L'
8
5.5

SN74LS' UNIT
V
7
7
V

0to70
-65 to 150