Chi-Un LEI, Ph.D.

Research Statement
Deep sub-micron CMOS technologies enable highly integrated circuit systems for consumers and
communications. These systems contain embedded high performance analog/mixed-signal (AMS)
circuit blocks and sensitive radio frequency (RF) frontends. Furthermore, the sophisticated CMOS
devices and emerging materials used in VLSI introduce new and unknown reliability issues in
VLSI circuit design, such as spatial stochastic unreliability effects, temporal deterministic
unreliability effects and dynamic unreliability effects. In the past, to cope with the reliability
issues, circuit designers pay attention to only verifying reliability issues in the technology level
and designing circuits conservatively. However, these measures expose more and more
limitations. Therefore, design for reliability will become one of the essential elements for the
future nanometer CMOS circuit design.
My research is about developing reliable AMS circuit in nanometer CMOS technologies. The
goal of my research is as follows:
To improve the quality of AMS IC design (e.g. robustness, yield and circuit lifetime)
To shorten the time to market and avoid expensive re-design process
Currently, I am working on the following topics:
Modeling and simulation techniques to verify circuit reliability efficiently
Design techniques to assure the reliability of circuits
Current Research
To effectively handle large scale and sophisticated simulations, reduced (macro)models are used
for simulations. My doctoral dissertation focused on the development of linear macrmodeling and
signal integrity verification in the perspective of digital signal processing. Currently, I am
extending my research on non-linear macromodeling, simulation and self-healing circuit design.
A. Non-Linear Marcomodeling and Simulation Techniques for AMS Circuits
New needs are raised to sophisticatedly simulate non-linear characteristics in nanometer CMOS
RF components and AMS components in a device/circuit level for a reliable design. However,
related studies are just begun in the VLSI design community. My collaborator, Dr. Ngai Wong,
and I are developing a ten times speed up non-linear modelling and simulation methodologies
for computation-intensive simulation processes, in order to practically verify the performance of
AMS circuits within a reasonable period of time. The modelling process mainly relies on the
generalized non-linear system identification, which can model circuit systems with massive ports
and arbitrary input/output responses. Meanwhile, the simulation process will be leveraged by the
extremely efficient GPU computation platform, such that large-scale simulations become practical.
We want to develop: i) automatically configured non-linear system identification process using
bilinear models and stochastic models, ii) highly parallelized time-domain transient computation
methodologies using multi-dimensional numerical inverse Laplace Transform, and iii) a
software/hardware architecture for CPU-GPU co-simulation. We are applying a research grant
and support from HKU, and will seek for other funding opportunities (e.g. NVIDA) in the future.
B. Self-Healing AMS Circuit Design
I am carrying studies about building reliable AMS circuits with stochastic reliability problems in
nanoscale CMOS technology, that cannot be designed using conservative design approaches. The
objective of this study is to improve the production yield and circuit lifetime of AMS circuits.
Recently, Dr. Abhilash Goyal (Graduate from Georgia Tech.) and I have started to design lowcomplexity self-healing (self-calibrating) AMS circuits. In particular, we are applying oscillation
principle to develop a self-healing phase locked loop (PLL) topology that can compensate
degradation, ageing and variation in a real-time manner without an external test signal source. We
will generalize this topology to other AMS circuit components in the future. Furthermore, we

would like to develop low-complexity software/hardware co-design methodology for real-time

monitoring.
C. Wizard-Mode Linear Macromodeling and Simulation
I am extending my doctoral study on developing a comprehensive linear macromodeling
framework with a better versatility and adaptively. Furthermore, I am developing a model
validation flow to improve the authenticity and automaticity of the macromodeling process, which
is a practical issue and under-research topic. This helps to reduce the verification effort of
engineers and shorten the time to market.
Future Research
Based on my experience in developing methodologies in circuit simulation and circuit design, I
would like to conduct the following researches for the nanometer VLSI circuit.
A. Smart Battery Management System Design
Conventional power management techniques may further magnify the problems associated with
process induced variations and aging problems in nanometer CMOS techniques. Therefore, I
would like to carry out study about variation aware battery management system. The aim of this
study is to prolong the operation time of circuit systems and life of batteries via a smart battery
management system. The study will mainly exploit i) current sensing methodology under a harsh
environment, ii) hybrid/stochastic (formal) modelling of aging and process variations in batteries,
and iii) low power hardware implementation of battery management systems. My collaborators in
both universities and industries and I will start to work on this topic in 2012. We aim at
developing product prototype at the end of this long-term project. Currently, we are preparing an
initiate research funding proposal.
B. Rapid Non-Linear AMS Circuit Simulation via Validation and Perturbation
Besides developing sophisticated non-linear circuit modelling and simulation techniques, I will
also develop rapid simulation methodologies via seamless post-simulation perturbations.
Probabilistic parametric noise modelling will be used for perturbations, such that we can have a
trade-off of accuracy, efficacy and scalability in simulations. Furthermore, a pre-/postidentification validation flow will be developed for data/model verification and model
configuration. Statistical methodologies, such as residual analysis and signal-independent error
model analysis, will be used to identify errors, non-linearities and unexpected dynamics. The aim
of this study is to develop prototype simulation methodologies and eventually real-time
simulation methodologies, and accelerate the design process. Developed methodologies can be
integrated into macromodeling tools and circuit simulation tools (e.g. SPICE), for a fully
automated simulation.
C. VLSI Circuits and Systems Education
The focus of chip design is moving to a system-integrated design and front-end/back-end codesign in nanomater CMOS technologies. Therefore, designing chips requires a new and
innovative set of engineering skills and mindset. Based on my experiences in studying first-year
engineering curriculum in HKU, I would like to conduct studies about student development in
VLSI design curriculum. In particular, I am interested to study how integrative project courses
can contribute to the students development of transferable and practical skills. Results from this
study can be used to train contemporary and immediately productive engineers for VLSI R&D
community and promote UM to the national's silicon design centre. We may seek for support
from industries (e.g. NVIDA Academic Partnership Program, Synopsis University Program and
Altera University Program).