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Expalin the block diagram of a typical processor unit with control signals and Arithmetic unit

( Refer pg: 10.38 10.40 and 10.26 10.29 in Godse)

2. Design ALU, Shift register and Shifter with its logic Diagram. (Refer pg: 10.30 -10.38 in
3. Design Simple Computer with its Block diagram. (Refer pg: 10.21 -1010.25 in Godse)
4. Write an HDL program for full adder and 4-bit Comparator (Refer pg: 11.62, 11.67-11.68
Realize the functions given using a PLA with 6 inputs, 4 outputs and 10 AND gates
f1(A,B,C,D,E,F) = m(0,1,7,8,9,10,11,15,19,23,27,31,32,33,35,39,40,41,47,63)
f2(A,B,C,D,E,F) = m(8,9,10,11,12,14,21,25,27,40,41,42,43,44,46,57,59) (Refer pg: 8.42
8.44 in Godse)
8. Draw the circuit of a CMOS two input NAND gate and NOR gate and explain its
(Refer pg: 9.38 9.41 in Godse)
9. Expalin about basic circuit and NOR gate of ECL with its characteristics. (Refer pg: 9.48
9.50 in Godse)
10. Explain about TTL, its wired logic and about the totem pole output, three state output
with its characteristics. (Refer pg: 9.13 9.36 in Godse)
1. Design a combinatorial circuit using ROM and PLA. The circuit accepts 3-bit number and
generates an output binary number equal to square of input number. (Refer pg: S.6, S7 in
2. Write a descriptive note on memories. (Refer pg: 71, 72 in Godse)
3. Discuss on the concept and applications of ROM, PROM and EPROM (Refer pg: 7.2 7.6
4. Discuss on the working of FPGA, PLA, PAL, PROM ( Refer section 8.2,3,4,5 in Godse)
5. Give the comparison between PROM, PLA, and PAL (Refer pg: 8-31 in Godse)
6. Implement the following Boolean function using PAL (Refer pg: 8.19-8.21 in Godse)
W(A,B,C,D) = m(0,2,6,7,8,9,12,13)
x(A,B,C,D) = m(0,2,6,7,8,9,12,13,14)
y(A,B,C,D) = m(2,3,8,9,10,12,13)
z(A,B,C,D) = m(1,3,4,6,9,12,14)
1. Design an asynchronous sequential circuit that has two inputs X1 and X1 and one output Z.
When X1=0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause
output Z to be 1. The output Z will remain 1 until X1 returns to 0. (Refer pg: 6.18-6.21 in
2. Design a pulse mode circuit having two input lines X1 and X2 and one output line Z. The
circuit should produce an output pulse to coincide with the last input pulse in the
X2, X2. No other input sequence should produce an output pulse. (Refer pg: 6.34 6.35 in
3. Draw the state diagram and obtain the primitive flow table for a circuit with two inputs x1
x2 and two outputs z1 and z2 that satisfies the following conditions.
1. When x1x2=00, output z1z2=00.

2. When x1=1 and x2 changes from 0 to 1, the output z1z2=01.

3. When x2=1 and x1 changes from 0 to 1, output z1z2=10.
4. Otherwise output does not change. ( Refer pg: 6.26, 6.27 in Godse)
5. Define the following: i) asynchronous sequential circuits, ii) Cycles, iii) critical race,
iv) non- critical race v) race vi) flow table vii) primitive flow table viii) stable state ( Refer
7. An asynchronous sequential circuit has two internal states and one output. The excitation
output function describing the circuit are as follows.
Z=x2+y1 (refer 6.24 6.26 in Godse)
1. Design a MOD 10 synchronous counter using JK flip-flops. Write the
excitation table and state table. (Refer pg: 5.37, 5.38 in Godse)
2. Design a sequential circuit with four flip-flops ABCD. The next states of B, C, and D
are equal to the present states of A, B, C respectively. The next state of A is equal to
the EX- OR of present states of C and D. (Refer pg: 5.86 in Godse)
3. Design a mod- 7 counter using JK flip-flops. (Refer pg: 5.49 - 5.51 in Godse)
4. Design a BCD Up / Down counter using S R flip-flops. (Refer pg: 5.98 5.102 in Godse)
5. Design a synchronous decade counter using D flip-flops. (Refer pg: 5.92, 5.93 in Godse)

6. Explain the working of JK flip- flop. What is race around condition? How is it
overcome? Explain these concepts with relevant timing diagrams. (Refer pg: 4.13 -4.16 in
7. Design a 3 bit up / down counter using JK flip flops and Explain its working with
diagrams. (Refer pg: 5.42, 5.43 in Godse)
8. Using SR flip-flops design a parallel counter, which counts in the sequence
101,110,001,010,000,111,101(Refer pg: 5.81, 5.82 in Godse)
9. Design a synchronous sequential counter using JK flip-flop and avoid lock out condition,
467314 (Refer pg: 5.28, 5.29 in Godse)
10. Expalin the operation of Master Slave JK flip-flop with suitable diagrams. (Refer 4.17
in Godse)
1. Determine the prime-implicants of the Boolean function by using the tabulation
method(w, x, y, z)=(1,4,6,7,8,9,10,11,15) (Refer pg: 1.62 1.64 in Godse)
2. Simplify the following Boolean expression using Quine McCluskey method:
F=m(0,9,15,24,29,30)+d(8,11,31). (Refer pg : 1.66 1.68 in Godse)
3. Design a combinational logic diagram for BCD to Excess-3 code converter. (Refer pg:
3.36,3.37 in Godse)
4. Find a minimum sum of products expression for the following function using QuineMcClusky method.
F (A,B,C,D,E) = (0,2,3,5,7,9,11,13,14,16,18,24,26,28,30) (Refer pg: 1.62 -1.64 in Godse)
5. Determine the minimum sum of products and minimum product of sums for f =
bcd+bcd+acd+abbcd. (Refer pg: 1.42 & 1.54 in Godse)
6. Find the minterm expansion of f (a, b, c, d) = a (b+d) +acd (Refer notes)

7. Explain with necessary diagram a BCD to 7 segment display decoder. (Refer pg: 3.55
3.59 in
9. With a suitable block diagram explain the operation of BCD adder (Refer pg: 3.20 3.22
10. Draw and explain the working of a carry-look ahead adder. (Refer pg: 3.15 3.18 in
Godse)advantages and disadvantages of Totem pole output?
1. External pull up resistor is not required
2. Operating speed is high

Output of two gates cannot be tied together.
108. Explain the wired And connection?
When the open collector outputs of two or more gates can be connected together, the
connection is called a wired AND.
It is represented as:
1. In wired AND connection, the output is high only when all the switches are open
2. Hence, the output is equivalent to the logical AND operation of the logic function
by the gates.
109. State the advantages and disadvantages of wired AND connection.
Advantage is, Outputs of two gates can be tied together using wired-AND technique.
Disadvantage is, Operating Speed is Low.
How to avoid Lock out Condition?
1. The counter should be provided with an additional circuit. This will force the counter from
an unused state to the next state as initial state.
2. It is not always necessary to force all unused states into an initial state. Because from
states which are not forced, the circuit may eventually arrive at a forced unused state. This
frees the circuit from the Lock out condition.
What are the types of shift register?
1. Serial in serial out shift register? 2. Serial in parallel out shift register 3. Parallel in serial
out shift register 4. Parallel in parallel out shift register 5. Bidirectional shift register shift
95. What are the types of counter?
1. Synchronous counter 2. Asynchronous Counter

96. What are the two models in synchronous sequential circuits.

1. Moore circuit 2. Mealy circuit
97. What is moore circuit?
When the output of the sequential circuit depends only on the present state of the flip-flop,
the sequential circuit is referred to as moore circuit.
98. What is Mealy circuit?
When the output of the sequential circuit depends on both the present state of flip- flop and
on the input, the sequential circuit is referred to as mealy circuit.