CONCORDIA UNIVERSITY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

ELEC 498N and 691N Mixed-Signal VLSI for Communication Systems
Assignment 1
th
Assigned January 27 , 2015. Due February 5th 2015 (noon).
Question 1: An NRZ data stream is measured at the input of a receiver. At the sampling times, the
signal is either +11 mV (representing logic level 1) or 0 mV (representing logic level 0). The
noise is measured to be 1 mVrms. Assuming that the receiver is noiseless, the noise is Gaussian and
signal independent, and that 0s and 1s occur with equal probability, estimate the anticipated bit error
rate. To what level would the noise have to be reduced in order to achieve a BER of 10-11? (Hint: You
may need to iterate to find the noise for this part)
Question 2: Sketch the power spectral density of an NRZ data stream (of random bits) at a bit rate of
10 Gb/s. Compute the power at dc, 5 GHz, 10 GHz, and 15 GHz.
Question 3: Consider a 1st order system with ideal NRZ data applied to its input. Ideal means zero
rise and fall time. Assume input voltage levels of +V0 and V0 for logic levels of 1 and 0,
respectively. Assume that the -3 dB bandwidth of the system is related to the data rate as: Rb = 3 f3dB
where Rb is the data rate in bits/s and f-3dB is the -3 dB bandwidth in Hz. Consider the following two
scenarios related to the issue of eye closure.
a) Below, several consecutive zeros have been applied to the input of the system. At t0, a 1 is
applied, followed by a few more. Determine the output of the system one bit period later. That
is, find: vout(t0+Tb). Express this voltage as a percent of V0.

+V0

vout(t)
vout(t0+Tb)

vin(t)

t
-V0

t0 t0+Tb

b) Below, a repeating 1, 0, 1, 0 pattern has been applied to the input of the system. Determine
vout(t0) and vout(t0+Tb). Express these as a percentage of V0. Hint: Assume that the system has
reached steady state and that vout(t0) = -vout(t0+Tb).

+V0

vin(t)

vout(t)
t

t0

vout(t0)=-vout(t0+Tb)

t0+Tb

c) Which scenario (a or b) causes more eye closure?

Question 4:
Assume the following parameters for the MOSFETs:
nCOX=140 A/V2
pCOX=50 A/V2
Vtn = |Vtp| = 600 mV
=0.1 m/V
Lmin = 0.25 m
VDD = 2.5 V
COX = 4 fF/m2.
In saturation for Lmin, CGD=0.3 * CGS and CDB = CGS. CGS = 23 COX WL
Part a) Find fT for a minimum length transistor in the circuit below:

Id
Ig
Vds
Vgs
Assume the dc gate bias is 1.8 V. You should be able to do this without specifying a particular W for
the transistor. However, if you get stuck, assume W = 5 m.

Part b) Find the low-frequency gain and bandwidth from Vin to Vout for the circuit below:

R
Vout
M1
Vin

M2
Cout

Assume both transistors have W = 5 m and L = 0.25 m. Assume the dc component of Vin = 1.2 V.
R = 1.19 k (assume both resistors are of this value). Ignore channel-length modulation (ro ).
VDD = 1.8 V. Assume that Cout is made up of CGS2/GD2 and CGD1/DB1. Consider the Miller effect on
CGD2. In doing your work, you should find the dc value of the drain current, draw the small-signal
low-frequency equivalent circuit, compute the small-signal parameters and solve for the gain. Then,
use Millers theorem on the CGD capacitors, draw the high-frequency small-signal equivalent circuit
and solve for the bandwidth. Compare the gain and bandwidth with your solution to Part a) and
comment.
Some useful formulae
MOSFETs (N channel, enhancement mode. Strong inversion, Triode):

VGS Vt , VDS VGS Vt or VGS VDS Vt

W
2
I D = n COX (VGS Vt )VDS 0.5VDS
L

MOSFETs (N channel, enhancement mode. Strong inversion, Saturation region):

VGS Vt , VDS VGS Vt or VGS VDS Vt

W
2
I D = 12 n COX (VGS Vt ) (1 + VDS )
L
g m = nCOX

V
W
(VGS Vt ) = 2 nCOX W I D = 2 I D , ro = A , VA = 1
L
L
VGS Vt
ID

'
=
L