1.

Switches that are connected in series with each other are the simplest representation of this logic
gate.
a. NOT gate
b. OR gate
c. AND gate
d. none of the choices
2.
a.
b.
c.
d.

Convert the value 87.410 to base 5.

323.2
313.4
332.4
322.2

3.
a.
b.
c.
d.

It is a digital circuit that has 2n (or fewer) input lines and n output lines.
decoder
multiplexer
encoder
demultiplexer

4.
a.
b.
c.
d.

The Boolean expression (A, B) for the sum (binary adder) of a half adder circuit is
A+B
AB + AB
AB + AB
AB + AB

5.
a.
b.
c.
d.

Determine the difference between 564.257 and 233.456

330.807
197.5810
322.116
none of the choices

6.
a.
b.
c.
d.

Determine the canonical form of the simplified Boolean expression F1 = xyz + xz

m(0, 5, 7)
m(2, 4, 7)
m(0, 2, 3, 7)
m(1, 6, 7)

7. From the given combinational circuit (fig.1), determine the Boolean expression at the output F1.
<no figure>
fig.1
a. AB + AC + BC + ABC
b. ABC + ABC + ABC + ABC
c. (AB + AC + BC) + ABC
d. ABC + ABC + ABC + BC

8.
a.
b.
c.
d.

Evaluate: 2122.113 + 121.759 444.225

142.45
41.4810
31.246
none of the choices

9.
a.
b.
c.
d.

Determine the Boolean expression at the output F2 from the combinational circuit fig. 1
AB + AC + BC + ABC
ABC + ABC + ABC +ABC
AB + AC + BC
ABC + ABC + ABC + BC

10.
a.
b.
c.
d.

A switch that is connected in parallel with the load is the simplest representation of this logic gate.
NOT gate
OR gate
AND gate
none of the choices

11.
a.
b.
c.
d.

How many possible functions can be made from an expression containing 2 variables?
4
32
8
16

12. Determine the essential prime implicants of the function F(A, B, C, D) = m(1, 3, 4, 5, 10, 11, 12, 13,
14, 15)
a. BCD and AC
b. AB and ACD
c. BC and AC
d. ABD and BC
13.
a.
b.
c.
d.

It is the algebraic description of the behavior of a clocked sequential circuit.

input equation
excitation equation
output equation
state equation

14.
a.
b.
c.
d.

From the given combinational circuit (fig.2) determine the Boolean expression at the output F1.
AB + D
ABC + AD + BD
A + BC + BCD + BD
A + BC + BD + BD

15.
a.
b.
c.
d.

Determine the value of 673.1248 in base 2.

11001110011.001011
110111011.001001
110111010.0011001
110111011.0010101

15.
a.
b.
c.
d.

Simplify the Boolean function F(A, B, C, D, E) = (0, 1, 4, 5, 16, 17, 21, 25, 29)
BDE + CD + ABCD
ABD + ADE + BCD
BD + ABD + ABCE
BD + BDE + ABC

16.
a.
b.
c.
d.

From the combinational circuit (fig.2), determine the Boolean expression at F2.
AB + D
ABC + AD + BD
A + BC + BCD + BD
A + BC + BD + BD

17.
a.
b.
c.
d.

The Boolean expression (a, b, c) for the carry (binary adder) of a full adder is
ab + ac + bc
abc + a + b + c
ab + ac + bc
ab + ac + bc

18. Determine the simplified Boolean expression of the function F(A, B, C, D) with F = m(0, 2, 4, 6, 8)
with d(10, 11, 12, 13, 14, 15)
a. A + BC + BD
b. D
c. CD + CD
d. BC + BD + CD
19.
a.
b.
c.
d.

The Boolean expression (A, B, C) for the sum (binary adder) of a full adder circuit is
ABC
ABC + ABC + ABC
A+B+C
ABC + ABC + ABC

20. It is a combinational circuit that selects binary information from one of the many input lines and
directs it to a single output line
a. decoder
b. multiplexer
c. encoder
d. demultiplexer

21.
a.
b.
c.
d.

If the inputs of a NAND gate are tied together as 1 input the gate functions like
an AND gate
an OR gate
a NOT gate
none of the choices

22. Switches that are connected in parallel with each other are the simplest representation of this logic
gate.
a. NOT gate
b. OR gate
c. AND gate
d. none of the choices
23. It is a combinational circuit that converts binary information from n input lies to inputs of a NAND
gate are tied together as 1 input the gate functions like
a. an AND gate
b.
c. a NOT gate
d.
23.
a.
b.
c.
d.

expression a maximum of 2n unique output lines.

decoder
multiplexer
encoder
demultiplexer

24. Determine the simplified Boolean expression of the function F(A, B, C, D) with
F = m(5, 6, 7, 8, 9) with d(10, 11, 12, 13, 14, 15)
a. A + BC + BD
b. BD + BD
c. CD + CD
d. ABC + BD + BCD
25.
a.
b.
c.
d.

The Boolean expression (A, B) for a carry (binary adder) of a half-adder circuit is
A+B
AB
A + B
AB

26. The part of the circuit that generates the inputs to flip-flops is described algebraically by a set of
Boolean functions called
a. output equation
b. transition equation
c. state equation
d. excitation equation

27.
a.
b.
c.
d.

It is a flip-flop that has the characteristic that if the inputs are both 1 it gives a complement output.
S-R flip-flop
D flip-flop
J-K flip-flop
T flip-flop

28. Simplify the Boolean function for T1 from the table 1 to a minimum number of literals.
A
B
C
T1
T2
0
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
Table 1
a. A + BC
b. (A + C) B
c. AB + C
d. A(B +C)
29.
a.
b.
c.
d.

Determine the canonical form of the simplified Boolean expression F2 = xyz + xy

m(0, 5, 7)
m(2, 4, 7)
m(2, 3, 4)
m(1, 6, 7)

30.
a.
b.
c.
d.

Determine the product of 1101 and 1011 is

14310
2078
8E16
101001112

31. Determine the simplified Boolean expression of the function F(A, B, C, D) with F = m(0, 3, 4, 7, 8)
with d(10, 11, 12, 13, 14, 15)
a. (A + BC + BD)
b. D + D
c. CD + CD
d. BC + BD + BCD
32. What is the canonical form of the simplified function F = xy + yz + xyz
a. M(0, 1, 3, 5)
b. M(1, 3, 4, 6)
c. M(3, 5, 6, 7)
d. M(0, 1, 2, 4)

33. Determine the essential prime implicants of the function F(w, x, y, z) = (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
a. xyz and wy
b. xz and xz
c. xyz and wy
d. wx and wz
34.
a.
b.
c.
d.

Simplify the Boolean function for T2 from the table 1 to a minimum number of literals.
A + BC
(A + C) B
AB + C
A(B + C)

35. It is a flow graph that that enumerates the sequence of operation together with the conditions
necessary for their execution.
a. Flow chart
b. ASM chart
c. Sequence control chart
d. none of the choices
36.
a.
b.
c.
d.

It is a circular shift register with table 1 to a minimum number of literals.

A + BC
(A + C) B
AB + C
A(B + C)

35. It is a flow graph that that enumerates the sequence of operation together with the conditions
necessary for their execution.
a. Flow chart
b. ASM chart
c. Sequence control chart
d. none of the choices
36.
a.
b.
c.
d.

It is a only 1 flip-flop being set at any particular time, all others are cleared.
BCD counter
binary ripple counter
up-down counter
ring counter

37.
a.
b.
c.
d.

the quotient from 100100012 / 1012

10111
10110
11001
11101

38.
a.
b.
c.
d.

Simplify the Boolean function F(A, B, C, D) with F = m(0, 6, 8, 13, 14) with d(2, 4, 10)
ABD + BC + BCD
BD + CD + ABCD
ABD + ABD + BCD
ABC + BD + BCD

39. It is a cascade of interconnected chain of flip-flops with the output of one flip-flop connected to the
input of the next flip-flop and all the flip-flops receives a common clock pulse.
a. BCD counter
b. binary ripple counter
c. up-down counter
d. shift register
40.
a.
b.
c.
d.

It is a flip-flop that has the characteristic that if the inputs are both 1 it gives an invalid output.
S-R flip-flop
D flip-flop
J-K flip-flop
T flip-flop

41. It is a table that defines the logical properties of a flip-flop by describing its operation in tabular
form.
a. State Table
b. Sequence Table
c. Excitation table
d. Characteristic table
42. It is a clocked sequential circuit consisting of n flip-flops and is capable of storing n-bits of
information.
a. counter
b. memory
c. register
d. none of the choices
43.
a.
b.
c.
d.

Determine the product of 1110 and 10

11100
10100
10011
overflow

44.
a.
b.
c.
d.

What is the canonical form of the simplified function F = CD + ABC + ABD + AB

M (1, 2, 3, 5, 9, 11,12, 13, 14)
M(1, 3, 4, 5, 6, 7, 9, 10, 12, 14, 15)
M(0, 2, 4, 6, 7, 8, 10, 11, 15)
M(1, 3, 5, 9,12, 13, 14)

45.
a.
b.
c.
d.

It is a table that contains the enumerated timing sequence of inputs, outputs and flip-flop states.
Sequence Table
State Table
Characteristic table
Excitation table

46.
a.
b.
c.
d.

Determine the canonical form of the simplified Boolean expression F3 = xyz + xy

m(0, 5, 7)
m(2, 4, 7)
m(2, 3, 7)
m(1, 6, 7)

47.
a.
b.
c.
d.

If the inputs of a NOR gate are inverted the gate function like
an AND gate
an OR gate
a NOT gate
none of the choices

48.
a.
b.
c.
d.

The maximum value number of addresses available for FFF16 is

256
1024
32
64

49. It consists of a series of connection of complementing flip-flops, with the output of each flip-flop
connected to the C input of the next higher order flip-flop and goes through a prescribed sequence of
transition.
a. BCD counter
b. binary ripple counter
c. up-down counter
d. ring counter
50.
a.
b.
c.
d.

How many 2 x 4 decoders are needed to create a decoder with 4 inputs and 16 outputs?
2
4
6
8