fuigfrwv wgwvrgvwrghRelease 14.6 - xst P.

68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.06 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Reading design: bisrfeb2.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
*
Synthesis Options Summary
*
=========================================================================
---- Source Parameters
Input File Name
: "bisrfeb2.prj"
Input Format
: mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name
Output Format
Target Device

: "bisrfeb2"
: NGC
: xc3s1600e-4-fg320

---- Source Options

Top Module Name
Automatic FSM Extraction
FSM Encoding Algorithm
Safe Implementation
FSM Style
RAM Extraction
RAM Style
ROM Extraction
Mux Style
Decoder Extraction
Priority Encoder Extraction
Shift Register Extraction
Logical Shifter Extraction

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:

bisrfeb2
YES
Auto
No
LUT
Yes
Auto
Yes
Auto
YES
Yes
YES
YES

XOR Collapsing
ROM Style
Mux Extraction
Resource Sharing
Asynchronous To Synchronous
Multiplier Style
Automatic Register Balancing

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:

YES
Auto
Yes
YES
NO
Auto
No

---- Target Options

Add IO Buffers
Global Maximum Fanout
Add Generic Clock Buffer(BUFG)
Register Duplication
Slice Packing
Optimize Instantiated Primitives
Use Clock Enable
Use Synchronous Set
Use Synchronous Reset
Pack IO Registers into IOBs
Equivalent register Removal

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YES
100000
24
YES
YES
NO
Yes
Yes
Yes
Auto
YES

---- General Options

Optimization Goal
Optimization Effort
Keep Hierarchy
Netlist Hierarchy
RTL Output
Global Optimization
Read Cores
Write Timing Constraints
Cross Clock Analysis
Hierarchy Separator
Bus Delimiter
Case Specifier
Slice Utilization Ratio
BRAM Utilization Ratio
Verilog 2001
Auto BRAM Packing
Slice Utilization Ratio Delta

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:

Speed
1
No
As_Optimized
Yes
AllClockNets
YES
NO
NO
/
<>
Maintain
100
100
YES
NO
5

=========================================================================
=========================================================================
*
HDL Compilation
*
=========================================================================
Compiling vhdl file "D:/new/feb/bisrfeb2.vhd" in Library work.
Architecture behavioral of Entity bisrfeb2 is up to date.
=========================================================================
*
Design Hierarchy Analysis
*
=========================================================================
Analyzing hierarchy for entity <bisrfeb2> in library <work> (architecture <behav
ioral>).
=========================================================================
*
HDL Analysis
*
=========================================================================
Analyzing Entity <bisrfeb2> in library <work> (Architecture <behavioral>).

WARNING:Xst:790 - "D:/new/feb/bisrfeb2.vhd" line 98: Index value(s) does not mat

ch array range, simulation mismatch.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
WARNING:Xst:790 - "D:/new/feb/bisrfeb2.vhd" line 101: Index value(s) does not ma
tch array range, simulation mismatch.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1607 - Contents of array <contents> may be accessed with an index that
does not cover the full array size.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1433 - Contents of array <contents> may be accessed with an index that
exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1432 - Contents of array <contents> may be accessed with a negative ind
ex, causing simulation mismatch.
INFO:Xst:1433 - Contents of array <contents> may be accessed with an index that
exceeds the array size. This could cause simulation mismatch.
INFO:Xst:1432 - Contents of array <loca> may be accessed with a negative index,
causing simulation mismatch.
INFO:Xst:1433 - Contents of array <loca> may be accessed with an index that exce
eds the array size. This could cause simulation mismatch.
INFO:Xst:1432 - Contents of array <loca> may be accessed with a negative index,
causing simulation mismatch.
INFO:Xst:1433 - Contents of array <loca> may be accessed with an index that exce
eds the array size. This could cause simulation mismatch.
Entity <bisrfeb2> analyzed. Unit <bisrfeb2> generated.
=========================================================================
*
HDL Synthesis
*
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <bisrfeb2>.
Related source file is "D:/new/feb/bisrfeb2.vhd".
WARNING:Xst:646 - Signal <m<9:5>> is assigned but never used. This unconnected s
ignal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <loca> is assigned but never used. This unconnected sig
nal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <fail<31:9>> is assigned but never used. This unconnect
ed signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <col_loca<0>> is assigned but never used. This unconnec
ted signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <col_loca<1:20>> is never used or assigned. This uncon
nected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <bit_loca<0>> is assigned but never used. This unconnec
ted signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <bit_loca<1:20>> is never used or assigned. This uncon
nected signal will be trimmed during the optimization process.
INFO:Xst:1439 - HDL ADVISOR - You may have used signed signal(s) to address this
RAM. If that is the case, negative values being out of range, sign bits were ig
nored. As a result only the first half of the RAM is actually accessed. Please c
heck your source code.
Found 21x5-bit single-port RAM <Mram_loca> for signal <loca>.
Using one-hot encoding for signal <pr_state>.
Found 8-bit register for signal <dataout>.
Found 1-bit register for signal <col_rep>.
Found 9-bit 301-to-1 multiplexer for signal <contents_0$varindex0000> create
d at line 654.
Found 32-bit register for signal <err>.
Found 32-bit adder for signal <err$share0000> created at line 91.
Found 32-bit register for signal <fail>.
Found 32-bit 4-to-1 multiplexer for signal <fail$mux0001>.
Found 32-bit 4-to-1 multiplexer for signal <fail$mux0002>.
Found 1-bit register for signal <fault>.
Found 8-bit register for signal <i>.
Found 8-bit addsub for signal <i$share0000> created at line 91.
Found 10-bit register for signal <j>.
Found 9-bit adder for signal <j$add0000> created at line 127.
Found 9-bit subtractor for signal <j$sub0000> created at line 197.
Found 10-bit register for signal <k>.
Found 9-bit adder for signal <k$add0000> created at line 166.
Found 32-bit up counter for signal <l>.
Found 8-bit register for signal <mem_bus>.
Found 1-bit 8-to-1 multiplexer for signal <mem_bus$mux0002> created at line
165.
Found 9-bit 301-to-1 multiplexer for signal <mem_bus$varindex0000> created a
t line 101.
Found 9-bit 301-to-1 multiplexer for signal <mem_bus$varindex0001> created a
t line 124.
Found 9-bit 301-to-1 multiplexer for signal <mem_bus$varindex0002> created a
t line 233.
Found 10-bit comparator greater for signal <mux0001$cmp_gt0000> created at l
ine 118.
Found 10-bit comparator less for signal <mux0001$cmp_lt0000> created at line
190.
Found 17-bit register for signal <Next_State>.
Found 32-bit comparator greater for signal <Next_State$cmp_gt0000> created a
t line 176.
Found 32-bit comparator less for signal <Next_State$cmp_lt0000> created at l

ine 177.
Found 17-bit register for signal <pr_state>.
Found 1-bit register for signal <rep>.
Found 32-bit register for signal <s>.
Found 32-bit adder for signal <s$addsub0000>.
Found 1-bit register for signal <t>.
INFO:Xst:738 - HDL ADVISOR - 2709 flip-flops were inferred for signal <contents>
. You may be trying to describe a RAM in a way that is incompatible with block a
nd distributed RAM resources available on Xilinx devices, or with a specific tem
plate that is not supported. Please review the Xilinx resources documentation an
d the XST user manual for coding guidelines. Taking advantage of RAM resources w
ill lead to improved device usage and reduced synthesis time.
Summary:
inferred 1 RAM(s).
inferred 1 Counter(s).
inferred 2870 D-type flip-flop(s).
inferred 6 Adder/Subtractor(s).
inferred 4 Comparator(s).
inferred 101 Multiplexer(s).
Unit <bisrfeb2> synthesized.
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmet
ic operations in this design can share the same physical resources for reduced d
evice utilization. For improved clock frequency you may try to disable resource
sharing.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
32-bit adder
8-bit addsub
9-bit adder
9-bit subtractor
# Counters
32-bit up counter
# Registers
1-bit register
10-bit register
17-bit register
32-bit register
8-bit register
# Comparators
10-bit comparator greater
10-bit comparator less
32-bit comparator greater
32-bit comparator less
# Multiplexers
1-bit 8-to-1 multiplexer
32-bit 4-to-1 multiplexer
9-bit 301-to-1 multiplexer

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6
2
1
2
1
1
1
2723
2713
2
2
3
3
4
1
1
1
1
7
1
2
4

=========================================================================
=========================================================================
*
Advanced HDL Synthesis
*
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch rep hinder the constant cleani

ng in the block bisrfeb2.

You should achieve better results
WARNING:Xst:1426 - The value init of
in the block bisrfeb2.
You should achieve better results
WARNING:Xst:1426 - The value init of
eaning in the block bisrfeb2.
You should achieve better results

by setting this init to 1.

the FF/Latch t hinder the constant cleaning
by setting this init to 1.
the FF/Latch col_rep hinder the constant cl
by setting this init to 1.

=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors
32-bit adder
8-bit addsub
9-bit adder
9-bit subtractor
# Counters
32-bit up counter
# Registers
Flip-Flops
# Comparators
10-bit comparator greater
10-bit comparator less
32-bit comparator greater
32-bit comparator less
# Multiplexers
1-bit 8-to-1 multiplexer
32-bit 4-to-1 multiplexer
9-bit 301-to-1 multiplexer

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5
1
1
2
1
1
1
2855
2855
4
1
1
1
1
7
1
2
4

=========================================================================
=========================================================================
*
Low Level Synthesis
*
=========================================================================
WARNING:Xst:1426 - The value init of the FF/Latch rep hinder the constant cleani
ng in the block bisrfeb2.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch t hinder the constant cleaning
in the block bisrfeb2.
You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch col_rep hinder the constant cl
eaning in the block bisrfeb2.
You should achieve better results by setting this init to 1.
WARNING:Xst:1293 - FF/Latch <Next_State_6> has a constant value of 0 in block <b
isrfeb2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Next_State_8> has a
constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during t
he optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Next_State_10> has
a constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during
the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Next_State_12> has
a constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during
the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Next_State_14> has
a constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during
the optimization process.

WARNING:Xst:2677
rfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
srfeb2>.
WARNING:Xst:2677
b2>.
WARNING:Xst:2677
eb2>.
WARNING:Xst:2677
eb2>.
WARNING:Xst:2677
eb2>.
WARNING:Xst:2677
eb2>.
WARNING:Xst:2677
eb2>.
WARNING:Xst:2677
eb2>.

- Node <fail_9> of sequential type is unconnected in block <bis

- Node <fail_10> of sequential type is unconnected in block <bi
- Node <fail_11> of sequential type is unconnected in block <bi
- Node <fail_12> of sequential type is unconnected in block <bi
- Node <fail_13> of sequential type is unconnected in block <bi
- Node <fail_14> of sequential type is unconnected in block <bi
- Node <fail_15> of sequential type is unconnected in block <bi
- Node <fail_16> of sequential type is unconnected in block <bi
- Node <fail_17> of sequential type is unconnected in block <bi
- Node <fail_18> of sequential type is unconnected in block <bi
- Node <fail_19> of sequential type is unconnected in block <bi
- Node <fail_20> of sequential type is unconnected in block <bi
- Node <fail_21> of sequential type is unconnected in block <bi
- Node <fail_22> of sequential type is unconnected in block <bi
- Node <fail_23> of sequential type is unconnected in block <bi
- Node <fail_24> of sequential type is unconnected in block <bi
- Node <fail_25> of sequential type is unconnected in block <bi
- Node <fail_26> of sequential type is unconnected in block <bi
- Node <fail_27> of sequential type is unconnected in block <bi
- Node <fail_28> of sequential type is unconnected in block <bi
- Node <fail_29> of sequential type is unconnected in block <bi
- Node <fail_30> of sequential type is unconnected in block <bi
- Node <fail_31> of sequential type is unconnected in block <bi
- Node <l_9> of sequential type is unconnected in block <bisrfe
- Node <l_10> of sequential type is unconnected in block <bisrf
- Node <l_11> of sequential type is unconnected in block <bisrf
- Node <l_12> of sequential type is unconnected in block <bisrf
- Node <l_13> of sequential type is unconnected in block <bisrf
- Node <l_14> of sequential type is unconnected in block <bisrf
- Node <l_15> of sequential type is unconnected in block <bisrf

WARNING:Xst:2677 - Node <l_16> of sequential type is unconnected in block <bisrf

eb2>.
WARNING:Xst:2677 - Node <l_17> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_18> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_19> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_20> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_21> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_22> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_23> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_24> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_25> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_26> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_27> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_28> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_29> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_30> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:2677 - Node <l_31> of sequential type is unconnected in block <bisrf
eb2>.
WARNING:Xst:1293 - FF/Latch <Next_State_7> has a constant value of 0 in block <b
isrfeb2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Next_State_9> has a
constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during t
he optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Next_State_11> has
a constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during
the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <Next_State_13> has
a constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during
the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_14> has a
constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during th
e optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_12> has a
constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during th
e optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_10> has a
constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during th
e optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_8> has a c
onstant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during the
optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_6> has a c
onstant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during the
optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_13> has a
constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during th

e optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_11> has a
constant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during th
e optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_9> has a c
onstant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during the
optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_7> has a c
onstant value of 0 in block <bisrfeb2>. This FF/Latch will be trimmed during the
optimization process.
Optimizing unit <bisrfeb2> ...
WARNING:Xst:1293 - FF/Latch <k_9> has
This FF/Latch will be trimmed during
WARNING:Xst:1293 - FF/Latch <k_9> has
This FF/Latch will be trimmed during

a constant value
the optimization
a constant value
the optimization

of 0 in block <bisrfeb2>.
process.
of 0 in block <bisrfeb2>.
process.

Mapping all equations...

Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block bisrfeb2, actual ratio is 44.
FlipFlop fault has been replicated 1 time(s)
FlipFlop i_0 has been replicated 1 time(s)
FlipFlop i_1 has been replicated 2 time(s)
FlipFlop i_3 has been replicated 1 time(s)
FlipFlop i_4 has been replicated 2 time(s)
FlipFlop i_5 has been replicated 1 time(s)
FlipFlop i_7 has been replicated 1 time(s)
FlipFlop j_0 has been replicated 1 time(s)
FlipFlop j_1 has been replicated 2 time(s)
FlipFlop j_2 has been replicated 2 time(s)
FlipFlop j_3 has been replicated 2 time(s)
FlipFlop j_4 has been replicated 1 time(s)
FlipFlop j_5 has been replicated 1 time(s)
FlipFlop j_6 has been replicated 1 time(s)
FlipFlop j_7 has been replicated 2 time(s)
FlipFlop j_8 has been replicated 2 time(s)
FlipFlop j_9 has been replicated 1 time(s)
FlipFlop l_5 has been replicated 1 time(s)
FlipFlop l_7 has been replicated 1 time(s)
FlipFlop pr_state_1 has been replicated 1 time(s)
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers
Flip-Flops

: 2849
: 2849

=========================================================================
=========================================================================
*
Partition Report
*
=========================================================================
Partition Implementation Status
------------------------------No Partitions were found in this design.

------------------------------=========================================================================
*
Final Report
*
=========================================================================
Final Results
RTL Top Level Output File Name
: bisrfeb2.ngr
Top Level Output File Name
: bisrfeb2
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: No
Design Statistics
# IOs

: 29

Cell Usage :
# BELS
: 17360
#
GND
: 1
#
INV
: 18
#
LUT1
: 58
#
LUT2
: 25
#
LUT2_D
: 23
#
LUT2_L
: 11
#
LUT3
: 5368
#
LUT3_D
: 219
#
LUT3_L
: 83
#
LUT4
: 4095
#
LUT4_D
: 685
#
LUT4_L
: 2251
#
MUXCY
: 84
#
MUXF5
: 2377
#
MUXF6
: 1151
#
MUXF7
: 562
#
MUXF8
: 280
#
VCC
: 1
#
XORCY
: 68
# FlipFlops/Latches
: 2849
#
FDC
: 8
#
FDE
: 2840
#
FDP
: 1
# Clock Buffers
: 1
#
BUFGP
: 1
# IO Buffers
: 28
#
IBUF
: 20
#
OBUF
: 8
=========================================================================
Device utilization summary:
--------------------------Selected Device : 3s1600efg320-4
Number
Number
Number
Number
Number
Number

of
of
of
of
of
of

Slices:
Slice Flip Flops:
4 input LUTs:
IOs:
bonded IOBs:
GCLKs:

6528
2849
12836
29
29
1

out of 14752
out of 29504
out of 29504

44%
9%
43%

out of
out of

11%
4%

250
24

--------------------------Partition Resource Summary:

--------------------------No Partitions were found in this design.
--------------------------=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Clk
| BUFGP
| 2849 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
--------------------------------------------------------------------------+------------------------+-------+
Control Signal
| Buffer(FF name)
| Load |
-----------------------------------+------------------------+-------+
rst
| IBUF
| 9
|
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -4
Minimum
Minimum
Maximum
Maximum

period: 11.099ns (Maximum Frequency: 90.102MHz)

input arrival time before clock: 13.358ns
output required time after clock: 4.283ns
combinational path delay: No path found

Timing Detail:
-------------All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'Clk'
Clock period: 11.099ns (frequency: 90.102MHz)
Total number of paths / destination ports: 2063662 / 3168
------------------------------------------------------------------------Delay:
11.099ns (Levels of Logic = 7)
Source:
j_5_1 (FF)
Destination:
contents<4>_4 (FF)
Source Clock:
Clk rising
Destination Clock: Clk rising
Data Path: j_5_1 to contents<4>_4
Gate
Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------

FDE:C->Q
LUT3:I0->O
LUT3_D:I2->O
LUT4:I3->O

3
7
13
2

0.591
0.704
0.704
0.704

0.706
0.743
0.987
0.526

j_5_1 (j_5_1)
fail_cmp_eq000011 (N938)
mem_bus_cmp_eq000021 (N1026)
mem_bus_and00011_1 (mem_bus_and000

11)
LUT4_D:I1->O
299 0.704 1.351 _mux0882211 (N988)
LUT4:I3->O
1 0.704 0.424 _mux132641_SW0 (N9698)
LUT4_D:I3->O
3 0.704 0.535 _mux132641 (N2991)
LUT4:I3->O
1 0.704 0.000 _mux1338 (_mux1338)
FDE:D
0.308
contents<4>_6
---------------------------------------Total
11.099ns (5.827ns logic, 5.272ns route)
(52.5% logic, 47.5% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Clk'
Total number of paths / destination ports: 52745 / 5258
------------------------------------------------------------------------Offset:
13.358ns (Levels of Logic = 9)
Source:
maddr<2> (PAD)
Destination:
contents<141>_0 (FF)
Destination Clock: Clk rising
Data Path: maddr<2> to contents<141>_0
Gate
Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
36 1.218 1.438 maddr_2_IBUF (maddr_2_IBUF)
LUT2:I0->O
8 0.704 0.932 mux0008_cmp_eq000021 (N3461)
LUT4:I0->O
15 0.704 1.096 mux0277_cmp_eq000011 (N4401)
LUT4:I1->O
9 0.704 0.995 mux0277_cmp_eq00002 (mux0277_cmp_e
q0000)
LUT4:I0->O
1 0.704 0.424 _mux0277313 (_mux0277313)
LUT4:I3->O
1 0.704 0.499 _mux0277321 (_mux0277321)
LUT4_D:I1->O
7 0.704 0.712 _mux0277354 (N3010)
LUT4_L:I3->LO
1 0.704 0.104 _mux0299_SW0_SW0 (N5932)
LUT4:I3->O
1 0.704 0.000 _mux0299 (_mux0299)
FDE:D
0.308
contents<141>_6
---------------------------------------Total
13.358ns (7.158ns logic, 6.200ns route)
(53.6% logic, 46.4% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'
Total number of paths / destination ports: 8 / 8
------------------------------------------------------------------------Offset:
4.283ns (Levels of Logic = 1)
Source:
dataout_7 (FF)
Destination:
dataout<7> (PAD)
Source Clock:
Clk rising
Data Path: dataout_7 to dataout<7>
Gate
Net
Cell:in->out
fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDE:C->Q
1 0.591 0.420 dataout_7 (dataout_7)
OBUF:I->O
3.272
dataout_7_OBUF (dataout<7>)
---------------------------------------Total
4.283ns (3.863ns logic, 0.420ns route)
(90.2% logic, 9.8% route)

=========================================================================
Total REAL time to Xst completion: 612.00 secs
Total CPU time to Xst completion: 611.14 secs
-->
Total memory usage is 1149840 kilobytes
Number of errors :
Number of warnings :
Number of infos
:

0 (
81 (
28 (

0 filtered)
0 filtered)
0 filtered)

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