74HC04

Hex Inverter
HighPerformance SiliconGate CMOS
The 74HC04 is identical in pinout to the LS04 and the MC14069.
The device inputs are compatible with Standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs.
The device consists of six threestage inverters.

http://onsemi.com
MARKING
DIAGRAMS

Features

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 36 FETs or 9 Equivalent Gates
These are PbFree Devices
LOGIC DIAGRAM
A1

A2

A3

A5

11

10

13

12

SOIC14
D SUFFIX
CASE 751A

14
1

HC04G
AWLYWW
1

14
14
1

TSSOP14
DT SUFFIX
CASE 948G
1

Y1

Y2

HC
04
ALYW G
G

HC04
= Device Code
A
= Assembly Location
WL or L = Wafer Lot
Y
= Year
WW or W = Work Week
G or G
= PbFree Package
(Note: Microdot may be in either location)

Y3
Y=A

A4

14

Y4

Y5

FUNCTION TABLE
A6

Inputs

Y6

Pinout: 14Lead Packages (Top View)

VCC

A6

Y6

A5

Y5

A4

Y4

14

13

12

11

10

Outputs

L
H

H
L

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

A1

Y1

A2

Y2

A3

Y3

GND

Semiconductor Components Industries, LLC, 2007

March, 2007 Rev. 1

Publication Order Number:

74HC04/D

74HC04

MAXIMUM RATINGS
Symbol

Parameter

Value

Unit

0.5 to + 7.0

DC Input Voltage (Referenced to GND)

0.5 to VCC + 0.5

DC Output Voltage (Referenced to GND)

0.5 to VCC + 0.5

VCC

DC Supply Voltage (Referenced to GND)

Vin
Vout
Iin

DC Input Current, per Pin

20

mA

Iout

DC Output Current, per Pin

25

mA

ICC

DC Supply Current, VCC and GND Pins

PD

Power Dissipation in Still Air,

Tstg

Storage Temperature

TL

Lead Temperature, 1 mm from Case for 10 Seconds

50

mA

500
450

mW

65 to + 150

_C

SOIC Package
TSSOP Package

_C

SOIC or TSSOP Package

260

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be
taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and
Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either GND or VCC). Unused outputs must be left open.
Derating SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol
VCC
Vin, Vout

Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time

(Figure 1)

VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V

Min

Max

Unit

2.0

6.0

VCC

55

+ 125

_C

0
0
0

1000
500
400

ns

ORDERING INFORMATION
Package

Shipping

SOIC14
(PbFree)

2500 / Tape & Reel

Device
74HC04DR2G
74HC04DTR2G

TSSOP14*

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.

http://onsemi.com
2

74HC04
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol

Parameter

Condition

Guaranteed Limit

VCC
(V)

55 to 25C

85C

125C

Unit

VIH

Minimum HighLevel Input

Voltage

Vout = 0.1V or VCC 0.1V

|Iout| 20mA

2.0
3.0
4.5
6.0

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

1.50
2.10
3.15
4.20

VIL

Maximum LowLevel Input

Voltage

Vout = 0.1V or VCC 0.1V

|Iout| 20mA

2.0
3.0
4.5
6.0

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

0.50
0.90
1.35
1.80

VOH

Minimum HighLevel Output

Voltage

Vin = VIH or VIL

|Iout| 20mA

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

3.0
4.5
6.0

2.48
3.98
5.48

2.34
3.84
5.34

2.20
3.70
5.20

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

3.0
4.5
6.0

0.26
0.26
0.26

0.33
0.33
0.33

0.40
0.40
0.40

Vin =VIH or VIL

VOL

Maximum LowLevel Output

Voltage

|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA

Vin = VIH or VIL

|Iout| 20mA
Vin = VIH or VIL

|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA

Iin

Maximum Input Leakage

Current

Vin = VCC or GND

6.0

0.1

1.0

1.0

mA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0mA

6.0

2.0

20

40

mA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Symbol

Parameter

Guaranteed Limit

VCC
(V)

55 to 25C

85C

125C

Unit

tPLH,
tPHL

Maximum Propagation Delay, Input A or B to Output Y

(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
30
15
13

95
40
19
16

110
55
22
19

ns

tTLH,
tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 2)

2.0
3.0
4.5
6.0

75
27
15
13

95
32
19
16

110
36
22
19

ns

10

10

10

pF

Cin

Maximum Input Capacitance

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD

20

Power Dissipation Capacitance (Per Inverter)*

* Used to determine the noload dynamic power consumption: PD = CPD VCC

ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

2f + I

http://onsemi.com
3

CC

pF

VCC . For load considerations, see Chapter 2 of the

74HC04
tf
INPUT A

tr
VCC

90%
50%
10%

GND

tPLH

tPHL
90%

OUTPUT Y

50%
10%
tTHL

tTLH

Figure 1. Switching Waveforms

TEST
POINT
OUTPUT
DEVICE
UNDER
TEST

C L*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

Figure 3. Expanded Logic Diagram

(1/6 of the Device Shown)

http://onsemi.com
4

74HC04
PACKAGE DIMENSIONS
SOIC14
CASE 751A03
ISSUE H

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

A
14

P 7 PL
0.25 (0.010)

T
D 14 PL
0.25 (0.010)

T B

DIM
A
B
C
D
F
G
J
K
M
P
R

K
M

R X 45 _

SEATING
PLANE

SOLDERING FOOTPRINT*
7X

7.04

14X

1.52
1
14X

0.58

1.27
PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our PbFree strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com
5

MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019

74HC04
PACKAGE DIMENSIONS

TSSOP14
CASE 948G01
ISSUE B

14X K REF

0.10 (0.004)
0.15 (0.006) T U

T U

N
2X

14

L/2

0.25 (0.010)

M
B
U

L
PIN 1
IDENT.

N
F

0.15 (0.006) T U

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.

DETAIL E

A
V

K1

J J1

DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M

SECTION NN
W

C
0.10 (0.004)
T SEATING
PLANE

DETAIL E

SOLDERING FOOTPRINT*
7.06
1

0.65
PITCH

14X

0.36

14X

1.26

DIMENSIONS: MILLIMETERS

*For additional information on our PbFree strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

http://onsemi.com
6

MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50

1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_

INCHES
MIN MAX
0.193 0.200
0.169 0.177
0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_

74HC04

ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: orderlit@onsemi.com

N. American Technical Support: 8002829855 Toll Free

USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81357733850

http://onsemi.com
7

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative

74HC04/D