Digital Circuits and Systems

Unit 3
Combinational Integrated Circuits

COMBINATIONAL ICs
REPRESENTATION OF BINARY VARIABLES AT THE PHYSICAL LEVEL
BASIC SWITCH. STRUCTURE OF GATES AND THEIR OPERATION
REALIZATION OF GATES USING cmos CIRCUITS

CHARACTERISTICS OF CIRCUITS: LOAD FACTORS AND FANOUT FACTORS, P

AGATION DELAYS, TRANSITION TIMES, AND EFFECT OF LOAD
THREE-STATE GATES (DRIVERS) AND BUSES
NOISE AND NOISE MARGINS
EVOLUTION OF ICs. VLSI CIRCUIT-LEVEL DESIGN STYLES
PACKAGING LEVELS: CHIPS, BOARDS AND CABINETS.

REPRESENTATION OF BINARY VARIABLES

REPRESENTATION OF 0 AND 1 BY ELECTRICAL SIGNALS

VOLTAGES
CURRENTS
ELECTRICAL CHARGES
REALIZATION OF CIRCUITS THAT OPERATE ON THESE SIGNALS TO
IMPLEMENT DESIRED SWITCHING FUNCTIONS
TYPICAL VALUES FOR A 3.3V cmos TECHNOLOGY
VHmax 3.3V VLmax 0.8V
VHmin 2.0V VLmin 0.0V

VOLTAGE REGIONS

voltage
V

Hmax

H region

Hmin

Forbidden region
V
V

Lmax

V
Lmin

L region

Figure 3.1: VOLTAGE REGIONS.

POSITIVE AND NEGATIVE LOGIC

POSITIVE LOGIC
VH 1
VL 0
NEGATIVE LOGIC
VH 0
VL 1

Input
Output
x y
z
voltagesvoltage

VL VL
VL V H

VH VL
VH V H

VL
VL
VL
VH

Positive
logic
x y z
0 0 0
0 1 0
1 0 0
1 1 1
0
f =and

Negative
logic
x y z
1 1 1
1 0 1
0 1 1
0 0
f =or

STRUCTURE AND OPERATION OF GATES

SWITCH AND mos TRANSISTORS

N-TYPE:
open (off) if VCA < VT n
closed (on) if VCA > VT n
VT n - THE THRESHOLD VOLTAGE FOR N-TYPE SWITCH

P-TYPE:
open (off) if VBC > Vdd - |VT p|
closed (on) if VBC < Vdd - |VT p|
VT p - THE THRESHOLD VOLTAGE FOR P-TYPE SWITCH

V
Tn

V
BC

V
n-type switch
CA
Resistance between A and B
very low: sw itch CLOSED (on)

p-type switch
Resistance between A and B
very low: switch CLOSED (on)

V
Tp

Resistance between A and B

very high: sw itch OPEN (off)

Resistance between A and B

very high: switch OPEN (off)

B
+

V
CA

V
BC
-

nS

C
-

(a)

A
logical
symbol

logical
symbol

PMOS transistor
B

drain

source

C
gate

gate source
A

pS

NMOS transistor

+ B

drain

C A
(b)

Figure 3.3: a) N-TYPE AND P-TYPE CONTROLLED SWITCHES. b) nmos AND pmos TRANSISTORS.

THE INVERTERS

DIGITAL GATES
Fundamental Parameters

Functionality

Reliability, Robustness

Area

Performance

Speed (delay)

Power Consumption

Energy

Noise in Digital Integrated Circuits

v(t)

VDD

i(t)

(a) Inductive coupling

(b) Capacitive coupling

(c) Power and ground

noise

DC Operation:
Voltage Transfer Characteristic
V(y)

V(x)
f

OH

V(y)=V(x)

Switching Threshold
M

VOL

VOL

OH

V(x)

Nominal Voltage Levels

V(y)

Mapping between analog and digital signals

"1"

V
OH
V
IH

V(y)
V

Slope = -1
OH

Undefined
Region

"0"

V
IL
V
OL

Slope = -1
VOL
V

IL

IH

V(x)

Definition of Noise Margins

"1"
V
OH

NMH

Noise Margin High

Noise Margin Low

NML

V
OL

V
IH
Undefined
Region
V

IL

"0"
Gate Output

Gate Input

Fan-in and Fan-out

(a) Fan-out N

M
N

(b) Fan-in M

The Ideal Gate

Vout

Ri =
Ro = 0
g=
Vin

VTC of Real Inverter

5.0

Vout (V)

4.0

NML

3.0
2.0

VM

1.0
0.0

1.0

NMH

2.0
3.0
Vin (V)

4.0

5.0

Delay Definitions
Vin

50%
t
t
Vout

pHL

pLH
90%

50%
10%

tf

tr

Power Dissipation

CMOS INVERTER

The CMOS Inverter:

A First
Glance
V
DD

Vin

Vout
CL

Switch Model of CMOS Transistor

|V GS|

Ron

|VGS| < |VT|

|VGS| > |VT|

CMOS Inverter: Steady State Response

VDD

VDD

Ron

VOH = VDD
Vout

Vout

VM = f(R onn,Ronp)

Ron

Vin = V DD

VOL= 0

Vin = 0

CMOS Inverter: Transient Response

V DD

tpHL = f(R on.CL)

= 0.69 RonCL
V out
CL
Ron

Vout
1

ln(0.5)

VDD

0.5
0.36

Vin = V DD
RonCL

CMOS Properties

Full rail-to-rail swing

Symmetrical VTC

Propagation delay function of load capacitance and

resistance of transistors

No static power dissipation

Direct path current during switching

The Miller Effect

Cgd1
V

Vout

Vout
V

Vin
M1

V
2Cgd1

M1
Vin

A capacitor experiencing identical but opposite voltage swings

at both its terminals can be replaced by a capacitor to ground,
whose value is two times the original value.

Where Does Power Go in CMOS?

Dynamic Power Consumption
Charging and Discharging Capacitors

Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

Leakage
Leaking diodes and transistors

Dynamic Power Dissipation

Vdd

Vin

Vout
CL

Energy/transition = CL * Vdd 2
Power = Energy/transition * f = CL * Vdd 2 * f

Not a function of transistor sizes!

Need to reduce CL , Vdd , and f to reduce power.

Static Logic Gates

Complex Logic CMOS functions

One extremely powerful aspect of CMOS is the ability to create single gate
circuits that can implement functions consisting of several basic logic
operations.

This makes digital CMOS design quite different from classical logic design
techniques.

A static logic gate is one that has a well defined output once the inputs are
stabilized and the switching transients have decayed away.

Static CMOS logic gates are relatively easy to design and use.

Complex Logic functions

Complex logic gates provide functions that consist of several primitive

NOT, AND, or OR operations.

This is an example of a canonical AOI (and-or-invert) equation1 which

falls into the category of a complex logic operation.

Complex logic gates are constructed using the CMOS inverter as a basis.

nFET and pFET are placed to act as pass transistors.

The input voltage controls the conduction modes of both transistors.

When input = 0V, the pFET conducts the power supply voltage to the
output. When input is Vdd, the nFET is ON, and transmits the ground (0v)
to the output.

Construction of Complex Logic Gates

In order to construct a complex logic gate, let us replace the single

inverter nFET by an array of nFETs that are connected to operate
as a large switch.
Similarly, we will substitute an array of pFETs for the single pFET
used in the inverter, and view the pFET array as a giant switch.
In order to insure proper electrical operation, however, we must
exercise care so that operation of the nFET array complements the
operation of the pFET array.
This means that if one array is a closed switch, the other must be
open.

Construction of Complex Logic Gates

The general structure of a complex logic gate can be created

by the following steps.

Provide a complementary pair (an nFET and a pFET with a common

gate) for each input;
Replace the single nFET with an array of nFETs that connects the
output to ground;
Replace the single pFET with an array of pFETs that connects the
output to Vdd
Design the nFET and pFET switching network so that only one
network acts as a closed switch for any given input combination.

For multiple inputs, the nFET and pFET

arrays are viewed as large composite
switches, with each array containing m
MOSFETs.
For a given input combination, only one
composite switch can be closed. If the
pFET switching array is closed, then the
output voltage is Vdd.
Conversely, if the nFET array is closed,
then the output is a logic 0

for proper operation, the arrays must be designed so that the

two cases where either (i) both switching arrays are closed, or,
(ii) both switching arrays are open, cannot occur, since both
situations give an undefined output.

CMOS NAND Gate

The NAND2 operation is described by

To construct a CMOS circuit that provides this

function we will use two complementary pairs, one
for each of the inputs A and B, and create the nFET
and pFET arrays according to the needed outputs.

Circuit of CMOS NAND2 Gate

Logical operation

Denoting the inputs by simply A

and B results in the circuit
shown in Figure. The output is
viewed as the OR operation
between the pFET switches
and the nFET switches such
that.

By Demorgans law

Output charge time

The worst-case initial condition

on the output voltage is that
Vout = 0V which implies that
both input voltages are initially
at high.
If either A or B (or both) switch
to logic 0 values, Cout charges
through the appropriate pFET
transistors.
Figure (a) shows the case where
a single pFET MpA is switched
into conduction.

In this case, the MOSFET current charges the output capacitance as seen
using the equivalent RC network shown in Figure (b).
The inverter analysis may thus be applied to estimate

Where
resistance.

is the time constant with as the equivalent pFET

In the opposite case where pFET MpB is switched into conduction

(implying that the nFET MnB is in cutoff), the parasitic capacitance CX
between the nFETs will also charge. This increases the value of since
charge is diverted away from the output node.

The best case (shortest) charge time occurs if both pFETs are
conducting. If both transistor have the same aspect ratio, then
the total charging current is double that passing through a
single transistor.
This is equivalent to having one-half of a single FET
resistance so that the effective pFET resistance is given by

in the time constant.

Output discharge delay time

To calculate the discharge delay time we
assume an initial output voltage VDD of
this implies that at least one of the inputs
is at a logic 0 value.
Discharging occurs when both A and B
increase to logic 1 voltages.
MOSFETs MnA and MnB are both active
and provide a conducting path between
and ground as shown in Figure (a).

The situation can be modeled using

the equivalent circuit in Figure (b).

The time constant in elmore form can be written as

where RnA and RnB are the equivalent MOSFET resistances, and CX
represents the internal node capacitance between the two transistors. This
can be used to estimate the high-to-low time by noting that the use of the
Elmore time constant implies that we are modelling the output voltage as
an exponential of the form

The time required to achieve a particular value of Vout is computed from

Since tHL is defined as the time required for the voltage to fall from the

CMOS NOR Gate

The NOR2 operation is described by

Circuit of CMOS NOR2 Gate

Logical operation

Denoting the inputs by simply A

and B results in the circuit
shown in Figure. The output is
viewed as the OR operation
between the pFET switches
and the nFET switches such
that.

By Demorgans law

Output Discharge Time

The high-to-low time is computed by noting

that Cout discharges through the nFET MnA
or MnB.
Since these are in parallel, the worst-case
discharge time occurs when only a single
nFET is conducting as shown in Figure a.
This situation is equivalent to the discharge
in a simple inverter circuit, so that
where

Output Charge Delay Time

With both A and B at logic 0 levels, pFETs MpA
and MpB provide a conducting path between
the output and the power supply as in Figure
(a).
Constructing the RC model in Figure (b) gives a
time constant for the discharge event as

Comparison of NAND and NOR gate

Both NAND and NOR gates are easy to implement in CMOS

logic.
However, for equal numbers of inputs and device sizes,
NAND gates have better transient response than NOR gates,
making them more popular in high-performance design.
We can understand this with help of delay times:

The series-connected transistors are the limiting factor.

In a NAND gate, the discharge delay time is determined by a chain of
n-channel MOSFETs.
A NOR gate, on the other hand, has a charging time which is due to
charging through a chain of p-channel transistors.

Since, in general, the resistance of a MOSFET has the

functional dependence

And
Applying this to the case of series-connected MOSFETs shows
that the nFET chain always discharges faster than the pFET
chain can charge.
Thus, for equal area designs, NAND gates are preferable to
NOR gates.

Complex Logic Gates

Complex logic functions can be implemented by designing the nFET and

pFET switching arrays such that only one composite switch is closed for a
given set of inputs.
If the nFET switch is closed while the pFET switch is open, then the
output is a logic 0. Conversely, a closed pFET switch and an open nFET
switch results in a logic 1 output.

The arrays must be designed to avoid two situations:

(1) both switches are open at the same time, since this gives an
undetermined value;
(2) both are closed at the same time, since the voltage will not be a
well-defined logic voltage.

we have labelled the nFET switching block by f, the pFET

block by f, and the output is also given as f.
This notation is defined to mean that if the output f is a logical
1, the nFET block is OPEN and the pFET block is CLOSED.
Conversely, if the nFET block is CLOSED while the pFET
block is OPEN, the output is at a value of f=0 , With regards to
the individual blocks themselves, the outcome is TRUE (a
logic 1)

Examples of Complex Logic Gates

Consider the function

Either A.B=1 OR C=1 will connect the output to ground by turning on an
nFET conduction path.
C=0 AND (A=0 OR B=0), then the pFETs provide a conduction path
between the power supply and the output, giving a logic 1 output voltage

Basic Logic Cascades

Exclusive OR and equivalence

(XNOR) Gates

XOR CMOS implementation

XNOR CMOS Implementation

Binary Adder

Full adder Circuit using AOI structure

CMOS Circuit using AOI structuring

SR Latch

Set Operation

Simplified SR Latch Circuit