Microcontrolador msp430g2231

MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER

SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
D
D
D
D
-- Active Mode: 220 A at 1 MHz, 2.2 V

-- Standby Mode: 0.5 A
-- Off Mode (RAM Retention): 0.1 A
Five Power-Saving Modes
Ultrafast Wake-Up From Standby Mode in
Less Than 1 s
16-Bit RISC Architecture, 62.5 ns
Instruction Cycle Time
Basic Clock Module Configurations:
-- Internal Frequencies up to 16 MHz With
One Calibrated Frequency
-- Internal Very Low Power LF Oscillator
-- 32-kHz Crystal
-- External Digital Clock Source
16-Bit Timer_A With Two Capture/Compare
Registers
D Universal Serial Interface (USI) Supporting

D
D
D
D
D
D
D
SPI and I2C (See Table 1)

Brownout Detector
10-Bit 200-ksps A/D Converter With Internal
Reference, Sample-and-Hold, and Autoscan
(See Table 1)
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
On-Chip Emulation Logic With Spy-Bi-Wire
Interface
Family Members Details See Table 1
Available in a 14-Pin Plastic Small-Outline
Thin Package (TSSOP), 14-Pin Plastic Dual
Inline Package (PDIP), and 16-Pin QFN
For Complete Module Descriptions, See the
MSP430x2xx Family Users Guide
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1s.
The MSP430G2x21/31 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and
ten I/O pins. The MSP430G2x31 family members have a 10-bit A/D converter and built-in communication
capability using synchronous protocols (SPI or I2C). For configuration details, see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2010 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRODUCT PREVIEW
D Low Supply Voltage Range 1.8 V to 3.6 V

D Ultralow Power Consumption
Table 1. Available Options -- MSP430G2x21 and MSP430G2x31

BSL
EEM
Flash
(KB)
RAM
(B)
Timer_A
USI
ADC10
Channel
CLOCK
I/O
Package
Type
MSP430G2231IRSA16
MSP430G2231IPW14
MSP430G2231IN14
--
128
1x TA2
LF, DCO, VLO
10
16-QFN
14-TSSOP
14-PDIP
MSP430G2221IRSA16
MSP430G2221IPW14
MSP430G2221IN14
--
128
1x TA2
--
LF, DCO, VLO
10
16-QFN
14-TSSOP
14-PDIP
MSP430G2131IRSA16
MSP430G2131IPW14
MSP430G2131IN14
--
128
1x TA2
LF, DCO, VLO
10
16-QFN
14-TSSOP
14-PDIP
MSP430G2121IRSA16
MSP430G2121IPW14
MSP430G2121IN14
--
128
1x TA2
--
LF, DCO, VLO
10
16-QFN
14-TSSOP
14-PDIP
Device
PRODUCT PREVIEW
For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DALLAS, TEXAS 75265
device pinout, MSP430G2x21
DVCC
P1.0/TA0CLK/ACLK
14
13
P1.1/TA0.0
P1.2/TA0.1
P1.3
P1.4/SMCLK/TCK
P1.5/TA0.0/SCLK/TMS
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/SDI/SDA/TDO/TDI
P1.6/TA0.1/SDO/SCL/TDI/TCLK
XIN/P2.6/TA0.1
12
N14
PW14
11
10
DVSS
DVSS
DVCC
DVCC
NOTE: See port schematics section for detailed I/O information.
12
P1.1/TA0.0
11
XOUT/P2.7
P1.2/TA0.1
10
TEST/SBWTCK
P1.3
RST/NMI/SBWTDIO
P1.4/SMCLK/TCK
P1.5/TA0.0/SCLK/TMS
RSA
PRODUCT PREVIEW
16 15 14 13
P1.0/TA0CLK/ACLK
DALLAS, TEXAS 75265
device pinout, MSP430G2x31
DVCC
P1.0/TA0CLK/ACLK/A0
14
13
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREFP1.4/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/A5/SCLK/TMS
12
N14
PW14
11
10
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
DVSS
DVSS
DVCC
16 15 14 13
P1.0/TA0CLK/ACLK/A0
12
XIN/P2.6/TA0.1
P1.1/TA0.0/A1
11
XOUT/P2.7
P1.2/TA0.1/A2
10
TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF-/VEREF-
RST/NMI/SBWTDIO
8
P1.5/TA0.0/SCLK/A5/TMS
RSA
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
PRODUCT PREVIEW
DVCC
DALLAS, TEXAS 75265
functional block diagram, MSP430G2x21

XIN
XOUT
DVCC
DVSS
P1.x
P2.x
Port P1
Port P2
8 I/O
Interrupt
capability
pull-up/down
resistors
2 I/O
Interrupt
capability
pull-up/down
resistors
ACLK
Clock
System
SMCLK
Flash
RAM
2KB
1KB
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
128B
Emulation
2BP
USI
Brownout
Protection
JTAG
Interface
15-Bit
Timer0_A2
2 CC
Registers
Universal
Serial
Interface
SPI, I2C
P1.x
P2.x
Spy-Bi
Wire
PRODUCT PREVIEW
Watchdog
WDT+
RST/NMI
functional block diagram, MSP430G2x31

XIN
XOUT
DVCC
DVSS
Port P1
Port P2
8 I/O
Interrupt
capability
pull-up/down
resistors
2 I/O
Interrupt
capability
pull-up/down
resistors
ACLK
Clock
System
ADC
SMCLK
Flash
2kB
1kB
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
128B
Emulation
2BP
JTAG
Interface
RAM
10-Bit
8 Ch.
Autoscan
1 ch DMA
USI
Brownout
Protection
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
Spy-Bi
Wire
Universal
Serial
Interface
SPI, I2C
RST/NMI
DALLAS, TEXAS 75265
Terminal Functions, MSP430G2x21 and MSP430G2x31

TERMINAL
NAME
16
RSA
NO.
NO.
DESCRIPTION
I/O
P1.0/
TA0CLK/
ACLK/
A0
I/O
General-purpose digital I/O pin

Timer0_A, clock signal TACLK input
ACLK signal ouput
ADC10 analog input A0 (see Note 1)
P1.1/
TA0.0/
A1
I/O

Timer0_A, capture: CCI0A input, compare: Out0 output
P1.2/
TA0.1/
A2/
I/O

Timer0_A, capture: CCI1A input, compare: Out1 output
I/O

ADC10, conversion clock output (see Note 1)
ADC10 negative reference voltage (see Note 1)
I/O

SMCLK signal output
ADC10 positive reference voltage (see Note 1)
JTAG test clock, input terminal for device programming and test
I/O

Timer0_A, compare: Out0 output
USI: clk input in I2C mode; clk in/output in SPI mode
JTAG test mode select, input terminal for device programming and test
P1.3/
ADC10CLK/
A3/
VREF--/VEREF/
PRODUCT PREVIEW
14
N, PW
P1.4/
SMCLK/
A4/
VREF+/VEREF+/
TCK
P1.5/
TA0.0/
A5/
SCLK/
TMS
P1.6/
TA0.1/
A6/
SDO/
SCL/
TDI/
TCLK
P1.7/
A7/
SDI/
SDA/
TDO/
TDI
I/O
I/O

USI: Data output in SPI mode
USI: I2C clock in I2C mode
JTAG test data input or test clock input during programming and test
USI: Data input in SPI mode
USI: I2C data in I2C mode
JTAG test data output terminal or test data input during programming and test
NOTES: 1. MSP430G2x31 only
DALLAS, TEXAS 75265
Terminal Functions, MSP430G2x21 and MSP430G2x31 (continued)

TERMINAL
14
N, PW
16
RSA
DESCRIPTION
I/O
NO.
NO.
XIN/
P2.6/
TA0.1
13
12
I/O
Input terminal of crystal oscillator

XOUT/
P2.7
12
11
I/O
Output terminal of crystal oscillator (see Note 1)

RST/
NMI/
SBWTDIO
10
Reset
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
11
10
Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
16
15
NA
Supply voltage
DVSS
14
14
13
NA
Ground reference
NC
--
--
NA
Not connected
QFN Pad
--
Pad
NA
QFN package pad connection to VSS recommended.
NOTES: 1. If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
TDO or TDI is selected via JTAG instruction.
DALLAS, TEXAS 75265
PRODUCT PREVIEW
NAME
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that

provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
PRODUCT PREVIEW
Program Counter
Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 2 shows examples of the three types of
instruction formats; Table 3 shows the address
modes.
CG2/R3
General-Purpose Register
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Table 2. Instruction Word Formats

Dual operands, source-destination
e.g., ADD R4,R5
R4 + R5 ------> R5
Single operands, destination only
e.g., CALL
PC ---->(TOS), R8----> PC
Relative jump, un/conditional
e.g., JNE
R8
Jump-on-equal bit = 0
Table 3. Address Mode Descriptions

ADDRESS MODE
S D
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
Absolute
EXAMPLE
F F
MOV &MEM,&TCDAT
OPERATION
R10
----> R11
M(2+R5)----> M(6+R6)
M(EDE) ----> M(TONI)
M(MEM) ----> M(TCDAT)
Indirect
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) ----> M(Tab+R6)
Indirect
autoincrement
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) ----> R11

R10 + 2----> R10
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
SYNTAX
D = destination
DALLAS, TEXAS 75265
#45
----> M(TONI)
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)

--
All clocks are active
D Low-power mode 0 (LPM0)

--
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled

CPU is disabled
--
ACLK and SMCLK remain active. MCLK is disabled
--
DCOs dc-generator is disabled if DCO not used in active mode
PRODUCT PREVIEW
--

--
CPU is disabled
--
MCLK and SMCLK are disabled
--
DCOs dc-generator remains enabled
--
ACLK remains active

--
CPU is disabled
--
--
DCOs dc-generator is disabled
--
ACLK remains active

--
CPU is disabled
--
ACLK is disabled
--
--
DCOs dc-generator is disabled
--
Crystal oscillator is stopped
DALLAS, TEXAS 75265
interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
PRODUCT PREVIEW
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 and 5)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A2
TACCR0 CCIFG (see Note 3)
maskable
0FFF2h
25
Timer_A2
TACCR1 CCIFG.
TAIFG (see Notes 2 and 3)
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
ADC10 (see Note 4)
ADC10IFG (see Note 3 and 4)
maskable
0FFEAh
21
USI
USIIFG, USISTTIFG
(see Notes 2, 3)
maskable
0FFE8h
20
I/O Port P2
(two flags)
P2IFG.6 to P2IFG.7
(see Notes 2 and 3)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 and 3)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
0FFDEh ... 0FFC0h
15 ... 0, lowest
(see Note 6)
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module
4. MSP430G2x31 only.
5. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
6. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
10
DALLAS, TEXAS 75265
special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
7
0h
ACCVIE
NMIIE
rw-0
WDTIE:
OFIE:
NMIIE:
ACCVIE:
Address
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
Oscillator fault enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
01h
interrupt flag register 1 and 2

Address
02h
NMIIFG
RSTIFG
PORIFG
OFIFG
rw-0
WDTIFG:
OFIFG:
RSTIFG:
PORIFG:
NMIIFG:
Address
rw-(0)
rw-1
rw-(1)
0
WDTIFG
rw-(0)
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC
power-up
Power-On Reset interrupt flag. Set on VCC power-up.
Set via RST/NMI-pin
7
03h
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.

Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
DALLAS, TEXAS 75265
11
PRODUCT PREVIEW
Address
memory organization
MSP430G2021
MSP430G2031
MSP430G2121
MSP430G2131
MSP430G2221
MSP430G2231
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
512B
0xFFFF to 0xFFC0
0xFFFF to
0xFE00
1kB
0xFFFF to 0xFFC0
0xFFFF to
0xFC00
2kB
0xFFFF to 0xFFC0
0xFFFF to
0xF800
Information memory
Size
Flash
256 Byte
010FFh -- 01000h
256 Byte
010FFh -- 01000h
256 Byte
010FFh -- 01000h
Size
128B
027Fh -- 0200h
128B
027Fh -- 0200h
128B
027Fh -- 0200h
16-bit
8-bit
8-bit SFR
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
RAM
Peripherals
flash memory
PRODUCT PREVIEW
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming and erasing.
It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data
is required.
12
DALLAS, TEXAS 75265
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x2xx Family Users Guide.
oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator
(DCO). The basic clock module is designed to meet the requirements of both low system cost and low power
consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 s. The basic
clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO CALIBRATION DATA (PROVIDED FROM FACTORY IN FLASH INFO MEMORY
SEGMENT A)
DCO FREQUENCY
CALIBRATION
REGISTER
SIZE
1 MHz
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
DALLAS, TEXAS 75265
PRODUCT PREVIEW
ADDRESS
13
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There is one 8-bit I/O port implementedport P1and two bits of I/O port P2:
D
D
D
D
D
All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt condition is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and the two bits of port P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull-up/pull-down resistor.
PRODUCT PREVIEW
WDT+ watchdog timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be disabled or configured as an interval timer and can
generate interrupts at selected time intervals.
Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A2 Signal Connections -- Device with ADC10
Input
Pin Number
14
PW, N
RSA
2 - P1.0
1 - P1.0
Device
Input Signal
Module
Input Name
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
TACLK
INCLK
Module
Block
Timer
Module
Output Signal
Output
Pin Number
PW, N
RSA
NA
2 - P1.0
1 - P1.0
3 - P1.1
2 - P1.1
TA0
CCI0A
3 - P1.1
2 - P1.1
7 - P1.5
6 - P1.5
ACLK (internal)
CCI0B
7 - P1.5
6 - P1.5
VSS
GND
4 - P1.2
3 - P1.2
VCC
VCC
4 - P1.2
3 - P1.2
TA1
CCI1A
8 - P1.6
7 - P1.6
TA1
CCI1B
VSS
GND
VCC
VCC
CCR0
CCR1
DALLAS, TEXAS 75265
TA0
TA1
8 - P1.6
7 - P1.6
13 - P2.6
12 - P2.6
USI
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
ADC10 (MSP430G2x31 only)
PRODUCT PREVIEW
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
DALLAS, TEXAS 75265
15
peripheral file map

PERIPHERALS WITH WORD ACCESS
ADC10
(MSP430G2x31 only)
ADC control 0
ADC control 1
ADC memory
ADC10CTL0
ADC10CTL0
ADC10MEM
01B0h
01B2h
01B4h
Timer_A
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCR1
TACCR0
TAR
TACCTL1
TACCTL0
TACTL
TAIV
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog Timer+
Watchdog/timer control
WDTCTL
0120h
PRODUCT PREVIEW
PERIPHERALS WITH BYTE ACCESS
16
ADC10
(MSP430G2x31 only)
Analog enable
ADC10AE
04Ah
USI
USI control 0
USI control 1
USI clock control
USI bit counter
USI shift register
USICTL0
USICTL1
USICKCTL
USICNT
USISR
078h
079h
07Ah
07Bh
07Ch
Basic Clock System+
Basic clock system control 3

DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2
Port P2 resistor enable

Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 resistor enable

Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Special Function
SFR interrupt flag 2

SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
DALLAS, TEXAS 75265
absolute maximum ratings

Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
Storage temperature, Tstg (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . --55C to 150C
Storage temperature, Tstg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . --40C to 85C
NOTES: 1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended
operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions

NOM
MAX
UNIT
Supply voltage during program execution, VCC
1.8
3.6
Supply voltage during program/erase flash memory, VCC
2.2
3.6
Supply voltage, VSS
Operating free-air temperature range, TA
I Version
Processor frequency fSYSTEM (Maximum MCLK frequency)
--40
85
VCC = 1.8 V,
Duty Cycle = 50% 10%
dc
4.15
VCC = 2.7 V,
dc
12
VCC 3.3 V,
dc
16
MHz
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.

Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
System Frequency --MHz
16 MHz
Supply voltage range,

during flash memory
programming
12 MHz
Supply voltage range,

during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage --V

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Save Operating Area
DALLAS, TEXAS 75265
17
PRODUCT PREVIEW
MIN
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
IAM, 1MHz
TEST CONDITIONS
Active mode (AM)

current (1MHz)
TA
VCC
fDCO = fMCLK = fSMCLK = 1MHz,

fACLK = 32,768Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
MIN
2.2 V
TYP
MAX
UNIT
220
A
3V
300
370
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
typical characteristics -- active mode supply current (into VCC)

4.0
fDCO = 16 MHz
4.0
Active Mode Current -- mA
Active Mode Current -- mA
PRODUCT PREVIEW
5.0
3.0
fDCO = 12 MHz
2.0
1.0
fDCO = 8 MHz
TA = 25 C
2.0
2.0
2.5
3.0
3.5
TA = 25 C
1.0
VCC = 2.2 V
4.0
0.0
0.0
VCC -- Supply Voltage -- V
Figure 2. Active mode current vs VCC, TA = 25C
18
VCC = 3 V
TA = 85 C
fDCO = 1 MHz
0.0
1.5
TA = 85 C
3.0
4.0
8.0
12.0
16.0
fDCO -- DCO Frequency -- MHz
Figure 3. Active mode current vs DCO frequency
DALLAS, TEXAS 75265
temperature (unless otherwise noted) (continued)
low-power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
TA
VCC
Low-power mode 0
(LPM0) current,
see Note 3
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25C
2.2 V
65
ILPM2
Low-power mode 2
(LPM2) current,
see Note 4
fMCLK = fSMCLK = 0 MHz,

fDCO = 1 MHz,
fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
25C
2.2 V
22
ILPM3,LFXT1
Low-power mode 3
(LPM3) current,
see Note 4
fDCO = fMCLK = fSMCLK = 0 MHz,

fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25C
2.2 V
0.7
1.5
ILPM3,VLO
Low-power mode 3
current, (LPM3)
see Note 4
fDCO = fMCLK = fSMCLK = 0 MHz,

fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
25C
2.2 V
0.5
0.7
fDCO = fMCLK = fSMCLK = 0MHz,

fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
25C
2.2 V
0.1
1.5
ILPM4
Low-power mode 4
(LPM4) current,
current
see Note 5
85C
2.2 V
0.8
1.5
ILPM0, 1MHz
NOTES: 1.
2.
3.
4.
5.
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PRODUCT PREVIEW
PARAMETER
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
DALLAS, TEXAS 75265
19
typical characteristics -- LPM3 current
9.0
8.0
7.0
6.0
5.0
Vcc = 3.6 V
4.0
Vcc = 3 V
3.0
Vcc = 2.2V
2.0
1.0
0.0
--40.0 --20.0 0.0
Vcc = 1.8 V
20.0 40.0 60.0 80.0 100.0 120.0
TA -- Temperature -- C
typical characteristics -- LPM4 current

10.0
ILPM4 -- Low--power mode current -- uA
PRODUCT PREVIEW
ILPM4 -- Low--power mode current -- uA
10.0
9.0
8.0
7.0
6.0
5.0
Vcc = 3.6 V
4.0
Vcc = 3 V
3.0
Vcc = 2.2V
2.0
1.0
0.0
--40.0 --20.0 0.0
Vcc = 1.8 V
20.0 40.0 60.0 80.0 100.0 120.0
TA -- Temperature -- C
20
DALLAS, TEXAS 75265
Schmitt-trigger inputs -- Ports Px
PARAMETER
VIT+
TEST CONDITIONS
VCC
Positive going input threshold

Positive-going
voltage
MAX
UNIT
0.45
0.75
VCC
1.35
2.25
0.25
0.55
VCC
3V
0.75
1.65
3V
0.3
1.0
3V
20
50
3V
VIT--
Negative going input threshold

Negative-going
voltage
Vhys
Input voltage hysteresis (VIT+ -VIT-- )
RPull
Pull-up/pull-down resistor
For pullup: VIN = VSS;

For pulldown: VIN = VCC
CI
Input Capacitance
VIN = VSS or VCC
MIN
TYP
35
5
pF
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
PARAMETER
Ilkg(Px.x)
TEST CONDITIONS
High-impedance leakage current
VCC
see Notes 1 and 2
MIN
TYP
3V
MAX
UNIT
50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is
disabled.
outputs -- Ports Px
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MA
X
UNIT
VOH
High-level output voltage
I(OHmax) = --6 mA (see Notes 2)
3V
VCC --0.3
VOL
Low-level output voltage
I(OLmax) = 6 mA (see Notes 2)
3V
VSS+0.3
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum
voltage drop specified.
output frequency -- Ports Px

PARAMETER
TEST CONDITIONS
VCC
fPx.y
Port output frequency

(with load)
Px.y, CL = 20 pF, RL = 1 kOhm

(see Note 1 and 2)
MIN
TYP
MAX
UNIT
3V
12
MHz
fPort_CLK
Clock output frequency
Px.y, CL = 20 pF
(see Note 2)
3V
16
MHz
NOTES: 1. A resistive divider with 2 times 0.5 k between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
DALLAS, TEXAS 75265
21
PRODUCT PREVIEW
leakage current -- Ports Px
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT

vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
25.0
TA = 25C
TA = 85C
20.0
15.0
10.0
5.0
0.5
1.0
1.5
2.0
I OL -- Typical Low-Level Output Current -- mA
I OL -- Typical Low-Level Output Current -- mA
VCC = 2.2 V
P1.7
0.0
0.0
VCC = 3 V
P1.7
TA = 85C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
1.5
2.0
2.5
3.0
3.5
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
0.0
I OH -- Typical High-Level Output Current -- mA
VCC = 2.2 V
P1.7
--5.0
--10.0
--15.0
TA = 85C
--20.0
TA = 25C
0.5
1.0
1.5
2.0
2.5
VCC = 3 V
P1.7
--10.0
--20.0
--30.0
TA = 85C
--40.0
TA = 25C
--50.0
0.0
0.5
1.0
1.5
Figure 6
Figure 7
NOTE: One output loaded at a time.
2.0
2.5
3.0
VOH -- High-Level Output Voltage -- V
VOH -- High-Level Output Voltage -- V
22
1.0
VOL -- Low-Level Output Voltage -- V
Figure 4
--25.0
0.0
TA = 25C
40.0
I OH -- Typical High-Level Output Current -- mA
PRODUCT PREVIEW
30.0
DALLAS, TEXAS 75265
3.5
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
(see Figure 8)
dVCC/dt 3 V/s
0.7 V(B_IT--)
V(B_IT--)
(see Figure 8 through Figure 10)
dVCC/dt 3 V/s
1.35
Vhys(B_IT--)
(see Figure 8)
dVCC/dt 3 V/s
140
mV
td(BOR)
(see Figure 8)
t(reset)
Pulse length needed at RST/NMI pin

to accepted reset internally
2000
2.2 V/3 V
s
s
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT--)
+ Vhys(B_IT--) is 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default
DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency.
PRODUCT PREVIEW
VCC
Vhys(B_IT--)
V(B_IT--)
VCC(start)
0
t d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
DALLAS, TEXAS 75265
23
typical characteristics -- POR/brownout reset (BOR)
VCC
3V
VCC(drop) -- V
2
VCC = 3 V
Typical Conditions
1.5
t pw
1
VCC(drop)
0.5
0
0.001
1000
1 ns
tpw -- Pulse Width -- s
1 ns
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
PRODUCT PREVIEW
VCC
2
3V
VCC(drop) -- V
VCC = 3 V
1.5
t pw
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
24
DALLAS, TEXAS 75265
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average =
32 f DCO(RSEL,DCO) f DCO(RSEL,DCO+1)
MOD f DCO(RSEL,DCO)+(32MOD) f DCO(RSEL,DCO+1)
DCO frequency
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
Vcc
Supply voltage range
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
3V
fDCO(0,3)
3V
0.12
MHz
fDCO(1,3)
3V
0.15
MHz
fDCO(2,3)
3V
0.21
MHz
fDCO(3,3)
3V
0.30
MHz
fDCO(4,3)
3V
0.41
MHz
fDCO(5,3)
3V
0.58
MHz
fDCO(6,3)
3V
0.80
fDCO(7,3)
3V
fDCO(8,3)
3V
1.60
MHz
fDCO(9,3)
3V
2.30
MHz
fDCO(10,3)
3V
3.40
MHz
fDCO(11,3)
3V
fDCO(12,3)
3V
fDCO(13,3)
3V
fDCO(14,3)
3V
fDCO(15,3)
3V
15.25
MHz
fDCO(15,7)
3V
21.00
MHz
SRSEL
Frequency step between

range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
SDCO
Frequency step between

tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
Measured at SMCLK output
3V
50
RSELx = 15
Duty Cycle
3.0
3.6
0.06
0.14
MHz
0.80
MHz
1.50
4.25
4.30
MHz
7.30
7.80
8.60
MHz
MHz
MHz
13.9
MHz
ratio
DALLAS, TEXAS 75265
25
PRODUCT PREVIEW
PARAMETER
calibrated DCO frequencies -- tolerance
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1 MHz tolerance over temperature

(see Note 1)
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
calibrated at 30C and 3.0V
0C to 85C
3.0 V
--3
0.5
+3
1 MHz tolerance over VCC
30C
1.8 V -- 3.6 V
--3
+3
1 MHz tolerance overall
--40C to
85C
1.8 V -- 3.6 V
--6
+6
MIN
TYP
MAX
NOTES: 1. This is the frequency change from the measured frequency at 30C over temperature.
wake-up from low-power modes (LPM3/4)
tDCO,LPM3/4
tCPU,LPM3/4
CPU wake-up time from LPM3/4

(see Note 2)
TEST CONDITIONS
VCC
3V
1.5
UNIT
s
1/fMCLK +
tClock,LPM3/4
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics -- DCO clock wake-up time from LPM3/4
10.00
DCO Wake Time -- us
PRODUCT PREVIEW
PARAMETER
DCO clock wake-up time from
LPM3/4
(see Note 1)
1.00
0.10
0.10
RSELx = 0...11
RSELx = 12...15
1.00
10.00
DCO Frequency -- MHz
Figure 11. DCO wake-up time from LPM3 vs DCO frequency
26
DALLAS, TEXAS 75265
crystal oscillator, LFXT1, low frequency modes (see Note 4)
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal

frequency, LF mode 0, 1
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
fLFXT1,LF,logic
LFXT1 oscillator logic level

square wave input frequency,
LF mode
XTS = 0, XCAPx = 0,
LFXT1Sx = 3
1.8 V to 3.6 V
Oscillation allowance for

LF crystals
OALF
Integrated effective load

capacitance LF mode
capacitance,
(see Note )
CL,eff
MIN
TYP
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle
LF mode
XTS = 0,
Measured at P2.0/ACLK,
fLFXT1,LF = 32,768Hz
fFault,LF
Oscillator fault frequency,

LF mode (see Note 3)
XTS = 0, XCAPx = 0.
LFXT1Sx = 3 (see Note 2)
2.2 V
30
2.2 V
10
50
pF
70
10000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
internal very low power, low frequency oscillator (VLO)

TA
VCC
MIN
TYP
MAX
fVLO
PARAMETER
VLO frequency
TEST CONDITIONS
-40 -- 85C
3.0 V
12
20
dfVLO/dT
VLO frequency
temperature drift
-40 -- 85C
3.0 V
dfVLO/dVCC
VLO frequency supply

voltage drift
25C
1.8 V -- 3.6 V
DALLAS, TEXAS 75265
UNIT
kHz
0.5
%/C
%/V
27
PRODUCT PREVIEW
PARAMETER
Timer_A
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
Internal: SMCLK, ACLK;

External: TACLK, INCLK;
tTA,cap
Timer_A, capture timing
TA0, TA1
VCC
MIN
TYP
MAX
fSYSTEM
3.0 V
20
VCC
MIN
UNIT
MHz
ns
USI, Universal Serial Interface

PARAMETER
TEST CONDITIONS
fUSI
USI clock frequency
External: SCLK;
Duty Cycle = 50% 10%;
SPI Slave Mode
VOL,I2C
Low-level output voltage on SDA

and SCL
USI module in I2C mode

I(OLmax) = 1.5 mA
TYP
MAX
fSYSTEM
3.0 V
VSS
UNIT
MHz
VSS+0.4
5.0
5.0
TA = 25C
4.0
3.0
TA = 85C
2.0
1.0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
4.0
Figure 12. USI Low-Level Output Voltage vs.

Output Current
TA = 85C
3.0
2.0
1.0
0.0
0.0
28
TA = 25C
VCC = 3 V
I OL -- Low-Level Output Current -- mA
VCC = 2.2 V
I OL -- Low-Level Output Current -- mA
PRODUCT PREVIEW
typical characteristics -- USI low-level output voltage on SDA and SCL
0.2
0.4
0.6
0.8
Figure 13. USI Low-Level Output Voltage vs.

Output Current
DALLAS, TEXAS 75265
1.0
10-bit ADC, power supply and input range conditions -- MSP430G2x31 only
TEST CONDITIONS
TA
VCC
Analog supply voltage

range
VSS = 0 V
VAx
Analog input voltage range

(see Note 2)
All Ax terminals.
Analog inputs selected in
ADC10AE register.
ADC10 supply current

(see Note 3)
fADC10CLK = 5.0 MHz

ADC10ON = 1, REFON = 0
ADC10SHT0 = 1,
ADC10SHT1 = 0, ADC10DIV
=0
25C
fADC10CLK = 5.0 MHz

ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
25C
fADC10CLK = 5.0 MHz

ADC10ON = 0, REF2_5V = 1,
25C
Reference buffer supply

current with ADC10SR=0
(see Note 4)
fADC10CLK = 5.0 MHz

ADC10ON = 0,
REFON = 1, REF2_5V = 0,
REFOUT = 1,
ADC10SR=0
IREFB,1
CI
IADC10
IREF+
IREFB,0
RI
NOTES: 1.
2.
3.
4.
VCC
3V
MIN
TYP
MAX
UNIT
2.2
3.6
VCC
3V
0.6
mA
3V
0 25
0.25
mA
25C
3V
1.1
mA
Reference buffer supply

current with ADC10SR=1
(see Note 4)
fADC10CLK = 5.0 MHz

ADC10ON = 0,
REFON = 1,
REF2_5V = 0,
REFOUT = 1,
ADC10SR=1
25C
3V
0.5
mA
Input capacitance
Only one terminal Ax selected

at a time
25C
3V
Input MUX ON resistance
0V VAx VCC
25C
3V
Reference supply current,

reference buffer disabled
(see Note 4)
27
1000
pF
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR-- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
DALLAS, TEXAS 75265
29
PRODUCT PREVIEW
PARAMETER
10-bit ADC, built-in voltage reference -- MSP430G2x31 only
PARAMETER
VCC,REF+
Positive built
built-in
in reference analog
supply voltage range
VREF+
Positi e b
Positive
built-in
ilt in reference voltage
oltage
ILD,VREF+
Maximum VREF+ load current
TEST CONDITIONS
MIN
IVREF+ 1mA, REF2_5V=0
2.2
IVREF+ 1mA, REF2_5V=1
2.9
IVREF+ IVREF+max, REF2_5V = 0

IVREF+ IVREF+max, REF2_5V = 1
TYP
MAX
UNIT
V
3V
1.41
1.5
1.59
3V
2.35
2.5
2.65
V
V
3V
mA
IVREF+ = 500 A +/-- 100 A

Analog input voltage VAx 0.75 V;
REF2_5V = 0
3V
LSB
IVREF+ = 500 A 100 A

Analog input voltage VAx 1.25 V;
REF2_5V = 1
3V
LSB
VREF+ load regulation response time
IVREF+ =
100A900A,
VAx 0.5 x VREF+
Error of conversion
result 1 LSB
3V
400
ns
CVREF+
Max. capacitance at pin VREF+
IVREF+ 1mA,
3V
100
pF
TCREF+
Temperature coefficient
IVREF+ = const. with

0 mA IVREF+ 1 mA
3V
tREFON
Settling time of internal reference

voltage to 99.9% VREF
IVREF+ = 0.5 mA, REF2_5V=0

REFON = 0 1,
tREFBURST
Settling time of reference buffer to

99.9% VREF
IVREF+ = 0.5 mA,

REF2_5V=1,
REFON = 1,
REFBURST = 1
VREF+ load regulation

reg lation
PRODUCT PREVIEW
VCC
30
ADC10SR = 0
ADC10SR = 0
DALLAS, TEXAS 75265
100 ppm/C
3.6 V
30
3V
10-bit ADC, external reference -- MSP430G2x31 only
VEREF+
TEST CONDITIONS
Positive external reference input

voltage range (see Note 2)
UNIT
V
VEREF-- VEREF+ VCC -- 0.15V

SREF1 = 1, SREF0 = 1 (see Note 3)
1.4
3.0
1.2
1.4
VCC
VEREF
Differential external reference input

voltage range
VEREF = VEREF+ -- VEREF--
VEREF+ > VEREF-- (see Note 5)
Static input current into VEREF--
MAX
VCC
VEREF+ > VEREF--
IVEREF--
TYP
1.4
Negative external reference input

voltage range (see Note 4)
Static input current into VEREF+
MIN
VEREF+ > VEREF-SREF1 = 1, SREF0 = 0
VEREF--
IVEREF+
VCC
0V VEREF+ VCC,
SREF1 = 1, SREF0 = 0
3V
0V VEREF+ VCC -- 0.15V 3V

SREF1 = 1, SREF0 = 1 (see Note 3)
3V
0V VEREF-- VCC
3V
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied
with reduced accuracy requirements.
DALLAS, TEXAS 75265
31
PRODUCT PREVIEW
PARAMETER
10-bit ADC, timing parameters -- MSP430G2x31 only
PARAMETER
For specified
performance of
ADC10 linearity
parameters
fADC10CLK
ADC10 inp
inputt clock frequency
freq enc
fADC10OSC
ADC10 built-in oscillator frequency
tCONVERT
tADC10ON
PRODUCT PREVIEW
TEST CONDITIONS
Con ersion time

Conversion
VCC
MIN
MAX
UNIT
ADC10SR = 0
3V
0.45
6.3
ADC10SR = 1
3V
0.45
1.5
ADC10DIVx=0, ADC10SSELx = 0
fADC10CLK = fADC10OSC
3V
3.7
6.3
MHz
ADC10 built-in oscillator,

ADC10SSELx = 0
fADC10CLK = fADC10OSC
3V
2.06
3.51
MH
MHz
13
ADC10DIV
1/fADC10CLK
fADC10CLK from ACLK, MCLK or

SMCLK: ADC10SSELx 0
Turn on settling time of the ADC
TYP
(see Note 1)
s
100
ns
NOTES: 1. The condition is that the error in a conversion started after tADC10ON is less than 0.5 LSB. The reference and input signal are already
settled.
10-bit ADC, linearity parameters -- MSP430G2x31 only

PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral linearity error
3V
LSB
ED
Differential linearity error
3V
LSB
EO
Offset error
LSB
EG
Gain error
3V
1.1
LSB
ET
Total unadjusted error
3V
LSB
32
Source impedance RS < 100 ,
DALLAS, TEXAS 75265
3V
10-bit ADC, temperature sensor and built-in VMID -- MSP430G2x31 only
ISENSOR
Temperature sensor supply

current (see Note 1)
TCSENSOR
TEST CONDITIONS
VCC
MIN
TYP
REFON = 0, INCHx = 0Ah,

TA = 25_C
3V
60
ADC10ON = 1, INCHx = 0Ah

(see Note 2)
3V
3.55
tSensor(sample)
Sample time required if

channel 10 is selected (see
Note 4)
ADC10ON = 1, INCHx = 0Ah,

Error of conversion result 1 LSB
3V
IVMID
Current into divider at channel

11 (see Note 5)
ADC10ON = 1, INCHx = 0Bh,
3V
VMID
VCC divider at channel 11

VMID is 0.5 x VCC
3V
tVMID(sample)
Sample time required if

channel 11 is selected
(see Note 6)

Error of conversion result 1 LSB
3V
MAX
A
mV/C
30
s
NA
1.5
1220
UNIT
A
V
ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature
sensor input (INCH = 0Ah).
2. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [C] + VSensor(TA = 0C) [mV]
3. Values are not based on calculations using TCSensor or VOffset,sensor but on measurements.
4. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on).
5. No additional current is needed. The VMID is used during sampling.
6. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
DALLAS, TEXAS 75265
33
PRODUCT PREVIEW
PARAMETER
flash memory
PARAMETER
VCC(PGM/
ERASE)
TEST CONDITIONS
VCC
Program and Erase supply voltage
TYP
2.2
fFTG
Flash Timing Generator frequency
IPGM
Supply current from VCC during program
2.2 V/3.6 V
257
1
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
tCPT
Cumulative program time (see Note 1)
2.2 V/3.6 V
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
TJ = 25C
MAX
476
kHz
mA
mA
10
ms
ms
105
tRetention
Data retention duration
tWord
Word or byte program time
30
tBlock, 0
Block program time for 1st byte or word
25
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
tSeg Erase
Segment erase time
cycles
100
years
18
see Note 2
UNIT
3.6
20
104
Program/Erase endurance
PRODUCT PREVIEW
MIN
tFTG
6
10593
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controllers state machine (tFTG = 1/fFTG).
RAM
PARAMETER
V(RAMh)
TEST CONDITIONS
RAM retention supply voltage (see Note 1)
CPU halted
MIN
1.6
TYP
MAX
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
34
DALLAS, TEXAS 75265
JTAG and Spy-Bi-Wire interface
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V / 3 V
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V / 3 V
0.025
15
us
tSBW,En
Spy-Bi-Wire enable time

(TEST high to acceptance of first clock edge, see
Note 1)
2.2 V/ 3 V
us
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V/ 3 V
15
100
2.2 V
MHz
3V
10
MHz
2.2 V/ 3 V
25
90
fTCK
TCK input frequency -- 4-wire

4 wire JTAG (see Note 2)
RInternal
Internal pull-down resistance on TEST
60
us
JTAG fuse (see Note 1)

TEST
CONDITIONS
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse-blow
IFB
Supply current into TEST during fuse blow
tFB
Time to blow fuse
TA = 25C
VCC
MIN
TYP
MAX
2.5
6
UNIT
V
100
mA
ms
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched
to bypass mode.
DALLAS, TEXAS 75265
35
PRODUCT PREVIEW
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWTCK pin high
before applying the first SBWTCK clock edge.
2. fTCK may be restricted to meet the timing requirements of the module selected.
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 -- P1.3, input/output with Schmitt trigger -- MSP430G2x21
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PxSEL.y
PxOUT.y
From Timer
DVSS
DVCC
PRODUCT PREVIEW
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Port P1 (P1.0 to P1.3) pin functions -- MSP430G2x21

PIN NAME (P1.X)
(P1 X)
X
0
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
TA0CLK/
TA0.TACLK
ACLK/
ACLK
P1.0/
P1.1/
TA0.0/
P1.2/
TA0.1/
P1.3/
36
P1.x (I/O)
CONTROL BITS / SIGNALS
P1.x (I/O)
I: 0; O: 1
TA0.0
TA0.CCI0A
P1.x (I/O)
I: 0; O: 1
TA0.1
TA0.CCI1A
I: 0; O: 1
P1.x (I/O)
DALLAS, TEXAS 75265
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PxSEL.y
PxOUT.y
From Module
DVSS
DVCC
0
1
P1.4/SMCLK/TCK
PRODUCT PREVIEW
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
PxIFG.y
Set
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
Port P1 (P1.4) pin functions -- MSP430G2x21

PIN NAME (P1.X)
X
4
FUNCTION
P1SEL.x
JTAG
Mode
I: 0; O: 1
SMCLK/
SMCLK
TCK
TCK
P1.4/
P1.x (I/O)
P1DIR.x
DALLAS, TEXAS 75265
37
Port P1 pin schematic: P1.5, input/output with Schmitt trigger -- MSP430G2x21

PxSEL.y
PxDIR.y
From USI
Direction
0: Input
1: Output
PxREN.y
PxSEL.y or
USIPE5
PxOUT.y
From USI
DVSS
DV CC
0
1
P1.5/TA0.0/SCLK/TMS
PxSEL.y
PRODUCT PREVIEW
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
EN
Set
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG

PIN NAME (P1.X)
X
5
FUNCTION
P1SEL.x
USIP.x
JTAG
Mode
I: 0; O: 1
TA0.0/
TA0.0
SCLK/
SCLK
SIMO0/
SIMO0
TMS
TMS
P1.5/
38
P1.x (I/O)
P1DIR.x
DALLAS, TEXAS 75265

PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PxSEL.y or
USIPE6
PxOUT.y
From Module
DVSS
DV CC
0
1
P1.6/TA0.1/SDO/SCL/TDI
PxSEL.y
PRODUCT PREVIEW
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG

PIN NAME (P1.X)
X
6
FUNCTION
P1SEL.x
USIP.x
JTAG
Mode
I: 0; O: 1
TA0.1/
TA0.1
SDO/
SDO
TDI/TCLK
TDI/TCLK
P1.6/
P1.x (I/O)
P1DIR.x
DALLAS, TEXAS 75265
39

USIPE7
PxDIR.y
From USI
Direction
0: Input
1: Output
PxREN.y
PxSEL.y or
USIPE7
PxOUT.y
From USI
DVSS
DVCC
0
1
PxSEL.y
PRODUCT PREVIEW
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
PxIFG.y
Set
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
From JTAG
To JTAG

7
P1.x (I/O)
I: 0; O: 1
SDI/SDO
SDI/SDO
TDO/TDI
TDO/TDI
P1.7/
40
DALLAS, TEXAS 75265
To ADC10
INCHx
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PxSEL.y
ACLK
DVCC
0
1
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
PRODUCT PREVIEW
PxOUT.y
DVSS
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
DALLAS, TEXAS 75265
41
Port P1 (P1.0 to P1.2) pin functions -- MSP430G2x31

PIN NAME (P1.X)
X
0
FUNCTION
P1SEL.x
ADC10AE.x
(INCH.y = 1)
I: 0; O: 1
TA0CLK/
TA0.TACLK
ACLK/
ACLK
P1.0/
A0
A0/
P1.1/
TA0.0/
A1/
P1.2/
TA0.1/
1 (y = 0)
I: 0; O: 1
TA0.0
TA0.CCI0A
A1
1 (y = 1)
P1.x (I/O)
P1.x (I/O)
I: 0; O: 1
TA0.1
TA0.CCI1A
A2
1 (y = 2)
PRODUCT PREVIEW
A2/
P1.x (I/O)
P1DIR.x
42
DALLAS, TEXAS 75265

SREF2
To ADC10 VREF-
VSS
0
1
To ADC10
INCHx = y
ADC10AE0.y
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxSEL.y
PxOUT.y
ACLK
DVSS
DV CC
PRODUCT PREVIEW
PxREN.y
0
1
P1.3/ADC10CLK/A3/VREF-/VEREF-
Bus
Keeper
EN
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y

PIN NAME (P1.X)
X
3
FUNCTION
P1SEL.x
ADC10AE.x
(INCH.x = 1)
CAPD.y
I: 0; O: 1
ADC10CLK/
ADC10CLK
A3
A3
1 (y = 3)
VREF--/
VREF--
VEREF--
VEREF--
CA3
CA3
1 (y = 3)
P1.3/
P1.x (I/O)
P1DIR.x
DALLAS, TEXAS 75265
43

To ADC10 VREF+
To ADC10
INCHx = y
ADC10AE0.y
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PRODUCT PREVIEW
PxSEL.y
PxOUT.y
ACLK
DVSS
DV CC
0
1
Bus
Keeper
EN
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
From JTAG
To JTAG
44
DALLAS, TEXAS 75265
P1.4/SMCLK/A4/VREF+/VEREF+/TCK

PIN NAME (P1.X)
X
4
FUNCTION
P1SEL.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
SMCLK
A4/
A4
1 (y = 4)
VREF+/
VREF+
VEREF+/
VEREF+
CA4/
CA4
TCK
TCK
PRODUCT PREVIEW
I: 0; O: 1
SMCLK/
P1.4/
P1.x (I/O)
P1DIR.x
DALLAS, TEXAS 75265
45

To ADC10
INCHx
ADC10EA.y
PxDIR.y
PxSEL.y
1
Direction
0: Input
1: Output
PxREN.y
PxSEL.y
PxOUT.y
From Module
DVSS
DVCC
0
1
PRODUCT PREVIEW
Bus
Keeper
EN
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
From JTAG
To JTAG
46
DALLAS, TEXAS 75265
P1.5/TA0.0/A5/TMS
Port P1 (P1.5) pin functions

PIN NAME (P1.X)
X
5
FUNCTION
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
TA0.0
A5/
A5
1 (y = 5)
SCLK/
SCLK
SIMO0/
SIMO0
TMS
TMS
PRODUCT PREVIEW
I: 0; O: 1
TA0.0/
P1.5/
P1.x (I/O)
P1DIR.x
DALLAS, TEXAS 75265
47

To ADC10
INCHx
ADC10EA.y
PxDIR.y
from USI
USIPE6
1
Direction
0: Input
1: Output
PxREN.y
PxSEL.y or
USIPE6
PxOUT.y
From USI
DVSS
DV CC
0
1
PRODUCT PREVIEW
Bus
Keeper
EN
PxSEL.y
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
48
DALLAS, TEXAS 75265
P1.6/TA0.1/SDO/SCL/A6/TDI
Port P1 (P1.6) pin functions

PIN NAME (P1.X)
X
6
FUNCTION
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
TA0.1
A6/
A6
1 (y = 6)
SDO/
SDO
TDI/TCLK
TDI/TCLK
PRODUCT PREVIEW
I: 0; O: 1
TA0.1/
P1.6/
P1.x (I/O)
P1DIR.x
DALLAS, TEXAS 75265
49

To ADC10
INCHx
ADC10EA.y
PxDIR.y
from USI
PxREN.y
USIPE7
1
Direction
0: Input
1: Output
PxSEL.y
PxSEL.y or
USIPE7
PxOUT.y
From USI
DVSS
DVCC
0
1
PRODUCT PREVIEW
Bus
Keeper
EN
PxSEL.y
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
From JTAG
To JTAG
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
50
DALLAS, TEXAS 75265
P1.7/SDI/SDA/A7/TDO/TDI

PIN NAME (P1.X)
X
7
FUNCTION
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
A7
1 (y = 7)
SDI/SDO
SDI/SDO
TDO/TDI
TDO/TDI
PRODUCT PREVIEW
I: 0; O: 1
A7/
P1.7/
P1.x (I/O)
P1DIR.x
DALLAS, TEXAS 75265
51
Port P2 pin schematic: P2.6, input/output with Schmitt trigger -- MSP430G2x21 and MSP430G2x31
XOUT/P2.7
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
PxSEL.6
PxDIR.y
Direction
0: Input
1: Output
PRODUCT PREVIEW
PxREN.y
PxSEL.6
PxOUT.y
from Module
DV SS
DV CC
Bus
Keeper
EN
XIN/P2.6/TA0.1
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
Port P2 (P2.6) pin functions -- MSP430G2x21 and MSP430G2x31

PIN NAME (P2.X)
(P2 X)
XIN
X
6
FUNCTION
XIN
P2.6
P2.x (I/O)
TA0.1
Timer0_A3.TA1
52
DALLAS, TEXAS 75265

P2DIR.x
P2SEL.6
PSEL2.7
I: 0; O: 1
Port P2 pin schematic: P2.7, input/output with Schmitt trigger -- MSP430G2x21 and MSP430G2x31
XIN/P2.6/TA0.1
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
PxDIR.y
1
0
from P2.6/XIN
Direction
0: Input
1: Output
PRODUCT PREVIEW
PxSEL.7
PxREN.y
PxSEL.7
PxOUT.y
from Module
DVSS
DV CC
Bus
Keeper
EN
XOUT/P2.7
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
DALLAS, TEXAS 75265
53
Port P2 (P2.7) pin functions -- MSP430G2x21 and MSP430G2x31

PIN NAME (P2.X)
XOUT
FUNCTION
XOUT
P2.x (I/O)
PRODUCT PREVIEW
P2.7
54
DALLAS, TEXAS 75265
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL.7
I: 0; O: 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-May-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package

Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
MSP430G2121IN14
ACTIVE
PDIP
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2121IPW14
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2121IPW14R
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2121IRSA16R
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Purchase Samples
MSP430G2121IRSA16T
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2131IN14
ACTIVE
PDIP
14
25
Pb-Free (RoHS)
Purchase Samples
MSP430G2131IPW14
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2131IPW14R
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2131IRSA16R
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2131IRSA16T
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2221IN14
ACTIVE
PDIP
14
25
Pb-Free (RoHS)
Contact TI Distributor
or Sales Office
MSP430G2221IPW14
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2221IPW14R
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2221IRSA16R
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2221IRSA16T
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2231IN14
ACTIVE
PDIP
14
25
Pb-Free (RoHS)
Request Free Samples
MSP430G2231IPW14
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2231IPW14R
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
26-May-2010
Status
(1)
Package Type Package

Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
MSP430G2231IRSA16R
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
Request Free Samples
MSP430G2231IRSA16T
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
Purchase Samples
(1)
The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
7
0 8
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.

This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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Copyright 2010, Texas Instruments Incorporated

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MSP430G2x21, MSP430G2x31

MIXED SIGNAL MICROCONTROLLER

-- Active Mode: 220 A at 1 MHz, 2.2 V

D Universal Serial Interface (USI) Supporting

SPI and I2C (See Table 1)

Copyright 2010 Texas Instruments Incorporated

PRODUCT PREVIEW information concerns products in the formative or

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

D Low Supply Voltage Range 1.8 V to 3.6 V

Table 1. Available Options -- MSP430G2x21 and MSP430G2x31

LF, DCO, VLO

LF, DCO, VLO

LF, DCO, VLO

LF, DCO, VLO

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

device pinout, MSP430G2x21

NOTE: See port schematics section for detailed I/O information.

NOTE: See port schematics section for detailed I/O information.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

device pinout, MSP430G2x31

NOTE: See port schematics section for detailed I/O information.

NOTE: See port schematics section for detailed I/O information.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

functional block diagram, MSP430G2x21

functional block diagram, MSP430G2x31

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Terminal Functions, MSP430G2x21 and MSP430G2x31

General-purpose digital I/O pin

General-purpose digital I/O pin

General-purpose digital I/O pin

General-purpose digital I/O pin

General-purpose digital I/O pin

General-purpose digital I/O pin

General-purpose digital I/O pin

NOTES: 1. MSP430G2x31 only

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Terminal Functions, MSP430G2x21 and MSP430G2x31 (continued)

Input terminal of crystal oscillator

Output terminal of crystal oscillator (see Note 1)

QFN package pad connection to VSS recommended.

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DALLAS, TEXAS 75265

The CPU is integrated with 16 registers that

Four of the registers, R0 to R3, are dedicated as

Table 2. Instruction Word Formats

e.g., ADD R4,R5

Single operands, destination only

Relative jump, un/conditional

Table 3. Address Mode Descriptions

Symbolic (PC relative)

M(R10) ----> M(Tab+R6)

M(R10) ----> R11

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D Active mode (AM)

All clocks are active

D Low-power mode 0 (LPM0)