Von Neumann Architecture

The term von Neumann architecture refers to a particular design

model for a stored-program digital computer.
Separate central processing unit (CPU) and random-access
memory (RAM).
Both instructions and data stored in RAM.
Data to be processed is transferred from RAM to CPU, and
results are transferred back to RAM.
Named for Hungarian-American mathematician
John von Neumann.
Most modern computers follow this basic design model, but are
substantially more complex.

John Von Neumann and IAS

The IAS machine was built during the period 1946-1951 at the
Institute for Advanced Study in Princeton, NJ, under von Neumanns direction.

Source: http://faculty.indwes.edu/bcupp/lookback/ias.jpg

IAS: Vital Statistics

40-bit word, 12-bit addresses (word addressible)
20-bit instructions, stored two per word
two program-accessible registers: accumulator and
multiplier/quotient
implemented memory was 1024 words (5KBytes)
(cathode ray tube storage)
circuitry used about 2300 vacuum tubes

IAS Organization

Source: http://www.ece.unm.edu/xup/images/ias.jpg

Von Neumanns Heritage

Most modern computers inherit their basic design model from
von Neumanns machine.
CPU: performs the actual processing
Control Unit: performs instruction decoding and control.
Arithmetic Logic Unit (ALU): performs basic arithmetic
and logical operations.
Registers: small amount of memory used to hold addresses, instructions, and data
RAM: larger memory used to store both program and data

Stored-Program Computer
In a stored-program computer, the program to be executed is
stored in RAM along with data to be processed.
Program consists of binary instructions stored in RAM.
A program counter (or instruction pointer) register in the
CPU stores the memory address of the next instruction.
Alternative (less flexible) is hard-wired program using switches,
patch cables, etc.

Fetch/Decode/Execute Cycle
The basic cycle of operation of a von Neumann-style computer:
Fetch: The next instruction is retrieved from RAM.
(program counter is immediately incremented)
Decode: The instruction is examined to determine what the
CPU should do:
Opcode: field that determines the type of instruction.
Operand(s): fields that determine the source and
destination of data to be operated on.
Execute: The operation specified by the instruction is
performed.
May involve one or more memory references.

Instruction Set
The instruction set of a computer is the repertoire of instructions
that the CPU can perform.
Determined by the computer architects/designers.
Hard-wired as part of the computer design.
Different for each type of computer.

Typical Instructions
The instruction set of a typical von Neumann computer will contain instructions like the following:
Load data from memory to CPU register.
Store data from CPU register to memory.
Add, subtract, multiply, divide, etc. data in CPU registers.
And, or, xor, not, etc. data in CPU registers.
Shift and rotate data in CPU registers.
Jump based on CPU state flags (condition codes).
Call a subroutine and return to caller.

Example
A high-level language statement: X = A + B would be translated
to machine instructions as follows:
Load A
Add B
Store X

Accumulator Machines
Early von Neumann-style machines were accumulator machines:
CPU contained one register: the accumulator.
Accumulator used in nearly every instruction.
RAM is also accessed in nearly every instruction.
Problem: CPU and RAM are made using different technologies,
and CPU is much faster than RAM.
Was true in von Neumanns day, and is even more of an issue
today.
Example: A 3GHz CPU has a cycle time of 0.333 nanoseconds, but the access time of typical DRAM is over 100 times
slower.

The von Neumann Bottleneck

In a von Neumann architecture, all data to be processed has to
be retrieved from RAM, processed in the CPU, and written back
to RAM.
Term von Neumann bottleneck coined by John Backus in
1977 to refer to the fact that computing speeds are limited
by CPU-to-RAM bandwidth.
Modern computers partially address the problem by putting small
amounts of faster memory in or close to the CPU. This memory
takes the form of caches and register files.

Caches
A cache is a high-speed memory placed in between the CPU and
the RAM.
The cache retains recently accessed data and also data from
nearby locations.
Relies on locality of reference: if data from one address has
just been accessed, chances are that nearby addresses will be
accessed soon.
Cache memory uses different technology than normal memory (SRAM vs. DRAM) and is several times faster.
Modern computers use multiple levels of caches, with different speeds and capacities.
Example: Intel Core 2 Duo has 32KB of L1 cache with 3-cycle
latency and 4MB of L2 cache with 14-cycle latency.

Register Files
The single accumulator of von Neumanns machine has been
supplanted by register files:
1. Consist of small, high-speed incorporated into the CPU itself.
2. Most instructions can operate on data already stored in registers.
3. Reduces the fraction of instructions that have to access
RAM.
4. Permits CPU instruction cycle time to be several times faster
than the RAM cycle time.
A typical computer might contain 32 registers, each of which
can store one word.

Caches vs. Registers: The Programmers

Perspective
Both caches and register files are used in modern computers.
Caches are transparent: they are an automatic hardware feature that the programmer normally doesnt have to be concerned with.
Registers affect the computers instruction set, and are therefore of constant concern to the programmer.

Faster

Larger

Increasing Complexity
For a long time, computer designers built machines with ever
larger and more complex instruction sets.
Many different kinds of instructions, with complex functions.
Many different addressing modes (ways to access memory).
Each instruction could make multiple memory references.
A complex instruction set required complex hardware to
implement it.

The RISC Idea

RISC stands for Reduced Instruction Set Computer.
It was realized that computers could be made faster if they
had smaller and simpler instruction sets.
The gain comes partly through the use of pipelining: the
CPU executes instructions like a factory production line.
At any instant, several instructions are in various stages of
execution, with one instruction completing in each cycle.
A simpler instruction set makes the pipelined design easier
to accomplish.
RISC computers also use larger register files.
Old-style architectures became known as CISC: (Complex
Instruction Set Computers.)

RISC vs. CISC

Intels x86 architecture is an example of CISC.
Need for backward binary compatibility has kept Intel locked
into this architecture.
Since Pentium Pro (P6), Intel has incorporated RISC features
into its processor designs, but kept same instruction set.
Complex control logic decodes x86 CISC instructions into
simpler RISC-like instructions on-the-fly.
Intel has managed to get some RISC-like speed improvements
while keeping the old CISC instruction set.