ACA 2nd Mid Semester 2010

Q1. Why RISC architecture is considered as better performance machine? [1]

What are important features of ULTRA SPARC IV plus? Describe them. [3]

Ans. The following features of the RISC architecture speeds-up the operations and hence
improve the performance,
a) Relatively few instruction types and addressing modes
b) Fixed and easily decoded instruction formats
c) Hardwired rather than Micro-programmed Control Unit
d) Memory access limited to load and store instructions
e) Use of compilers to optimize object code performance

Features of ULTRA SPARC IV plus are,

Diagram UltraSPARC IV plus
a) The UltraSPARC IV plus implements chip-multithreading (CMT) multiple multiplethread cores. More specifically, it implements two cores with two threads per core.
b) Internally, it implements two modified UltraSPARC III cores, and its physical packaging
is identical to the UltraSPARC III.
c) UltraSPARC IV plus also incorporates a 3-level cache hierarchy. Both cores share a L2
cache with a capacity of up to 16 MB but have their own L2 cache tags.
d) It implements 4-way superscalar architecture and a 14-stage non-stalling pipeline.
e) The UltraSPARC III cores are improved by optimizing the instruction fetch, store
bandwidth, and data prefetching.
f) The floating-point adder implements additional hardware to handle more not a number
(NaN) and underflow cases to avoid exceptions.
g) A better branch prediction mechanism, augmented prefetching capabilities and new
computational abilities.

Q2. What is the basis of VLIW? [1]

Why this machine is incompatible with other machines? [1]
How is it made compatible? [1]
What are the problems in compaction? [1]

Ans. VLIW combines the concept of Horizontal Microcoding in which multiple operations are
packed within a single instruction using opcodes; and Superscalar Processing in which multiple
independent instructions are simultaneously executed. So VLIW provides simultaneous
execution of instructions by the use of multiple Functional Units and Common Large Register
File shared by all FUs. For example, if there are 5 FUs, then a single VLIW instruction will have
opcodes for all the FUs, which will be simultaneously initiated to process their respective
instructions.

VLIW machines are incompatible with other machines because of the following reasons,
a) Its instruction format contains the opcodes corresponding to the number of FUs, which
can be different for different machines. Example.
b) Instructions issued to the different FUs at the same time may produce different latencies
on similar architectures. Example.

It is made compatible by the use of Code Compaction. In Code Compaction, the short
independent instructions are packed into a VLIW word from a Trace. A Trace is a sequence of
control assuming certain outcomes. This helps in branch prediction. There can be multiple traces
depending upon the branching in the code. Independent instructions from a trace can be packed
into a VLIW word. So by converting short instructions into VLIW words by the compiler, this
architecture can be made compatible. Example.

The problem with Code Compaction occurs when the branch predictions are not accurate.
Because in code compaction the instructions can be moved up or down depending upon the trace
selected. And if the trace selected is not the most likely one then the other off-trace paths get
separated from the rest of the program and cannot be used without being again linked to the rest
of the program. Example.