Keith R.

Abell
keithabell@aol.com

Home: 512-260-9940 Cell: 512-587-8323

Professional Profile
- Know where you are and where you want to go; motivation and perseverance will get you there. Recent positions as Embedded FW and HW Engineer -- responsibilities included:
o Senior Firmware Engineer [SolarBridge Technologies, Inc.]
FW development in C [PSOC3, PSOC5l, STM32F050/51]
Development of smart mini-inverters [MIs] that transform solar panel DC to grid AC
Assigned in early 2014 to the Advanced Development Group working on advanced MI topologies
o Principal Engineer [Lumenergi, Inc.]
FW development in C [PIC24F32KA302] and machine assembly code [PIC16F886, 883, 785]
Development of smart energy efficient dimmable ballasts and lighting control products
o Senior Engineer [NovusEdge, Inc.]
FW development in Microchip [PIC16F776, 777] and extended 8051 [80C400] in machine assembly code.
HW design and development of Microchip PIC based control units used in building security applications.
Unit, QA, and MFG test tool development in machine language, C, and MS Visual Suite.
Patent activity: 1 Pending (SolarBridge Technologies in area of PWM control of MI), 1 Pending (Lumenergi sensor
control of smart ballasts), 1 Awarded US 7,337,333 (DELL distributed power supply)
Broad background in embedded development in roles as developer, team lead, architect, and tech support engineer.
Broad experience in microprocessor/SOC architectures (RISC/CISC) and memory (cache, flash, SRAM, EEPROM).
Recent experience (10+ years) with embedded C-based and assembly FW for 8, 16, and 32 bit micros tools and IDEs.
Familiar with PC/server and mass storage enclosure management and relevant industry standards (IPMI).
Experience utilizing test equipment: emulators, simulators, oscilloscopes, power supplies, signal generators, DVMs.
Experience developing designs with HW teams (reviewing schematics, suggesting optimal signal assignments).
Worked with Agile development process and working familiarity with the Rally [Agile] online Web based tracking tool.
Proven ability in developing ideas and articulating technical information to peer engineers, customers, and management
through Executive VP level.

Technical Skills - Advanced

PSOC3, PSOC5lp, STM32F050/51,
XMC4400, PIC24F32K302, DAVE
IDE, uVision 4 and 5, PICF16F886/883,
PIC16F876A and 877A architecture,
MPLAB C30 C, Microchip assembler,
PIC ICE-2000 emulator, REAL-ICE,
MELAB's PIC programmer, ANSI C,
PowerGREP, BeyondCompare,

Embedded FW, Embedded POST,

Embedded Drivers, In-circuit Emulation
(ICE), DALI Lighting Control, I2C ,
Enclosure Management, Systems
Management, Remote Systems
Management, CISC and RISC concepts,
Analog/digital Oscilloscopes, I2C Bus
Analyzers, DVM, Serial-to-I2C Tools,

Interrupt driven I/O (ADC and sensors,

GPIO, RS232, RS485), FW Defect
Analysis, Root Cause Analysis, Top
Down Design, Schematic Evaluation,
Logic Design Concepts, Customer
Engineering Support (HW & FW),
PADS Layout and Schematic Review
Tools

Technical Skills - Intermediate/Familiar

Dallas 80C400 [Extended 8051]
architecture, META-ICE 80C400
Emulator, SMBus, ARM 32bit RISC,
Motorola 68020/30/40, A390 8051
extended set assembler, ARM7TDMI
Core, Intelligent Platform Management
Interface (IPMI) 1.0/1.5/2.0, MIPS

R3000/4000, Multi-threaded, Multitasking, RTOS, ThreadX, CodeWright,

Editor Green Hills Development
Environment, SES, SAF-TE, SAT-TE
over SATA/SEP, SW Simulation of
HW, Logic Analyzers (w/ and w/o bus
analysis), SCSI Bus Analyzers,

SourceSafe, PCCS, MS-DOS, Win95,

Win9, WinNT, Win2K, WinXP, MSWord, Excel, PowerPoint, Access,
Project, CVS, Subversion, Agile
Development Process, Rally Agile
tracking tool (Web), Custom PC build
and Repair

Management and Project Leader Skills

Project Management, Resource Management,
Budgeting, Capital Planning, Expense Planning,
Team Building, Process Development, Technical

Reviews and Appraisals, One-on-Ones,

Executive Presentations (Selling an Idea, Status)
Training

Education
B.S.E.E., Computer and Digital Circuit Design, Clarkson University (Graduated with Distinction, 3.53 GPA)

Keith R. Abell (V4.1 09/22/12)

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Keith R. Abell
Experience
- Set the expectation then meet or beat it every time SolarBridge Technologies, Inc., Austin, TX (Now part of SunPower, Inc.)
Feb 2013 Nov 2014
Senior Firmware Engineer, FW Development Smart Energy Efficient Solar DC-to-AC Mini-inverters

As part of Advanced Product Development team, met aggressive development schedules on two new mini-inverted designs
geared towards higher efficiency in converting DC to AC.
As part of firmware development team, participated in major port of current Gen 2.2 FW base from an 8051 based PSOC3 design
to an ARM based PSOC5lp design.
Additional duty as part of firmware development team was to handle issues reported on any of our MI products either out of the
development team or reported from the field.

Results:
1) First Advanced project was a new topology to increase efficiency in the input DC front-end processing. This required considerable
additions to the ADC sensor side involving the addition of multiple voltage and current sensors to control an ST-Micro
STM32F050 C-source based firmware. Also extensions to the Input-to-Output processor communication to allow polling for
control info. Completed project starting in early Mar on time for live demo at end of May with working Power Management
support with PLC communication based commands to request operational data from the MI.
2) Second advanced project was a significant variant in current SolarBridge MI designs in a topology unifying the input and output
functions. Completed vendor search to identify correct microprocessor (XMC4400) to implement the control function. Developed
platform firmware supporting all ADC sensor datum and support for multiple synchronized PWM complexes involved for control.
Base firmware was completed on time in three months (Aug) to start bring-up on prototype HW. Since Aug spent time tuning and
working issues with HW team.
3) As part of development team work as primary project for PSOC5lp port required making many distributed changes to
almost all of the source files to modify big endian based code to work in an ARM little endian environment. Code base
became target firmware still under development for SBTs next flag ship product.
4) Worked with HW team to implement a special low-voltage version of our MI in support of an external foundation
investigating solar DC-to-AC conversion. Required modifying voltage limit values to run at low power.
5) Worked a number of maintenance issues and special firmware for custom products. Worked critical HW shutdown issue
due to some voltage management issues. Worked with HW to identify and FW based fix to sequence shutdown in a way
that would not cause MI HW damage.
Lumenergi Inc., Cottonwood Shores, TX
Mar 2008 Jan 2013
Principal Embedded FW Engineer, FW Development Smart Energy Efficient Lighting Products

Current lighting control project based around PIC24F32K302 processor using MPLAB C30 compiler and MPLAB IDE tools
with REAL-ICE debugger. Will employ PID techniques to synchronize and control output based on requested setting.
Sole FW developer on iB107 follow-on product to iB100, Lumenergis line of smart dimmable fluorescent lamp ballasts.
Expanded feature set to handle over 30 different configurations of 4 major types of bulbs brought to market in 2011.
Took full FW development control of initial iB100 ballast product brought to market in Dec 2010.

Results:
1) Devised scheme on iB100 to auto-configure for 1, 2, or 3 32W T8 fluorescent lamps or 2ea 17W T8 lamps. Resolved
issues related to detection of bulb removal, auto re-start with bulb replacement.
2) Resolved major HW/FW issue related to insufficient resolution in the PWM function controlling lamp levels insufficient
granularity of PWM frequencies required to run at (60 KHz-100 KHz) for sufficiently smooth dimming. Developed
scheme that broke up the arc-control with a 300Hz control that allowed variable timing between two different
frequency/duty cycle pairs to divide up each operating point into 48 different discrete steps. Solution was effective enough
to allow product to enter production.
3) Work on an enhanced iB107 resulted in two patents pending in the area of auto-configuration and heater management.
The iB107 increased the solution set to 4 major fluorescent bulb types and over 30 configurations (type and bulb counts)
with only 2ea part numbers (SKUs) based on a FW switch. Developed concept of single heater feedback for type
characterization and total heater feedback to assist in determining bulb count. Also developed a sensitive heater change
algorithm to detect the loss of single heater with a 200 mv signal change to resolve bulb replacement issues.
4) Current project due to ship by end of year is based on the advanced 16-bit 24F series processor in C. Developed
techniques to drive triac control of sampled load current waveform for synchronizing and managing the delivered power in
accordance with the requested level.
Keith R. Abell (V4.1 09/22/12)

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NovusEdge Inc, Austin, TX

Senior Embedded SW/HW Engineer, FW & HW Development Building Security Products

Aug 2005 - Jan 2008

Sole developer in the embedded FW and HW development role; responsible for all design, development, testing, maintenance, of
the Microchip mid-range PIC based door access, input, and output connectors that made up product offerings.
Responsible for the communication section of a Dallas 80C400 [extended architecture 8051] based controller that communicated
with the connectors over a multi-drop RS485 serial bus. This FW was a set of interrupt and polled driver routines running under
TiniOS and written in 8051 machine level code and driven from upper level applications.
Responsible for developing new features and maintaining existing features in the both Microchip PIC and 80C400 assembler
source bases to include proper software versioning, control, and archiving (CVS and Subversion).
Responsible for the design and development of all connector and controller HW (UL and RoHS compliant) to include
establishing functional requirements, selecting appropriate microcontrollers and glue/sensor logic, and the mechanical design in
support of the feature set. Coordinated with vendors related to schematic capture, layout, routing, and PCB/PWB procurement.
Responsible for all prototype FW and HW bring-up and all unit/product testing. Provided inputs and changes to correct any
deficiencies and coordinated any required changes to the final design (BOM or PCB).
Responsible for designing and maintaining all MFG test fixtures and test suites and developed new test strategies and test HW to
reduce test cost while increasing test coverage.
Performed duties using the Agile development process through Rally, a web-based tracking tool.

Results:
1) Originally hired on 90-day contract to resolve major communication problems as it related to a proprietary protocol over a
multi-drop RS485 communication bus (multi-master and multi-slave). Made sufficient progress in two months to be
awarded a regular position.
Resolved all issues pertaining to the 485 communication problems within 86 days and given a special award.
Transport layer issues related to short stop and start bits, poor collision avoidance, and timing violations.
Protocol issues to include a rejection of resent commands.
Misunderstandings of the PIC 16F876A architecture to include interrupt timing and failure to protect critical sections.

2) Inherited two faulty connector designs, one for input (w/ 4 spins) and another for output (w/ 5 spins) that suffered from a
number of HW logic errors:
Within two weeks, identified and resolved all of the HW issues. Entered production with a single spin of the PCBs for both assemblies.

3) Over the course of a year, resolved on the order of thirty FW issues of varying complexity and importance related to the
connectors and the controller representing the entire backlog of must fix FW issues.
4) Championed and sold organization on FW based Super-loader concept.
Designed and developed smart secondary loader for the PIC based connectors that accepted encoded Intel hex records for error detection.
Built C-based object tool that generated unique CRC code for each downloadable object and integrated solution into the build tools.
Super-loader remains in download mode if application code CRC check fails, preventing field replacement of connectors failing download.

5) Developed an industry standard ESD test table (with shielding and grounding) and developed a formal test plan and
procedure to investigate a series of field failures that could have been static related. The ensuing testing verified that our
controller design was good to at least 16KV (air) and 8KV (shorting) which was deemed sufficient.
6) Played major role in defining the requirements for a new access door connector incorporating new features. Sold the
organization on using a sister PIC chip to the version used in previous offerings allowing backwards and forwards FW
compatibility with older HW while providing a platform to deliver new features in a cost effective way.
Served as project lead for all aspects of the design, development, vendor relations, and productization of the device.
Championed use of self-protecting FETs for the outputs eliminating separate and costly parts for shorts and over-current situations in the field.
Resolved inherited power supply problem that did not current limit to a level that would have prevented damage to the switching power supply
filter inductor. The fixes led to a PS design that could survive a long term dead short across the output.
Utilized cost effective connectors to eliminate an expensive hand soldered wire harness; this allowed design and use of a clam shell and pogopin test fixture saving minutes per unit of MFG test time over old design.
Utilized surface mount LED and light-pipe technology to provide status in a tight form factor and in a cost effective way.
Resolved all engineering issues related to mechanical, electrical, and functional design. Worked BOM and parts issues with appropriate
parties. Advised management on cost/benefit tradeoffs.
Developed all FW to implement the new features.
Developed test SW tools in C and Visual Basic for unit testing and production MFG for the new connector design to include error messages
with fault tree identification of parts to check to repair failed boards.
Moved project from inception to production with delivery of debugged test fixture into contract MFG facility.

QLogic Corp., Austin, TX

Senior Principal Engineer, FW & HW Technical Support - Management Products Group

2001 - 2005

Hired to create a world class technical support function to assist OEM HW design and FW engineers on all aspects of integrating
Zircon (ARM7TDMI) & GEM (6502) enclosure management controllers and FW solutions into their designs around a custom

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series of SOCs with an RTOS implementation of a fully IPMI compliant management solution (Dell was an early adopter of our
product). Provided engineer-to-engineer design and development assistance to include c-code samples.
Given additional responsibility as team lead and supervisor of FW sustaining and turn-key custom FW for selected tier 1
customers after major group reorganization in 2004.
Promoted to Senior Principal Engineer and Site Manager in 2004 to service critical tier 1 customer as QLogic moved to close
down the MPG group in early 2005.

Results:
1) Developed effective and streamlined support methodologies due to growth in customer base and expansion of chip
offerings (from 2 to 6 chips in the Zircon line) and the addition of the GEM line (4 chips) to the support function in 2002.
Investigated Zircon HW/FW issues reported from field using Green Hills Development environment, ICE debuggers, and lab tools to find
problems in C-based systems management FW in ARM ThreadX RTOS environment. Required understanding of RS232, LAN,
I2C/SMBUS, and memory drivers and all operational aspects of the IPMI command sets and their implementations.
Reviewed designs and recommended architectures for OEM ESM solutions for server and mass storage management controllers and provided
guidance on how to modify/configure the standard FW to accommodate the system design and sensor sets.
Providing training on all facets of the solution set:
All aspects of the Intel IPMI implementation and standard command set (API/ABI).
Modifying, building, and debugging FW to accommodate specific customer requirements
Hardware architecture, schematic requirements, and utilization of ARM based (ARM7TDMI core) microcontrollers
Created and built custom configurations of FW for Taiwan and US customers and delivered pre-built FW code binaries for their testing.
Provided input to Senior Management (GM and VP level) on customer trends, feature requirements, and common problems.
Added and mentored second engineer to support function in late 2003 and provided day-to-day coordination of all support activities by team.
Achieved a Customer Satisfaction rating for the Management Product Group in the fall of 2004 at over 90% (highest of all QLogic divisions)
while handling a significant increase in the number of issues and total email volume; this rating was deemed high enough by the company to
guarantee retention of customers and the only division so recognized.
Volume grew from ~400 issues/~3100 emails in 01/02 to ~570 issues/~4500 emails in 03/04. Added GEM storage management customer
support in the fall of 2002 to the Zircon server management support already responsible for.

2) As team lead and supervisor of FW sustaining and custom engineering function, provided technical oversight and day to
management in support of building customized versions of our standard FW to support full featured implementations
based on customer requirements. Efforts involved detailed schematic and design reviews, coordination and assisting
development, debug of implemented customer features, and final delivery to key tier 1 customers including Mitac,
HP/Compaq, Wistron, and Celestica.
3) As Site Manager, maintained successful working environment to retain 8 of 10 key engineering personnel after major
reorganization and RIF leading to the dissolution of the MPG group. Kept six critical turn-key FW development projects
on track over 8 months for a large tier 1 customer and materially contributed to rebuilding a positive relationship to
maintain a multi-million dollar revenue stream.
Dell Corporation, Austin, TX
Architect, Embedded Systems Management FW - Enterprise Systems Group

1999 - 2001

Became first Dell architect in the field of ESM FW. Established subsystem requirements and influenced management decisions
at Director and VP level.
Responsible for new technology and systems engineering in the areas of ESM firmware, error reporting, and remote
platform/system management.
Assigned as Dell representative to the IPMI and DIG64 Specification Committees.

Results:
1) Created new IPMI compliant Enclosure Management System Architecture and a turn-key blue print HW design around an
RTOS embedded management solution across all server lines of business of the Enterprise Systems Group (Dell).
Achieved across LOB buy-in of front panel error reporting mechanism and remote system management network connectivity via LAN and
serial interfaces (EMP).
Created architecture presentations and concept design documents and achieved approval from two director level development departments,
server and system management product marketing and the Executive VP of ESG.
Investigated vendors and made recommendation on vendor to supply ESM controller and base ESM firmware. Achieved acceptance and buyin from LOB teams of System Managers and their Directors.

2) Worked major quality issue with a set of C-based system utilities for managing embedded system management firmware to
include testing and downloads.
Discovered improper logic flow on both sides of the host-to-ESM processor I/F (later adopted as part of IPMI I/F Block Transfer HIF port).
Found race condition in testing port register bits that allowed the management controller FW and the PC based host utilities to get out of
synchronization. Net result of my proposed fixes was a highly reliable FW download and BMC-to-host communications.

3) As member of Intel DIG64 technical committee, played key role towards adoption of a systems management strategy:
Management section in final draft of the initial DIG64 specification reflects my draft to the committee.
Able to head off a proposal to remove the management section altogether.
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4) Patent issued (US 7,337,333) in area of smart power supply design involving multiple redundant power supplies that
monitor power required to supply a variable set of blade servers that maintained reliability while shutting down unneeded
supplies to save power. Title: A System and Method for Strategic Power Supply Sequencing in a Computer System
Dell Corporation, Austin, TX
Manager, BIOS and Embedded Systems Management FW - Enterprise Systems Group

1995 - 1999

Hired as Senior Manager III, responsible for a new team developing BIOS FW for Dells entry into the Server Market.
Moved over in 1998 to reorganize ESM (Enclosure System Management) FW team.

Results:
1) Assessed feature set of Dell developed BIOS for use in first complete line of PC servers; discovered issues with desktop
BIOS not suitable for PC Servers (e.g., lacking support for multiple processors and large memory arrays).
Worked vendor comparison and effort assessment; sold senior management (Director and VP) on acquiring new base with proper feature set to
match system requirements and save six months of development effort.
Delivered BIOS FW for five different server systems over two years on or ahead of schedule. First two systems went from inception to
production in an extremely aggressive 7 to 8 month cycle and both shipped on time.
Built team from 8 to 12 engineers over first twelve months.

2) Assigned additional duty as member of Process Development team involving key members of the Dell Server
management team:
Provided inputs as it relates to BIOS and FW development in a phased process that was created, from the requirements stage through final QA
testing and piloting.
Assisted in preparation of training materials and presentations to all of the engineering community.
Our results were of a quality that our process was adopted with only minor modifications across all of the development organizations
(Desktops and Laptops) and paved the way to Dell ISO-9000 certification.

3) Asked to take over management of embedded systems management FW team (4 engineers). Early assessment turned up
morale, resource, quality, and build/source-control issues:
FW team had been dispersed into the HW teams negatively impacting productivity and the ability to drive common solutions.
Instituted proper source control and tagging procedures for all unit test (X), product test (P), and production releases (A) so FW team could
rebuild any release and deliver defect fixes on any specific release required by system managers.
Hired project manager to assist coordination and deliverables through the development cycle. Grew team to six FW developers over 6 months.
Hired another FW engineer to create a regression test that would be required to run before any release outside the FW team. Materially
contributed to reducing poor quality and eliminated dead-on-arrival FW due to lack of regression testing on minor changes.
Assigned additional duty on Manufacturing Tiger team to assist resolution in some ongoing MFG issues with FW. Resolved a number of
issues to include poor test methodology, FW download issues, and reduction of test times to allow faster system assembly. Reduced MFG line
fall out by 80-90%.

Tandem Computers, Austin, TX

Manager, Firmware and Platform Development Sections, Product Development Group

1991 - 1995

Promoted to FW development supervisor in 1991. Managed FW, POST, boot-ROM, and service processor development teams.
Managed 15 engineers in fault-tolerant HAL and driver code for Unix OS.

Results:
1) Promoted twice in two years at Tandem from FW developer to FW team manager to FW and Service Processor
development manager.

Oversaw delivery of processor FW for new R4000 based system and a fault tolerant service processor built around the pSOS RTOS.

2) Hand picked by Senior Management to lead Platform team (15 senior engineers) to develop a fault tolerant HAL layer for
a new UNIX System V release on a new Tandem architecture.
Tandem Computers, Austin, TX
Senior Firmware Developer, Platform BIOS and DVT, Product Development Group

1990 - 1991

Responsible for developing fault-tolerant POST/BIOS code and advanced chip design firmware verification tests in Verilog HDL
simulation environment.

Results:
1) Ramped up in 1 month to take over final development of MIPS based POST and boot ROM FW for MIPS 3000 based
fault tolerant computer in machine language environment. During release process, investigated critical flash programming
issue jeopardizing delivery schedule:
Flash programming would fail depending on combination of DC Converter and main board.
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 HW engineering suspected design problem; was able to determine flash programming was sensitive to voltage and found improper FW loop
was not properly retrying each location. If programming voltage was only a few tenths low, a location would not program on first try and
download would fail. Completed recovery efforts to ship HW on time.

2) Assigned to DVT team, wrote test FW in MIPS machine language to test all aspects of a fault tolerant memory subsystem. Involved creating test cases to test valid and invalid memory cycles against Verilog HDL models of a MIPS 3000
processor and the system board logic in a simulation environment.
Texas Instruments, Austin, TX
1983 - 1990
Senior Firmware/POST Developer and Manager, POST and Diagnostic Section, Computer Systems Division

Promoted to working diagnostics supervisor within two years (1983).

Promoted to Manager of TI990 diagnostic and firmware development groups in 1984.
Started new development group as lead engineer on new Motorola 68020 based UNIX architecture in 1986 and became
supervisor/manager within first year.

Results:
1) Promoted to TI Diagnostic manager, met and exceeded financial and capital planning metrics while managing team of 12
diagnostic and FW development engineers.

Met critical development schedules on recurring basis and awarded non-periodic raise for efforts.
Rewrote inherited diagnostic build process to solve severe schedule and quality issues.
Pared two build files of 1300 lines to 130 lines (via simple loop) reducing build times from 1 wk to 24 hrs.
Established reputation as having best builds for QA and production releases.

2) Chosen as one of two pioneer developers assigned to new Advanced Systems project:
Assisted the creation of a portable diagnostic subsystem to resolve issues with two different HW architectures in an extremely short (3 month)
development window.
Created a reusable test harness in a FOURTH like diagnostic language that included all standard infrastructure allowing diagnostic team to
meet critical schedule commits.

3) Tapped as senior lead engineer for FW and Diagnostics on new open standards TI UNIX system based around the
Motorola 680X0 32bit CISC architecture and written in Motorola assembly code:

Created memory map and flash partition for boot functions, diagnostic and post functions, full ROM based debug monitor, built-in Motorola
disassembler, and special MFG test loops.
Created full 4-way associative cache test (Harvard architecture) in half the time of a previous design by using top-down design techniques.
With design complete, coding took 7 days and debug took only 3 days.
Created ROM code build and splitter tool in C to assist flash image creation.
Grew the team to a half-dozen FW engineers and became team lead and supervisor in less than 6 months.

Texas Instruments, Austin, TX

Firmware/POST Developer, POST and Diagnostic Section, Computer Systems Division

1981 - 1983

Developed ROM based POST and boot firmware for 990 systems.

Results:
1) Designed, coded, and tested boot and POST FW for TI990 99000 based minicomputer on time and on budget:
Required management of 8 1K byte pages of flash memory; met schedule by paging 3 pages and downloaded rest into tested RAM.
Wrote full diagnostics of processor, register set, memory buses, and cache memory and peripheral devices.
Wrote drivers for front panel and cassette tape unit for diagnostic loading.

Keith R. Abell (V4.1 09/22/12)

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