A

Seminar Report
On
FLIP FLOP CIRCUITS, MEALY AND
MOORE MODEL
In partial fulfillment of requirements for the degree of
Bachelor of Engineering
In
Electronics & Communication Engineering

Submitted By

SURAJ. P. B

Department of Electronics Engg:

Govt. Engineering College, Thrissur

Page

INDEX
1. Introduction - Page 3
2. SR Latch -

Page 4

3. D Flip-Flop Page 8
4. JK Flip Flop Page 9
5. T Flip flop Page 10
6. Mealy and Moore Model with examples Page 11

Page

Introduction

The circuits stored information about the previous history of

inputs are called storage or memory elements. A primitive storage
element can be constructed from a small number of gates
connecting the outputs back as inputs. These circuits are binary
cells capable of storing one bit of information. They have two
outputs, one for the normal value and one for the complement value
of bit stored in it. Primitive memory elements actually fall into two
board classes : latches and flip-flop.
If a latch has only data inputs, it is called an unlocked latch (or
only latch). Level-sensitive latches have an additional enable input,
sometimes called the clock. Level-sensitive latches continuously
sample their inputs when they are enabled. Any change in the level
of the input is propagated through to the output. When the enable
signal is unasserted, the last value of the inputs is determines the
state held by the latch.
Flip-flops differ from latches in that their output change only with
repeat to the clock, whereas latches change output when their
inputs change. Flip-flops are characterized on the basis of the clock
transition that cause the output change : there are positive edgetriggered, negative edge-triggered, and master/slave flip-flops.
A positive edge-triggered flip-flop samples its inputs on the lowto-high clock transition. A negative edge-triggered flip-flop works in
a similar fashion, with the input sampled on the high-to-low clock
transition.
A master-slave flip-flop is constructed from two stage separate
flip-flops. The first stage ( first flip-flop) samples the inputs on the
rising edge of a clock signal. The second stage transfer them to the
output on the falling edge of the clock signal.
These circuits have two additional control inputs. These are
Preset and Clear, which force the output of the flip-flop or latch to
the logic-1 or logic-0 state, respectively, independent of the flip-flop
or latch inputs.

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S-R Latch:

A S-R ( Set-Reset) latch is the simplest possible memory element.

It is constructed by feeding the outputs of two NOR gates back to
the other NOR gates input.
The inputs R and S are referred to as the Reset and Set inputs,
respectively.
To understand the operation of the S-R latch consider the
following scenarios :
S=1 and R=0: The output of the bottom NOR gate is equal to
Q 0
zero,
.
Hence both inputs to the top NOR gate are equal to zero, thus,
Q 1
.
Hence, the input combination S=1 and R=0 leads to the latch
Q 1
being set to
.
S=0 and R=1: Similar to the arguments above, the outputs
Q 1
Q0
become
and
.
We say that the latch is reset.
Q 0
Q 1
S=0 and R=0: Assume the latch is set (
and
),
Q 1
then the output of the top NOR gate remains at
and the
Q 0
bottom NOR gate stays at
.
Q 1
Q0
Similary, when the latch is in a reset state (
and
), it
will remain there with this input combination.
Therefore, with inputs S=0 and R=0, the latch remains in its
state.
S=1 and R=1: This input combination must be avoided
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The logic diagram and

graphic symbol are shown in
Figure.4.1.
The following truth table can be summarized the operation of
the S-R latch.
R

Q '

S
(a) Logic Diagram
Symbol

Q'

(b)Graphic

Q'

Q'

0
1
1

1
0
1

0
1
-

1
0
-

Comme
nt
Hold
State
Reset
Set
Forbidde
n

(c) Truth table

Figure.4.1 S-R latch with NOR gates.

A S-R latch can also be constructed from NAND gates.

The graphic symbol, logic diagram, and truth table of
the latch are shown in Figure.4.2.
S

Q '

(a) Logic Diagram

Symbol

Page

Q'

Q'

0
1

1
0

1
0

0
1

Q'

(b)Graphic
Comme
nt
Hold
State
Set
Reset

Forbidde
n

(c) Truth table

Figure.4.2 S-R latch with NAND gates.

Level Sensitive (Clock) S-R Latch:

The operation of the S-R latch can be modified by providing an
additional control input that determines when the state of the circuit is
to be changed. The logic diagram, graphic symbol, and thruth table of
level sensitive S-R latch are shown in Figure.4.3 [1].

Q '

Q'

(a) Logic Diagram

(b)Graphic

Symbol
S

Q'

Q'

0
1
1

1
0
1

1
1
1

0
1
-

1
0
-

Q'

Comme
nt
Hold
State
Reset
Set
Forbidde
n
Hold
State

(c) Truth table

Figure.4.3 Level Sensitive S-R latch with NAND gates.

Level Sensitive (Clock) D (Delay) Latch :

One way to eliminate the undesirable condition of the
indeterminate state in the S-R latch is to ensure that inputs S and R are
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never equal to 1 at the state time. This is done level sensitive D latch
shown in Figure.4.4. The latch has only two inputs: D and C. The D
input connect directly to the S input and its complement is applied to
the R input. The D input is sampled when C is equal to 1. If D is
equal to 1, the Q output goes to 1. If D is equal to 0, the Q output goes
to 0. If C is equal to 0, the Q output remains in its previous state [1].

D
Q

Q '

Q'

(a) Logic Diagram

(b)Graphic

Symbol

C
1
1
0

D
0
1
x

Q
0
1
Q

Q'
1
0
Q'

(c) Truth table

Figure.4.4 Level Sensitive D latch with NAND gates.
Level Sensitive (Clock) J-K Latch:
A level sensitive J-K latch shown in Figure.4.5 is a refinement of
the S-R latch in that the indeterminate state of the S-R type is defined
in the J-K type. Inputs J and K behave like inputs S and R to set and
clear the latch, respectively. The input marked J is for set and the
input marked K is for reset. When the both inputs J and K are equal to
1, the latch switches to its complement state, that is , if Q=1, it
switches to Q=0, and vice versa. If the C is equal to 0, The output of
the latch remains in its previous state [1].

C
Page

Q '

Q'

(a) Logic Diagram

(b)Graphic

Symbol
C

Q'

1
1
1
1
0

0
0
1
1
x

0
1
0
1
x

Q
0
1
Q'
Q

Q'
1
0'
Q
Q'

Commen
t
Hold
Reset
Set
Toggle
Hold

(c) Truth table

Figure.4.5 Level Sensitive J-K latch.

D Flip-Flop:
Positive-Edge Triggered:

CLK

Q'

Q'

Q'

(a) Truth table

(b) Graphic Symbol

Figure.4.6. Positive edge-triggered D flip-flop.

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Negative-Edge Triggered:
Q

CLK

Q'

Q'

Q'

(a) Truth table

CLK

Q'

(b) Graphic Symbol

Figure.4.7. Positive edge-triggered D flip-flop.

J-K Flip-Flop:
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Positive-Edge Triggered:
CLK

0
1

Q'

Q'

Q'

x
x

x
x

Q
Q

Q'
Q'

(a) Truth table

(b) Graphic Symbol

Figure.4.8. Positive edge-triggered J-K flip-flop.

Negative-Edge Triggered:
CLK

Q'

Q'

Q
CLK

0
1

Q'

x
x

x
x

Q
Q

Q'
Q'

(a) Truth table

Q'

(b) Graphic Symbol

Figure.4.9. Negative edge-triggered J-K flip-flop.

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T Flip-Flop:

CLK

The T flip-flop is a single-input version of the J-K flip-flop. As

shown in Figure.4.10, the T flip-flop is obtained from the J-k flip-flop
when both inputs are tied together. The designation T comes from the
ability of the flip-flop to toggle, or complement, its state. While input
T is 1, The flip-flop complements its output when the clock pulse
T
occurs.
While T is 0, The output of the flip-flop remains in its previous
state [1].

CLK

0
1

Q'

Q'

Q'

x
x

Q
Q

J
CLK

Q'
Q'

(a) Truth table

(b) Graphic Symbol

Figure.4.10. Negative Edge-Triggered T flip-flop.

Moore & Mealy Machines

Sequential Design Review:
Page

Q'

- A binary number can represent 2 states, where n is the number of bits.

- The number of bits required is determined by the number of
2
states. Ex. 4 states requires 2 bits (2 = 4 possible states)
5
Ex. 19 states requires 5 bits (2 = 32 possible states)
- One flip-flop is required per state bit.
Steps to Design Sequential Circuits:
1) Draw a State Diagram
2) Make a Next State Truth Table (NSTT)
3) Pick Flip-Flop type
4) Add Flip-Flop inputs to NSTT using Flip-Flop excitation
equation (This creates an Excitation Table.)
5) Solve equations for Flip-Flop inputs (K-maps)
6) Solve equations for Flip-Flop outputs (K-maps)
7) Implement the circuit

Moore State Machines:

- Outputs determined solely by the current state
- Outputs are unconditional (not directly dependent on input signals)
INPUT

INPUT

INPUT
STATE

STATE

OUTPUT

OUTPUT

INPUT

GENERIC MOORE STATE MACHINE

Note: This should look at lot like the counter designs done previously.

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Example: Design a simple sequence detector for the sequence 011. Include three outputs
that indicate how many bits have been received in the correct sequence. (For example,
each output could be connected to an LED.)
1) Draw a State Diagram (Moore) and then assign binary State Identifiers.
1
X=1

X=0
X=0
A

B
000

001
X=0

X=1

X=0

X=1

111

011
X=1

MOORE SEQUENCE DETECTOR FOR 011

Note: State A is the starting state for this diagram.
2) Make a Next State Truth Table (NSTT)

Q1
0
0
0
0
1
1
1

Page

State
A
A
B
B
D
D
C
C

X
0
1
0
1
0
1
0
1

O2
0
0
0
0
1
1
0
0

O1
0
0
0
0
1
1
1
1

O0
0
0
1
1
1
1
1
1

State+
B
A
B
C
B
A
B
D

Q0
0
0
1
1
0
0
1

X
0
1
0
1
0
1
0

O2
0
0
0
0
1
1
0

O1
0
0
0
0
1
1
1

O0
0
0
1
1
1
1
1

Q1 +
0
0
0
1
0
0
0

Q0 +
1
0
1
1
1
0
1

STATES

Page

A=00
B=01
C=11
D=10

3) Pick Flip-Flop type

- Pick D Flip-Flop
4) Add Flip-Flop inputs to NSTT to make an excitation table
Q1
0
0
0
0
1
1
1
1

Q0
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1

O2
0
0
0
0
1
1
0
0

O1
0
0
0
0
1
1
1
1

Q1+
0
0
0
1
0
0
0
1

O0
0
0
1
1
1
1
1
1

Q0+
1
0
1
1
1
0
1
0

D1
0
0
0
1
0
0
0
1

D0
1
0
1
1
1
0
1
0

5) Solve equations for Flip-Flop inputs (K-maps)

X\Q1Q0
0
1

00
0
0

01
0
1

11
0
1

X\Q1Q0
0
1

10
0
0

00
1
0

01
1
1

11
1
0

10
1
0

D0 = X +Q1Q0

D1 = XQ0

6) Solve equations for Flip-Flop outputs (K-maps)

Q1\Q0
0
1

0
0
1

O 2 = Q1

Q0

1
0
0

Q1\Q0
0
1

0
0
1

O1 = Q1

1
0
1

Q1\Q0
0
1

O0 = Q1 +Q0

Note: Moore designs do not depend on the inputs, so X can be neglected.

8) Implement the circuit

0
0
1

1
1
1

Example: Design a sequence detector that searches for a series of binary inputs to satisfy
the pattern 01[0*]1, where [0*] is any number of consecutive zeroes. The output (Z)
should become true every time the sequence is found.
1) Draw a State Diagram (Moore) and then assign binary State Identifiers.

Recall: Picking state identifiers so that only one bit changes from state to state will
generally help reduce the amount of hardware required for implementation. Only
the transition from Success to First requires two bits to change.
2) Make a Next State Truth Table (NSTT)
State
Start
Start
First
First
Success
Success
Second
Second
Unused
SuccessD
SuccessD
Delay
Delay

Q2
0
0
0
0
0
0
0
0
1
1
1
1
1

Q1
0
0
0
0
1
1
1
1
0
1
1
1
1

Q0

X
0
0
1
1
0
0
1
1
*
0
0
1
1

0
1
0
1
0
1
0
1
*
0
1
0
1

Z
0
0
0
0
1
1
0
0
X
1
1
0
0

State+
First
Start
First
Second
First
Start
Delay
Success
X
Delay
Success
Delay
SuccessD

Q2 +
0
0
0
0
0
0
1
0
X
1
0
1
1

Q1 +
0
0
0
1
0
0
1
1
X
1
1
1
1

Q0 +
1
0
1
1
1
0
1
0
X
1
0
1
0

3-7) Do the remainder of the design steps.

Mealy State Machines:

- Outputs determined by the current state and the current inputs. -Outputs
are conditional (directly dependent on input signals)
INPUT/OUTPUT

INPUT/OUTPUT

STATE

INPUT/OUTPUT

STATE

INPUT/OUTPUT

GENERIC MEALY STATE MACHINE

Example: Design a sequence detector that searches for a series of binary inputs to satisfy
the pattern 01[0*]1, where [0*] is any number of consecutive zeroes. The output (Z)
should become true every time the sequence is found.
1) Draw a State Diagram (Mealy) and then assign binary State Identifiers.

Moore vs. Mealy Timing Comparison

Clock (CLK):
Input (X):
Moore Output (Z):
Mealy Output (Z):
Current State (Qi):
+
Next State (Qi ):

Initialize
_
0
_

1
1
0
0

2
0
0
0

3
0
0
0

4
1
0
0

5
0
0
0

6
0
0
0

7
1
0
1

8
0
1
0

9
1
0
1

A
1
1
1

B
1
1
0

C
0
0
0

Start
_

Start
Start

Start
First

First
First

First
Second

Second
Delay

Delay
Delay

Delay
SuccD

SuccD
Delay

Delay
SuccD

SuccD
Succ

Succ
Start

Start
First

Note: The Moore Machine lags one clock cycle behind the final input in the
sequence. The Mealy Machine can change asynchronously with the input.
One of the states in the previous Mealy
State Diagram is unnecessary:

Note: The Mealy Machine requires one less state than the Moore Machine! This is
possible because Mealy Machines make use of more information (i.e. inputs) than
Moore Machines when computing the output. Having less states makes for an easier
design because our truth tables, K-maps, and logic equations are generally less
complex. In some cases, the reduction of states is significant because it reduces the
number of flip-flops required for design implementation. In spite of the advantages of
using a design with less states,
We will still use the 6-state
Mealy Machine for the remainder of these notes to facilitate a direct
comparison with the 6-state Moore Machine.
2) Make a Next State Truth Table (NSTT)

State

Q2

Q1

Q0

Start
0
Start
0
First
0
First
0
Success
0
Success
0
Second
0
Second
0
unused
1
SuccessD
1
SuccessD
1
Delay
1
Delay
1
State+
Z
0
First
0
Start
0
First
0
Second
0
First
0
Start
0
Delay
1
Success
X
X
0
Delay
1
Success
0
Delay
1
SuccessD

0
0
0
0
1
1
1
1
0
1
1
1
1
Q2+
0
0
0
0
0
0
1
0
X
1
0
1
1

0
0
1
1
0
0
1
1
*
0
0
1
1
Q1+
0
0
0
1
0
0
1
1
X
1
1
1
1

0
1
0
1
0
1
0
1
*
0
1
0
1
Q0 +
1
0
1
1
1
0
1
0
X
1
0
1
0

Note: This is identical to the Moore Machine, except for output Z.

3) Pick Flip-Flop
type Select D
Flip-Flops..

4) Add Flip-Flop inputs to NSTT using Flip-Flop excitation equation

State
Start
Start
First
First
Success

Q2
0
0
0
0
0

Q1 Q0 X
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0

Z
0
0
0
0
0

State+
First
Start
First
Second
First

Q2 +
0
0
0
0
0

Q1+
0
0
0
1
0

Q0+
1
0
1
1
1

D2
0
0
0
0
0

D1
0
0
0
1
0

D0
1
0
1
1
1

Success
Second
Second
unused
SuccessD
SuccessD
Delay
Delay

0
0
0
1
1
1
1
1

1
1
1
0
1
1
1
1

0
1
1
*
0
0
1
1

1
0
1
*
0
1
0
1

0
Start
0
Delay
1 Success
X
X
0
Delay
1 Success
0
Delay
1 SuccessD

0
1
0
X
1
0
1
1

0
1
1
X
1
1
1
1

0
1
0
X
1
0
1
0

0
1
0
X
1
0
1
1

0
1
1
X
1
1
1
1

0
1
0
X
1
0
1
0

5) Solve equations for Flip-Flop inputs (K-maps)

Q2Q1\Q0X 00 01
00
0 0
01
0 0
11
1 0
10
X
X

D2 = Q2Q0 +Q2

11 10
0 0
0 1
1 1
X X

Q2Q1\Q0X 00 01 11 10
00
0
0
1
0
01
0
0
1
1
11
1
1
1
1
10
X
X
X
X

Q2Q1\Q0X 00 01
00
1 0
01
1 0
11
1 0
10
X X

X +Q1Q0 X D1 = Q2 +Q1Q0 +Q0 X

D0 = Q0 X +Q0 X +Q1Q0

Note: This is identical to the Moore Machine.

6) Solve equations for Flip-Flop outputs (K-maps)

Moore
Mealy
Q2Q1\Q0
00
01
11
10

0
0
1
1
X

1
0
0
0
X

Q2Q1\Q0X 00
00
0
01
0
11
0
10
X

=Q

01
0
0
1
X

11
0
1
1
X

10
0
0
0
X

= Q X +Q Q X

Mealy
2
1
0
Q0
Recall: Moore outputs do not depend on the input.
- ZMoore can only change when the state changes (synchronous).
- ZMealy can change asynchronously because it can change with X.
Moore

Note: The Moore and Mealy Machines solve the same problem.
7) Implement the circuit
D2
X, Q2, Q1, Q0

Q2

Combo
Logic

D-FF

D1
X, Q2, Q1, Q0

Combo

11 10
1
1
0
1
0
1
X X

Q1

Z
Combo

Logic

D-FF

D0
X, Q2, Q1, Q0

Q Q0

Combo
Logic

Logic

D-FF
Q

Clk

Notes: The 3 boxes of combinational logic on the left are the same for both of the Moore
and Mealy designs because the state transitions are the same. This would not have been
the case had we implemented the 5-state Mealy Machine.
The larger box of combinational logic on the right is different for the Moore and Mealy
designs because the output, Z, is computed differently