Dynamic Random Access Memories (Drams) : Gagandeep Singh Iit Guwahati

Dynamic random access
memories (DRAMs)
Gagandeep Singh
IIT Guwahati
2
Dynamic Random Access
Memory
OUTLINE
Introduction
RAM: SRAM & DRAM
SRAM & DRAM Structure
Read Operation
Write Operation
Refresh
Error Correction
Different versions of DRAM
Trends
Conclusions
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MEMORY
Data/Instruction storage
unit of a system
Essentially stores all
data in form of bits (0/1)
Several technologies:
magnetic tape
hard disks
optical disks
semiconductor
memories
Computer memory hierarchy

Source: wikipedia.org
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CLASSIFICATION
Semiconductor
Memory
Random Access
Memory
(RAM)
SRAM
DRAM
Read Only
Memory
(ROM)
NVRAM
PROM,
EPROM,
EEPROM
Resistive
Memories
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RANDOM ACCESS MEMORY (RAM)

Data can be read/write
Data can be accessed in random order
All memory locations can be accessed at almost the
same speed
Mostly volatile e.g. DRAM, SRAM but NVRAM nonvolatile
Temporary storage and working memory
Can be classified into SRAM and DRAM
Contrast with
ROM
Sequential memory devices
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STATIC RANDOM ACCESS MEMORY (SRAM)

Uses bistable latch formed by cross-connecting
two invertors to store bit value
Very fast but expensive
Requires more space, less power
Does not require periodic refresh
Used where high speed data access is required
e.g. in CPU cache memory
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SRAM STRUCTURE
Bit is stored on
bistable latch formed
by four transistors
Two additional access
transistors serve to
control the access to a
storage cell during
read and write
operations
Each cell connected to
2 bit lines and one
word line
6T SRAM structure
source Wikipedia.org
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DYNAMIC RANDOM ACCESS MEMORY (DRAM)

Stores bit value as capacitor charge
Needs to be refreshed periodically
Higher density & small cell area compared to
SRAM
Low production cost
Used in CPU main memory
Slower as compared to DRAM
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DRAM CELL STRUCTURE

Capacitor connected by
pass transistor
Bit stored as charge value
on capacitor
Voltage on word line
ascertains transistor is
open or close
Word line and bit line
connected to multiple cells
Word line
Bit line
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DRAM ARRAY
Has two bit lines per
column
Each bit connected to
each other cell
Word lines connecting
whole row
Memory cell at
intersections
Sense amplifiers, latch
and selection circuitry
Pre-charge and refresh
circuitry
4x4 DRAM array
Source: wikipedia.org
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Memory
READ OPERATION
Bit-lines pre-charged
Capacitance maintains the precharged voltage
Desired row's word-line driven
Transfer of charge from the
storage cell to the connected bitline
Vsig = Vdiff.Cs
Cs + CB
where Vdiff = Vcell - Vdd/2
Cs and Cb are capacitances of
storage cell and bit line
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Memory
READ OPERATION (Contd)

Voltage difference on bit
lines too small
Sense amplifiers amplify
voltage difference between
the odd and even row bitlines
Sense amplifier outputs
latched
Column selected
Simultaneous recharging the
storage cells
Word-line, sense amplifier
switched off, bit lines precharged again
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SENSE AMPLIFIER
Initially VN is at Vdd/2 and VP at signal
ground
The P and N sense amplifiers are fired
sequentially
Nsense amp is fired by bringing VN
toward ground
NMOS with gate connected to higher
voltage conducts
This brings low bit line to ground
Similar operation of Psense amp
The memory cell transistor remains ON
and hence charge on cell capacitor is
restored
Sense Amplifier Schematic
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EARLY READ SEQUENCING

Assert Row Address
Assert RAS_L
Commence read cycle
Meet Row Address setup time before asserting RAS_L
Assert OE_L
Assert Col Address
Assert CAS_L
Meet Col Address setup time before CAS/hold time
after CAS
Valid Data Out after access time

De-assert OE_L, CAS_L, RAS_L to end cycle
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LATE READ SEQUENCING

Assert Row Address
Assert RAS_L
Commence read cycle
Meet Row Address setup time before asserting RAS_L
Assert CAS_L
Meet Col Address setup time before CAS/hold time
after CAS
Assert OE_L
Valid Data Out after access time
De-assert OE_L, CAS_L, RAS_L to end cycle
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READ CYCLES DIAGRAM
Source: EECS 150 David Culler, EECS UCB
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WRITE OPERATION
Data to be written i.e. 0 or 1 is
provided at the bit line
Done by opening row and is
temporarily forcing a given column's
sense amplifier to the desired high
or low voltage state Word line is
asserted to turn on the pass
transistor
Capacitor charges or discharges
depending on bit line state
Word line de-asserted
Due to the sense amplifier's positive
feedback configuration, it will hold a
bit-line at stable voltage even after
the forcing voltage is removed
Entire row is refreshed
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WRITE CYCLE DIAGRAMS

DRAM WR Cycle Time
RAS_L
CAS_L
A
Row Address
Col Address
Junk
Row Address
Col Address
Junk
OE_L
WE_L
D
Junk
Data In
WR Access Time
Early Wr Cycle: WE_L asserted before CAS_L
Junk
Data In
Junk
WR Access Time
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Late Wr Cycle: WE_L asserted after CAS_L
Source: EECS 150 David Culler, EECS UCB
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REFRESH
Refresh during read/write is
not enough
Typically each row must be
refreshed every 64 ms or less
Refresh logic is provided in a
DRAM controller
Refresh can be done every row
in a burst of activity involving
all rows every 64 ms or one row
at a time staggered throughout
the 64 ms interval
Some counter is required
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DRAM LAYOUT
Requirements to DRAM cells:
Sufficient retention time
Minimal leakage currents through capacitor and
transistor
Sufficient signal voltage
Storage capacitance of 30 fF or more
Use of high- dielectrics, large area of capacitor
Low soft error rate
Increase durability against radiation
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DRAM LAYOUT
PLANAR CAPACITOR
LAYOUT
First DRAM cell
One transistor and
capacitor
Planar capacitor
Has scaling issues as
thickness reduction
can be limited
Layout of Planar Capacitor Memory Cell

Source: US patent US3387286
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DRAM LAYOUT
TRENCH CAPACITOR CELL
Suitable for embedded DRAM
Comprises a trench etched into the substrate
Trench is typically filled with n+ doped poly
which serves as one plate of capacitor
The second plate is formed by outdiffusing
n+ dopants from a dopant source into region
of the substrate surrounding the lower
portion of the trench
A dielectric layer separates two plates
To prevent or reduce parasitic leakage that
occurs along the upper portion of the trench
to an acceptable level, an oxide collar of
sufficient thickness is provided therein
Trench Capacitor Cell Layout
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DRAM LAYOUT
STACKED CAPACITOR CELL
Capacitor stack on top of chip
surface
Various designs
possible(crown, fin, etc.)
Less susceptible to radiation
Surface area considerably less
then trench capacitor
Taller Structures causes
mechanical instability
problems
Wiring difficult because of
height difference
Stacked Capacitor Cell Layout
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ENHANCER DRAMs: SDRAM

Synchronous DRAMs
Made by adding a synchronous interface between
basic DRAM circuitry and control coming from offchip
Makes DRAM operation faster
Clock signals triggers response to inputs
All commands and operations to and from the
DRAM executed on the rising edge of a master clock
signal common to all SDRAMs
Data storage area is divided into several banks,
allowing the chip to work on several memory access
commands at a time
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TIMING PARAMETERS
tCAS: Number of clock cycles needed to access a certain
column of data in SDRAM. CAS latency is the column
address strobe time, sometimes referred to as tCL
tRCD (row address to column address delay time):
Number of clock cycles delay required between an active
command RAS and a CAS.
tRP (row precharge time): Number of clock cycles needed
to terminate access to an open row of memory, and open
access to the next row.
tRAS (row active time): Minimum number of clock cycles
needed to access a certain row of data in RAM between
the data request and the precharge command
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A LOOK AT ACTUAL VALUES

To have an idea about
actual DRAM timings refer
the label on a DRAM:
1333 MHz is the maximum
clock speed that memory
can support
Real clock is half of labelled
speed
Data can be transferred at
10,664 MB/sec
7-7-7-18 denotes 7 clock
cycles of CAS Latency, RAS
to CAS delay and RAS
precharge time, & 18 cycles
row active time
A label on DRAM indicating timings

Source: hardwaresecrets.com/article/Understanding-RAM-Timings
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ENHANCER DRAMs: DDR SDRAM

Double Data-Rate Synchronous DRAM
Data transferred on both the rising and falling edges
of the clock signal. Hence data transfer rate is twice
the clock frequency.
DDR SDRAM succeeded by DDR2 SDRAM and
DDR3 SDRAM each with an increase in the
bandwidth and speed of operation
Current PCs use DDR3 SDRAM which gives a
maximum transfer rate of 6400 MB/s.
DDR3 standard permits capacities as high as 8 GB
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Enhanced DRAMs
Fast Page Mode DRAM (FPM DRAM)
All data for a page stored in sense amplifiers after
trailing edge of RAS clock
CAS used to cycle through all addresses on the page
and access time reduces to tCAC
Video DRAM (VRAM)
Mostly used for video memory

Dual ported (allows concurrent reads and writes)
Extended Data Out DRAM (EDO DRAM)

New access cycle can be started, keeping the data
output of the previous cycle active
Allows pipelining, resulting in improved speed
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ERRORS IN DRAM
Memory error caused in DRAM when a logic
state of 1 is detected as 0 or vice-versa
HARD ERRORS
Caused by physically damaged components and
design error
irreversible
SOFT ERRORS
Data alterations (single event upset)
Caused by particle radiation
Reversible for DRAM
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SOFT ERRORS
SYSTEM-LEVEL SOFT ERRORS
Caused when data being processed is hit with a noise
phenomenon (e.g. data on a data bus)
Noise interpreted as data bit, causing errors in addressing or
processing program code.
Bad data bit saved in memory can cause problems at a later time
CHIP-LEVEL SOFT ERRORS

Caused by radioactive decay of chips material atoms releasing particles
-particles strike memory cells and cause them to change state
Actual structure of the chip unaffected
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CAUSES OF SOFT ERRORS

Alpha particles
Radioactive contaminants in packaging material
(238U, 232Th, 210Po)
Energy up to 20 MeV
Dominant problem in early devices
Cosmic radiation
Neutrons, protons created by nuclear reaction in
stratosphere
Energy up to 1000 MeV
Rate of upsets depends on height of operation
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Memory
LOW ENERGY -PARTICLES

Generated by radioactive decay
of trace U-238 & Th-232 in
quartz filler or from Po-210 in
lead bumps
Travel through the
semiconductor material and
affect the electron distribution
causing charge drifts
Logic state of memory cell
changed if drift at node exceeds
critical charge
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COSMIC PARTICALES
Neutrons, protons created by nuclear reaction in
stratosphere
Different from -particles since they do not interact
coulombically with the semiconductor material
Neutrons undergo neutron capture by silicon nucleus
followed by decay producing -particles & other heavy
ions generating electron-hole pairs with higher energies
Neutrons particularly troublesome since
Penetrate most man-made construction
Neutron flux is higher in higher altitudes
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ERROR CORRECTION
Using redundant memory bits and memory controllers
that exploit these bits
Error Correcting codes e.g. SECDED Hamming code
ECC-capable memory controller in modern PCs can
typically detect and correct errors of a single bit per 64bit "word", and detect (but not correct) errors of two bits
per 64-bit word
Single event upsets due to cosmic radiation dropping
dramatically with process geometry
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DEVELOPMENT OVER YEARS
Comparison of processor performance vs RAM capacity over years
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PERFORMANCE OVER YEARS
Performance of DRAM over years

Source: MEMORY 2013 Trends
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DRAM MARKET DISTRIBUTION
Market distribution of DRAM

Source: HIS iSuppli research
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POTENTIAL IMPROVEMENTS
Retain adequate storage capacitance with reduced
feature size
High-dielectrics (ZrO2, HfO2)
Ultra high-dielectrics (perovskite)
Low leakage current in access transistor and storage

capacitor
Suppress sub-threshold leakage current
Replacement of planar FET (FinFET)
Reducing soft errors

Meeting ever increasing demand for high density,
low cost, high speed
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FUTURE OF RAM
Thyristor RAM (T- RAM)
High density and high speed
Uses negative differential resistance
Twin transistor RAM (TT-RAM)

Capacitorless DRAM
Uses floating body effect inherent in a silicon on
insulator
Ferroelectric RAM (Fe-RAM)

Non-volatile
Uses a ferroelectric layer instead of a dielectric
layer to
achieve non-volatility.
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Memory
THANK YOU!!!
12/11/2013

Dynamic Random Access Memories (Drams) : Gagandeep Singh Iit Guwahati

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Dynamic random access

Computer memory hierarchy

RANDOM ACCESS MEMORY (RAM)

STATIC RANDOM ACCESS MEMORY (SRAM)

DYNAMIC RANDOM ACCESS MEMORY (DRAM)

DRAM CELL STRUCTURE

READ OPERATION (Contd)

Sense Amplifier Schematic

EARLY READ SEQUENCING

Valid Data Out after access time

LATE READ SEQUENCING

READ CYCLES DIAGRAM

Source: EECS 150 David Culler, EECS UCB

WRITE CYCLE DIAGRAMS

Early Wr Cycle: WE_L asserted before CAS_L

Layout of Planar Capacitor Memory Cell

Trench Capacitor Cell Layout

Stacked Capacitor Cell Layout

ENHANCER DRAMs: SDRAM

A LOOK AT ACTUAL VALUES

A label on DRAM indicating timings

ENHANCER DRAMs: DDR SDRAM

Video DRAM (VRAM)

Mostly used for video memory

Extended Data Out DRAM (EDO DRAM)

CHIP-LEVEL SOFT ERRORS

CAUSES OF SOFT ERRORS

LOW ENERGY -PARTICLES

DEVELOPMENT OVER YEARS

Comparison of processor performance vs RAM capacity over years

PERFORMANCE OVER YEARS

Performance of DRAM over years

DRAM MARKET DISTRIBUTION

Market distribution of DRAM

Low leakage current in access transistor and storage

Reducing soft errors

Twin transistor RAM (TT-RAM)

Ferroelectric RAM (Fe-RAM)

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