ENEE640

Virtuoso Schematic, Layout, and Verification

University of Maryland ECE Department

Domenic Forte

Virtuoso Schematic, Layout, and Verification

This tutorial will cover the basic steps involved in

Accessing the Cadence tool called Virtuoso on GLUE

Creating a schematic in the Virtuoso Schematic Editor
Creating and extracting a layout with the Virtuoso Layout Editor
Verifying the layouts manufacturability with Design Rule Checking
Verifying the layouts functionality with Layout Versus Schematic (LVS)

The document covers schematic and layout creation of a simple NMOS transistor for illustrative
purposes. More details about using Virtuoso can be found in the References section and under
cdnshelp. To launch Cadence documentations application, type cdnshelp at the terminal.
Notes: We shall assume that you are using a Windows Operating System and are familiar with
basic Linux system commands (creating directories, deleting files, etc.).

Contents
INITIALIZATION................................................................................................................................1
SET UP AND START VIRTUOSO........................................................................................................2
CREATE A NEW LIBRARY.................................................................................................................3
CREATE A SCHEMATIC
CREATE AND VERIFY

WITH

VIRTUOSO.........................................................................................4

A LAYOUT WITH

VIRTUOSO.........................................................................6

REFERENCES..................................................................................................................................13

INITIALIZATION
If you are working in Windows, the following software will be needed for the tutorial.
1. Xming. Xming is a free, open source X-Windows terminal emulator (X Server) that runs
on Microsoft Windows computers. In simplest terms, Xming allows you to run an X
application after connecting to a remote server using SSH. It is available at
http://sourceforge.net/projects/xming/ and should be installed prior to starting the tutorial.
2. PuTTY. PuTTY is a free and open source terminal emulator application which can act as
a client for the SSH, Telnet, rlogin, and raw TCP computing protocols and as a serial
console client. You will use PuTTY to connect to the GLUE server and access Virtuoso. It
is available at http://www.chiark.greenend.org.uk/ ~sgtatham/putty/download.html and
should be installed prior to beginning the tutorial.

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

SET

UP AND START

Domenic Forte

VIRTUOSO

1. Start Xming. If Xming is started correctly, it should appear in your system tray.
2. Start and configure PuTTY. In the Category portion of the PuTTY Configuration
window (lefthand side), select the subcategory SHH of Connection. Then, select
X11 which opens the Options controlling SSH X11 forwarding. Under X11 forwarding,
make sure that Enable X11 forwarding is checked (see Figure 1). Next, go to the
subcategory Data of Connection. Under Login details, enter your Auto-login
username (see Figure 2). Note you username should be your login name for accessing
MyUMD, testudo, campus e-mail, etc. Return to the Basic options for your PuTTY
session by clicking Session in the Category portion of the Configuration window.
Under Host name and port, write linux.glue.umd.edu and 22 respectively. For
Connection type, choose SSH (see Figure 3).

Figure 1: Set X11 Forwarding

Figure 2: Set Username

Figure 4: Command Prompt

Figure 3: Setup and Save Session Options

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

3. Save the PuTTY settings. In order to avoid repeating these steps the next time you want
to use Virtuoso, you should save the session. This can be done by naming the session in
the Saved Sessions bar and clicking the Save button. If done correctly, the name of your
session will appear in the box next to the Load, Save, Delete buttons. To retrieve your
settings, select the session you named and click the Load button (see Figure 3).
4. Open a PuTTY session. Click the Open button at the bottom of the window. In the
terminal window that opens, you will be prompted for your password. Note you password
should be the one you use for accessing MyUMD, testudo, campus e-mail, etc. The
command prompt will appear upon entering your password (see Figure 4).
5. Virtuoso Setup. Create a directory (mkdir) you want to put your designs in and change
(cd) to that directory. In the terminal, type the command tap cadenceIC6 and click
enter. Note this command is required every time you begin a new PuTTY session and
gives you access to the Cadence tools. In order to use Virtuoso, youll also need to setup
the North Carolina State University CDK design technology files. To do so, simply run
the following two commands
(i)
cp
/afs/glue.umd.edu/department/enee/software/cadenceIC6/l
inux/inst/ncsu-cdk-1.6.0.beta/.cdsinit .
(ii)
cp
/afs/glue.umd.edu/department/enee/software/cadenceIC6/l
inux/inst/ncsu-cdk-1.6.0.beta/cdssetup/cds.lib .
to copy the two files to your current directory (note that there is a space before the last
period).
6. Launch Virtuoso. Type virtuoso & and press enter. After a few moments, Virtuoso
should start and the Command Interface Window will appear (see Figure 5).

Figure 5: Command Interface Window (CIW)

Note: If you are having trouble logging into GLUE or launching Virtuoso, please contact
the ECE helpdesk at ecehelp@ece.umd.edu. For additional documentation on Virtuoso,
type cdnshelp in the terminal after the above tap commands.

CREATE

A NEW LIBRARY

When starting a design in Cadence, the first thing to do is to create a library where you can store
your designs. Every library is associated with a technology file and it is the technology file that

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

supplies all the color maps, layer maps, design rules, extraction parameters required to view,
design, simulate, and fabricate your design. To create a new library, goto ToolsLibrary
Manager in the CIW. Note if you performed the above Virtuoso Setup steps properly, you will
see the NCSU technology libraries in the directory (see Figure 6).Then in the Library Manager
window, goto FileNewLibrary. When the New Library window opens, enter the name of
your library and press the OK button. Then choose Attach to an existing technology library and
press the OK button. Choose NCSU_TechLib_tmsc02 as the technology library and press
OK.
At this point, you have created a library to store your design and can start the design process. For
a full custom design, the process will proceed by creating the following: schematic, symbol, and
layout. In this tutorial, we shall focus on creating new schematics and layouts for an NMOS
transistor.

Figure 6: Library Manager with NCSU libraries

CREATE

A SCHEMATIC WITH

VIRTUOSO

1. Create a New Cell. We shall begin with the Virtuoso Schematic Editor. To create a new
cell schematic, highlight the library you created in the previous section and goto
FileNewCell View in the Library Manager. In the New File window, enter the
name of your cell. Set the view and type to schematic (see Figure 7), and then press
OK. If you receive any warnings about the version of the tool (L, XL, GXL), just keep
clicking Yes until the Schematic Editor opens.
2. Virtuoso Schematic Editor Menu. The following menu items are frequently used while
creating a layout. It may also be worthwhile to be familiarize yourself with their key
shortcut commands. Some of the menu options are also accessible via the buttons below
the menu.
File
o Save: Save your changes to the layout.
Edit
o Undo: Undo the previous commands.

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

o Redo: Redo the previous commands.

o Move: Click on any object once, move it in the schematic editor, and click
once to drop it.
o Copy: Creates a copy of any object in the schematic. Click on the object
you want to copy, move the mouse to the desired location in the
schematic, and click again to paste the copied object.
o Delete: Delete an object in the layout by choosing delete from the menu
and then clicking the object.
o Rotate: Rotate an object 90 degrees by choosing rotate from the menu and
then clicking the object.
Create
o Instance: Allows you to choose a part (transistor, gate, etc.) and place it in
the schematic. Choose the desired part by browsing the library, and then
place it by clicking once in the schematic editor.
o Pin: Create pins. Name the pin first, and then place it in the schematic by
clicking once.
o Wire: Connect wires to terminals of the parts and pins by clicking the
yellow diamonds of the parts/pins (see Figure 9). Draw wires and create
bends in the wires with additional clicks of the mouse.
3. Create a simple NMOS schematic. Create a new instance by going to CreateInstance.
In the Component Browser Window, choose the NCSU_Analog_Parts library, select
N_Transistors and then choose nmos4 for a 4-terminal NMOS (see Figure 8). Note
that you can adjust the NMOS parameters (length, width, etc.) in the Add Instance
Window, but this will not be necessary to complete the tutorial. Place the nmos4 part by
clicking the mouse in the schematic. Now we should connect the source, drain, and gate
to ground (gnd), voltage supply (vdd), and input (in) respectively. We do this by adding
I/O pins to the schematic and then creating wires. First, Goto CreatePin. In the Add Pin
window, name the first pin vdd, choose inputOutput as the direction, and then click in
the schematic to place the pin. Follow a similar procedure for ground and input pins. For
the input pin, choose input as the direction. Finally, connect the pins to the NMOS with
wires by clicking CreateWire. To connect wires to the pins, hover over the pins with
the mouse, and click the yellow diamond that appears (see Figure 9). Routing wires in the
schematic (bends, etc.) can be accomplished by clicking the mouse. When you are
finished, your schematic look similar to Figure 10. Save the schematic with FileSave.

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

Figure 7: Create new Cell layout

Figure 8: Component Browser

Figure 9: Yellow Diamond Appearing in Pin

CREATE

AND VERIFY A LAYOUT WITH

Figure 10: Completed NMOS Schematic

VIRTUOSO

1. Create a New Cell. Next, we shall discuss how to create a layout for the NMOS
transistor. To create a new cell layout, highlight the library you created in the Section III
and goto FileNewCell View. In the New File window, enter the name of your cell.
Set the view and type to layout. Then press OK. If you receive any warnings about the
version of the tool (L, XL, GXL), just keep clicking Yes until the Layout tool opens.
Note if you performed the above Virtuoso Setup steps properly, the layers (pwell, nwell,

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

etc.) in the Layers Window (snapped to the lefthand side of Virtuoso) will have different
colors as shown in Figure 11.
2. Virtuoso Menu. The following menu items are frequently used while creating a layout. It
may be worthwhile to familiarize yourself with their shortcut key commands. Some of
the menu options are also accessible via the buttons below the menu.
File
o Save: Save your changes to the layout.
Create
o Rectangle: Creates a rectangle for the current layer selected in the Layers
window. To create a rectangle, click the mouse once to start the rectangle,
then drag, then click the mouse again to finish the rectangle.
o Multipart Path: Creates a path of the layer selected in the Layers window.
Click once to begin a path then drag. To make 90 degree bends in the path,
click once. Double click to end the path.
o Instance: Used to import another existing cell view into this cell view.
Place in the layout by clicking once.
o Pin: Create pins. Pins are created in the layout similar to rectangles.
Edit
o Undo: Undo the previous commands.
o Redo: Redo the previous commands.
o Move: Click on any object once, move it in the layout, and click once to
drop in back into the layout.
o Copy: Create a copy of any object in the layout. Click on the object you
want to copy, move the mouse to the desired location in the layout, and
click again to paste the copied object.
o Stretch: Click on the edge of a rectangle and re-size it by moving the
mouse and clicking again.
o Delete: Delete an object in the layout by choosing delete from the menu
and then clicking the object.
o Basic:
Properties: Change the properties of objects in the layout (Eg. the
layer the object corresponds to).
Tools
o Ruler: Creates a ruler for you to measure features in your layout. Click
once to start the ruler, drag the mouse, and click once more to end the
ruler. The ruler will remain in the layout until deleted.
o Clear All Rulers: Deletes all rulers.
Verify
o DRC: Check the layout for design rule violations.
o Extract: Create an extracted view of the layout (used for simulations and
for comparison to schematics).

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

o Markers:
Explain: Click on the markers to see what rule was violated.
Delete all: Remove the markers after a DRC run.

Layers
Window

Figure 11: Virtuoso Window with Layers Window

3. Set Display Options. Before starting the layout, you need fix the grid sizing. In the
Virtuoso window, goto OptionsDisplay, which will open the Display Options
window. Set the grid control parameters in the right hand upper corner to the desired
values (see Figure 12). Note that the unit of each parameter is in m. You should set the
grid parameters to match the minimum feature size of your technology (i.e. ). Suggested
parameters are shown in Figure 12.

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

Figure 12: Display Options window and grid spacing

4. Drawing an NMOS Transistor. As discussed above, we will be creating an NMOS

transistor layout in this tutorial. Note that the black background in the initial layout
corresponds to a p-substrate. Since we are designing an NMOS, we can place our active
layers directly in the p-substrate. Note that building a PMOS requires you to create an nwell.
The layers required to build the NMOS are shown in Figure 13. The layers are cc, metal1,
pactive, nactive, poly, nselect, and pselect. You can create each layer using the commands
discussed in Virtuoso Menu. The order in which the layers are created is not important.
The only requirement is that all the layers should be present. Note that the size of each
rectangle is a function of the display options you choose above and should be chosen to

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

pass the rules in the selected technology file. Design rules to follow can be found at the
MOSIS website (eg. http://www.mosis.com/files/scmos/ scmos.pdf).

p-select

n-select

p-active

n-active

polysilicon
cc

metal1

Figure 13: Layers for an NMOS transistor

The NMOS is now created by merging together the layers in the window (see Figure 14).
The n-select region should cover the entire active area and the poly gate. You will need
metal and n-contacts to connect the source/drain to GND/VDD. You will also need to

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

place a contact to connect the p-substrate to ground. The p-contact is complementary to

the n-contact and is made of cc, p-active and metal1 surrounded by a p-select rectangle.

Figure 14: NMOS Transistor Layout

5. Design Rule Check. To verify that your design is correct, goto VerifyDRC. Any errors
in your design will be printed in the CIW. If your layout has errors, they will be shown
with Xs in the Editor. To get more information on your errors, goto
VerifyMarkersExplain, and then click the Xs in your layout. When your layout has
zero errors, proceed to the next step.
6. Create Pins. To complete the layout, we will need to create pins corresponding to gnd,
vdd, and input as we had done earlier for the NMOS schematic. Goto CreatePin. In the
Create Shape Pin Window (see Figure 15), write the terminal name, select Display
Terminal Name (to show the name in the layout), and select the proper I/O Type. Note
that the name and type for each pin should match the choices made in the NMOS
schematic (gnd and vdd are inputOutput type, in is input type). A pin is then added by
clicking once on the layout, dragging the mouse, and clicking again (as you would create
a rectangle). The label is then added to the layout by clicking the mouse one more time.
The gnd and vdd pins should be added to the source and drain of the NMOS (metal1
layers). The in should be added to the gate terminal of the NMOS (polysilicon layer).
Upon adding the pins, your layout should be similar to the one shown in Figure 16.

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

Figure 15: Create Shape Pin Window

Figure 16: NMOS Transistor Layout with Pins

7. Layout Extraction and Verification. The layout extraction tool is used to generate a
circuit netlist from your layout. The extracted view can be used to run Layout Versus
Schematic (LVS) or to run simulations. To run layout extraction tool, go to
VerifyExtract. The Extractor window (see Figure 17) should appear. Click on the Set

ENEE640
Virtuoso Schematic, Layout, and Verification
University of Maryland ECE Department

Domenic Forte

Switches button. In the Switches Selection Window (see Figure 18), select
Extract_parasitic_caps and Keep_labels_in_extracted_view options as shown in the
figure (hold Ctrl and click on options to select multiple options). Note that if the
Extract_parasitic_caps switch is turned on during extraction, the extraction tool
calculates the parasitic capacitances on all layers on the layout. Click OK to close set
switches dialog and click OK again on Extractor dialog to run the layout extraction. The
extraction report will appear in CIW window when finished and should hopefully be
error-free.

Figure 17: Extractor Window

Figure 18: Set Switches Window

REFERENCES
1. Ekarat Laohavaleeson, Virtuoso Schematic Composer, available at http://www.csee.
umbc.edu~cpatel2/links/315/cadence/handouts/composer_schematic.pdf
2. Ekarat Laohavaleeson and Chintan Patel, Virtuoso Layout Editor, available at
http://www.csee.umbc.edu/~cpatel2/links/315/cadence/handouts/virtuoso_layout.pdf
3. Cadence2007 Tutorial, available at http://www.cerc.utexas.edu/~jiwoo/vlsi1/lab1/
cadence_tutorial#Schematic%20Composer