FPGA/ CPLD LAB

EXPERIMENT 1
AIM : To design and simulate a half-adder and full-adder using Verilog HDL using different
modelling.

EDA TOOL USED : Xilinx ISE 8.1i

METHODOLOGY : The half adder adds two input bits and generates a carry and sum, which
are the two outputs of a half adder. The input variables of a half adder are called the augend and
addend bits. The ALU (arithmetic logic circuitry) of a computer uses half adder to compute the
binary addition operation on two bits. Half adder is used to make full adder as a full adder requires 3
inputs, the third input being an input carry i.e. we will be able to cascade the carry bit from one adder
to the other.
A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full
adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is
a bit carried in from the previous less significant stage. The full adder is usually a component in a
cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit
output, output carry and sum typically represented by the signals Cout and S. Many adder designs can
be adopted to build the ALU which is the building block of any processing element. The applications
of the half-adder and full-adder are thus unlimited.
Logic Symbol :

Truth table :
Half-adder

Full-adder

Cin

Cout

FPGA/ CPLD LAB

Diagram :

Half Adder

Full Adder

VERILOG CODE :
Gate level Modelling
Half Adder
module ha1(a, b, s, c);
input a, b;
output c,s;
and(c,a,b);
xor(s,a,b);
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endmodule
Full Adder
module fa11(a, b, c, s, ca);
input a,b,c;
output ca,s;
wire d,f,g;
xor(d,a,b); xor(s,d,c); and(f,d,c); and(g,a,b); or(ca,f,g);
endmodule
Data flow level Modelling
Half Adder
module ha_flow1(a, b, s, c);
input a,b;
output c,s;
assign {c,s}=a+b;
endmodule
Full Adder
module fa_flow1(a, b, ci, s, co);
input a,b,ci;
output co,s;
assign {co,s}=a+b+ci;
endmodule
Behavioural level Modelling
Half Adder
module ha_beh1(a, b, s, c);
input a,b;
output reg c,s;
initial
begin
c=0; s=0;
end
always @(a,b)
begin
case({a,b})
0: begin s=0; c=0; end
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1: begin s=1; c=0; end

2: begin s=1; c=0; end
3: begin s=0; c=1; end
endcase
end
endmodule
Full Adder
module fa_beh1(a, b, ci, s, co);
input a,b,ci;
output reg co,s;
initial
begin s=0; co=0;

end

always @(a,b,ci)
begin
case({a,b,ci})
0: begin s=0; co=0; end
1: begin s=1; co=0; end
2: begin s=1; co=0; end
3: begin s=0; co=1; end
4: begin s=1; co=0; end
5: begin s=0; co=1; end
6: begin s=0; co=1; end
7: begin s=1; co=1; end
endcase
end
endmodule

RTL SCHEMATIC VIEW :

Gate level Modelling

FPGA/ CPLD LAB

Half Adder

Full Adder
Data flow level Modelling

Half Adder

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Full Adder
Behavioural level Modelling

Half Adder

FPGA/ CPLD LAB

Full Adder

OUTPUT WAVEFORM :

Half Adder

Full Adder

RESULT : Half adder and Full adder are successfully implemented using different modelling and
their operations are verified through simulation.
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