Demonstration Workbook

Clock Creation and Basic Static Timing Analysis Demo Script

Clock Creation and Basic Static Timing Analysis

Demo Script
Introduction
This demonstration script provides high-level instructions on the key features to
be included with this demo.

Clock Creation
Action with Description

Point of Emphasis and Key Takeaway

Open the Vivado Design Suite

from the Start menu.

Click the Open Project link in the

Quick Start page.

Open the wave_gen design in the

C:\training\AdvVivadoTimingforPN\
demos\clock_creation directory.

Open the synthesized design from

the Flow Navigator.

Note the Critical Warning message that

appears.

Open the wave_gen_timing.XDC

file and note that there are no
timing constraints.

Why was there a critical warning when

the wave_gen_timing.xdc file does not
have any constraints?

Open the char_fifo.XDC file and

confirm the contents of the critical
warning.

After finding the line in the XDC that

generates the warning:

What does this constraint do?

Why is the critical warning

generated on this constraint?

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Clock Creation and Basic Static Timing Analysis Demo Script

Action with Description

Demonstration Workbook

Point of Emphasis and Key Takeaway

Open the Constraints Wizard (from

the Flow Navigator) to make the
initial clock constraints on the
design.

Note the "No Target Constraints"

message. Make the appropriate
constraints set and constraint file active
before making constraints with the
Right-click the constrs_1 constraints Wizard.
set (verify that it is set to active).
Right-click wave_gen_timing.xdc
and select Set as Target Constraint
File (target will appear).

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Demonstration Workbook

Clock Creation and Basic Static Timing Analysis Demo Script

Action with Description

Point of Emphasis and Key Takeaway

Open the Constraints Wizard.

The Constraints Wizard is designed to

make it as easy as possible to make
Click Next for all windows, except
complete constraint for any design
for the page that asks you to enter
an input clock frequency (set to 200 (hence all the questions). In this case,
wave_gen does not need any special
MHz).
timing constraints.
After entering this constraint (and
Note that since there was no initial
clicking Next many times) the
Summary window will acknowledge clock constraints that the wizard does
the new clock constraint. The utility not recognize any I/O pins and cannot
will then close without opening the be as helpful when clocks are defined.
So to properly use the wizard, designers
Constraints Editor.
will need to run this utility once to make
Re-open the Constraints Wizard and clocks and then a second time to make
now the tool will recognize I/O pins their I/O timing constraints (only a clock
since a clock has been defined (you constraint will be made in this demo).
will see this after clicking Next a few
times). You will have to de-activate
the input and output pins to avoid
making input and output
constraints.

In the Constraints Summary page,

click View Timing Constraints. The
Constraints Editor will then open and
show the new clock constraint and
any timing constraints associated
with IP in the design (in this case,
char_fifo).

Enter report_clocks in the Tcl

Console. Make sure to press the
<Enter> key.

Describe the contents of this report.

From clocks report, what is the input
clock to the MMCM?
How many output clocks are generated
from this MMCM?
Where is the source file for this MMCM?

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Clock Creation and Basic Static Timing Analysis Demo Script

Action with Description

Open the clk_gen.v file in the

Sources window.

Demonstration Workbook

Point of Emphasis and Key Takeaway

Verify that the signals clk_pin_p,
clk_out1, and clk_out2 are made from
the clk_core (bottom of file).
From this you will see that clk_rx and
clk_tx are out1 and out2. This matches
the output signal names from the top
of the file.

Double-click the char_fifo.xci file in

the Sources window (under
wave_gen). This will open the
Re-customize IP Wizard.

Review the output frequencies

generated by the MMCM.
Can you explain how this MMCM was
configured to produce clocks of 200
MHz and 193.75 MHz? Hint: go to the
Summary tab.

Click Report Clock Networks in the Review how the report generated
Flow Navigator.
confirms how the MMCM made the
three output clocks.
Select File > Save Constraints to
save the new constraints file.

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Demonstration Workbook

Clock Creation and Basic Static Timing Analysis Demo Script

Basic Static Timing Analysis

Action with Description

Point of Emphasis and Key Takeaway

Rerun synthesis (23 min).

Review the following:

Open the synthesized design.

Organization of the report in the GUI

Generate a Timing Summary report

from the Flow Navigator (use default
settings).

Timing summary

check_timing report

Intra-clock paths

Inter-clock paths

User-ignored paths

Unconstrained paths

Select the longest setup path for

clk_out1.

Describe the inter-clock paths and

the possible need for
synchronization circuits.
Select the longest path in the
Inter-clock Paths section

Review the following:

Path properties

Confirm the slack calculation for

hold time (clock path to source delay
plus data path delay)

Logic descriptions

Element delay and cumulative delay

Schematic generation and cross

probing to source HDL

Review the possible need for

synchronization circuits.
Review the path to show that they have
different clocks on the source and
destination flip-flops.

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Clock Creation and Basic Static Timing Analysis Demo Script

Action with Description

Generate the Report Clock

Interaction report.

Demonstration Workbook

Point of Emphasis and Key Takeaway

Review the following:

Facilitate an open-ended discussion

on fixing the design.

Color coding

Source clock/destination clock chart

Right-click options for the paths

between each clock domain.

Review the following:

Synchronization circuitry

Fixing timing problems

Need for path-specific constraints

If I do all of these things, will I fix all the

timing problems?
How accurate are these timing
numbers?
Note: In this demo, all this analysis can
be done without having to complete a
single implementation (saved huge
amount of time).

Conclusion
In this demo, you learned how to make your initial clock constraints and verify the
clocking structures built into your design using some of the most common
reports. You also used the static timing analysis capabilities of the Vivado
Design Suite to perform some basic timing verification.
References:

Supporting materials

Vivado Design Suite User Guide (Using Constraints) (UG903)

Vivado Design Suite User Guide (Design Analysis and Closure Techniques)
(UG906)

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