MINISTERE DE L'ENSEIGNEMENT SUPERIEUR ET

DE LA RECHERCHE SCIENTIFIQUE
ECOLE NATIONALE SUPERIEURE DINFORMATIQUE
TP strm_2
Anne Universitaire :
20010/2011

Quelques dexercices en vhdl

: Prsent par
BENYAGOUB MOHAMED 3siq groupe 3

Exercice 01
.Ecrire en VHDL la modlisation du circuit hexa7 segments

: Solution
; library IEEE
; use IEEE.STD_LOGIC_1164.ALL
; use IEEE.STD_LOGIC_ARITH.ALL
; use IEEE.STD_LOGIC_UNSIGNED.ALL
Uncomment the following library declaration if instantiating ---. any Xilinx primitives in this code ---; library UNISIM-; use UNISIM.VComponents.all-entity Dec7Seg is
; Port ( x : in STD_LOGIC_VECTOR (3 downto 0)
;( sig : out STD_LOGIC_VECTOR (6 downto 0)
; end Dec7Seg
architecture arch_Dec7Seg of Dec7Seg is
begin
sig<="1111110" when x=0
else "0110000" when x=1
else "1101101" when x=2
else "1111001" when x=3
else "0110011" when x=4
else "1011011" when x=5
else "1011111" when x=6
else "1110000" when x=7
else "1111111" when x=8
else "1111011" when x=9
;"-------" else
; end arch_Dec7Seg

son schema est :

Exercice 02
: Modliser en VHDL un comparateur de deux signaux de
a) 1 bit.
b) 4 bits.

: Solution
a) 01 bit :
; library IEEE
; use IEEE.STD_LOGIC_1164.ALL
; use IEEE.STD_LOGIC_ARITH.ALL
; use IEEE.STD_LOGIC_UNSIGNED.ALL
Uncomment the following library declaration if instantiating ---. any Xilinx primitives in this code ---; library UNISIM-; use UNISIM.VComponents.all-entity comp1bit is
; Port ( a : in STD_LOGIC
; b : in STD_LOGIC
;( s : out STD_LOGIC
; end comp1bit
architecture Arch_comp1bit of comp1 bit is
begin
; s<= not ( a xor b)
; end Arch_comp1bit

b) 04 bits :
; library IEEE
; use IEEE.STD_LOGIC_1164.ALL
; use IEEE.STD_LOGIC_ARITH.ALL
; use IEEE.STD_LOGIC_UNSIGNED.ALL
Uncomment the following library declaration if instantiating ---. any Xilinx primitives in this code ---; library UNISIM-; use UNISIM.VComponents.all-entity comp4bits is
; Port ( a : in STD_LOGIC_VECTOR (3 downto 0)
; b : in STD_LOGIC_VECTOR (3 downto 0)
;( s : out STD_LOGIC
; end comp4bits
architecture Arch_comp4bits of comp4bits is
begin
;' s<= '1' when ( a=b )else '0
; end Arch_comp4bits

: Exercice 03
: Modliser en VHDL un multiplexeur, 4 sommets vers 1
a) Chaque signal est sur 1 bit.
b) Chaque signal est sur 4 bits.

: Solution
a) 01 bit :
; library IEEE
; use IEEE.STD_LOGIC_1164.ALL
; use IEEE.STD_LOGIC_ARITH.ALL
; use IEEE.STD_LOGIC_UNSIGNED.ALL
Uncomment the following library declaration if instantiating ---. any Xilinx primitives in this code ---; library UNISIM-; use UNISIM.VComponents.all-entity mux1bit is
; Port ( a : in STD_LOGIC
; b : in STD_LOGIC
; c : in STD_LOGIC
; d : in STD_LOGIC
; com : in STD_LOGIC_vector ( 1 downto 0 )
;( s : out STD_LOGIC
; end mux1bit
architecture Arch_mux1bit of mux1bit is
begin
s <= a when com=0
else b when com=1
else c when com=2
;else d when com=3
; end Arch_mux1bit

a) 04 bits :
entity mux4bits is
; Port ( a : in STD_LOGIC_VECTOR (3 downto 0)
; b : in STD_LOGIC_VECTOR (3 downto 0)
; c : in STD_LOGIC_VECTOR (3 downto 0)
; d : in STD_LOGIC_VECTOR (3 downto 0)
; com : in STD_LOGIC_VECTOR (1 downto 0)
;( s : out STD_LOGIC_VECTOR (3 downto 0)
; end mux4bits
architecture Arch_mux4bits of mux4bits is
begin
s <= a when com=0
else b when com=1
else c when com=2
; else d when com=3
; end Arch_mux4bits

: Exercice 04
a) Raliser un demi-additionneur.
b) Raliser un additionneur de 08 bits.

: Solution
a) Un demi-additionneur :
; library IEEE
; use IEEE.STD_LOGIC_1164.ALL
; use IEEE.STD_LOGIC_ARITH.ALL
; use IEEE.STD_LOGIC_UNSIGNED.ALL
Uncomment the following library declaration if instantiating ---. any Xilinx primitives in this code ---; library UNISIM-; use UNISIM.VComponents.all--

entity add_1bit is
; Port ( a : in STD_LOGIC
; b : in STD_LOGIC
; c_in: in STD_LOGIC
; s : out STD_LOGIC
;( c : out STD_LOGIC
; end add_1bit

architecture arch_add_1bit of add_1bit is

begin
; s<= (c_in xor (a xor b))
; c<= (a and b) or (c_in and (a xor b))
end arch_add_1bit

b) Additionneur 08 bits :
; library IEEE
; use IEEE.STD_LOGIC_1164.ALL
; use IEEE.STD_LOGIC_ARITH.ALL
; use IEEE.STD_LOGIC_UNSIGNED.ALL
Uncomment the following library declaration if instantiating ---. any Xilinx primitives in this code ---; library UNISIM---; use UNISIM.VComponents.all-entity add_n_bits is
; Port ( a : in STD_LOGIC_VECTOR (7 downto 0)
; b : in STD_LOGIC_VECTOR (7 downto 0)
; s : out STD_LOGIC_VECTOR (7 downto 0)
; c_out : out STD_LOGIC
;( c_in : in STD_LOGIC
; end add_n_bits
architecture arch_add_n_bits of add_n_bits is
component add_1_bit port (a1,b1,c1_in : in std_logic;S1,C1 : out std_logic )
; end component
; signal c:std_logic_vector (7 downto 0)
; for all : add_1_bit use entity work.add_1bit
begin
for i in 0 to 7 generate
;g: add_1_bit port map (a(i),b(i),c(i),s(i),c(i+1))
; c(0)<=0
; c_out<=c(8)
; end arch_add_n_bits