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IFET COLLEGE OF ENGINEERING

Department of Electrical & Electronics Engineering


IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

EE2356 - MICROPROCESSOR AND MICRO CONTROLLER


LABORATORY
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

LAB MANUAL

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

STUDENT NAME

REGISTER NO

SEMESTER&SEC

YEAR

BATCH

2011 - 2015

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

Lab In charge

lab co-ordinator

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

HOD

Ex.
No

EXPERIMENTS

Page No.

8 - BIT MICROPROCESSOR (8085)


1(a) 8- bit Addition
1(b) 8 - bit Subtraction
1(c) 8- bit Multiplication

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

1(d) 8- bit Division


2(a) Ascending order
2(b) Descending order
2( c) Largest of a given numbers
2(d) Smallest of a given numbers
3(a) Code Conversion: ASCII to Hexadecimal
3(b) Code Conversion: Hexadecimal to ASCII
3(c) Code Conversion: Hexadecimal to Binary
3(d) Code Conversion: Hexadecimal to BCD

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

4
5
6

INTERFACING A/D AND D/A CONVERTER WITH 8085

Interfacing: Traffic Light Controller with 8085


6(a)Interfacing: 8251 with 8085
6(b) Interfacing: 8279 with 8085
6(c) Interfacing: 8253 with 8085
MICROCONTROLLER(8051)
7(a) Sum of elements in an array
7(b) Sum using Stack

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

7( c) Sum using call option


8(a) Interfacing: Stepper Motor with 8051
8(b) Interfacing: DAC with 8051

STUDY OF BASIC DIGITAL ICS


9
10
11

Verification of truth table for AND, OR, EXOR,


NOT, NOR, NAND, JK FF, RS FF,D FF
Implementation of Boolean Functions, Adder /
Subtractor circuits
Code converters, Encoder and Decoder

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

12 Study of Flipflops
13 Counters(synchronous and asynchronous), Shift
14
15

registers
Differentiator, Integrator
Timer IC applications

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

SYLLABUS

EE2356 - MICROPROCESSOR AND MICRO CONTROLLER LABORATORY


AIM
1. To understand programming using instruction sets of processors.
2. To study various digital & linear
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

8-bit Microprocessor
1. Simple arithmetic operations:
Multi precision addition / subtraction / multiplication / division.
2. Programming with control instructions:
Increment / Decrement, Ascending / Descending order, Maximum / Minimum of numbers,
Rotate instructions - Hex / ASCII / BCD code conversions.
3. Interface Experiments:
A/D Interfacing.
D/A Interfacing.
Traffic light controller.
4.IFETCE/
InterfaceEEE
Experiments:
Simple experiments
8279,
8254. LAB/ MANUAL/ VER 1.1
/T.ILANSEZHIAN/
III YEAR/ VIusing
SEM/8251,
EE2356/
MP&MC

8-bit Microcontroller
5. Demonstration of basic instructions with 8051 Micro controller execution, including:
Conditional jumps, looping
Calling subroutines.
Stack parameter testing
6. Parallel port programming with 8051 using port 1 facility:
- Stepper motor and D / A converter.
7. Study of Basic Digital ICs

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

(Verification of truth table for AND, OR, EXOR, NOT, NOR, NAND, JK FF, RS FF,D FF)
8. Implementation of Boolean Functions, Adder / Subtractor circuits.
9. Combination Logic; Adder, Subtractor, Code converters, Encoder and Decoder
10. Sequential Logic; Study of Flip-Flop,Counters(synchronous and asynchronous),Shift
Registers

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

LIST OF EXPERIMENTS
Ex. No

Page No.
8 - BIT MICROPROCESSOR (8085)

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

8-Bit Arithmetic operations

Addition

Subtraction

Multiplication

Division

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

Array operations

Ascending order

Descending order

Largest element in an array

Smallest element in an array

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

Code conversion

ASCII to Hexadecimal

Hexadecimal to ASCII

Hexadecimal to Binary

Hexadecimal to BCD

INTERFACING A/D AND D/A CONVERTER WITH 8085

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

5
6
76
8
9
7
10
11

Interfacing: Traffic Light Controller with 8085


Interfacing: 8251 with 8085
Interfacing: 8279 with 8085
Interfacing: 8253 with 8085
MICROCONTROLLER(8051)
Sum of elements in an array
Sum using Stack
Sum using call option
Interfacing: Stepper Motor with 8051

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

12
13

Interfacing: DAC with 8051

STUDY OF BASIC DIGITAL ICS


IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

14
15
16
17
18
19

Verification of truth table for AND, OR, EXOR,


NOT, NOR, NAND, JK FF, RS FF,D FF
Implementation of Boolean Functions, Adder /
Subtractor circuits
Code converters,
Encoder
Decoder
Study of Flipflops

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

20

Counters(Asynchronous)

21

Shift registers

22
23
24

Differentiator, Integrator
Integrator
Timer IC applications

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

8085 MICROPROCESSOR
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

Ex.No: 1

8-BIT ARITHMETIC OPERATIONS

AIM:
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

To write an assembly language program to add, subtract, multiply and divide the given
data stored at two consecutive locations using 8085 microprocessor.
8 BIT DATA ADDITION:
ALGORITHM:
1. Initialize memory pointer to data location.
2. Get the first number from memory in accumulator.
3. Get the second number and add it to the accumulator.

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

4. Store the answer at another memory location.

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

2
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

FLOW CHART:

START

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[C]

00H

[HL]

4500H

[A]

[M]

[HL]
[HL]+1
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[A]

[A]+[M]

Is there a
Carry ?

YES

NO

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[C]

[C]+1

[HL]

[HL]+1

[M]

[A]

[HL]
[HL]+1
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[M]

[C]

STOP

3
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

PROGRAM:
ADDRESS OPCODE LABEL
MNEMONICS OPERAND
COMMENT
4100
START
MVI
C,
00
Clear
C reg. VER 1.1
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/
MANUAL/

4101
4102
4103
4104
4105

LXI

H, 4500

MOV

A, M

Initialize HL reg. to
4500

Transfer first data to


accumulator
4106
INX
H
Increment HL reg. to
point next memory
Location.
4107
ADD
M
Add first number to
acc.MANUAL/
Content. VER 1.1
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/

4108
4109
410A
410B
410C
410D

L1

JNC

L1

Jump to location if
result does not yield
carry.

INR
INX

C
H

MOV

M, A

Increment C reg.
Increment HL reg. to
point next memory
Location.
Transfer the result from
acc. to memory.

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

410E

INX

410F
4110

MOV
HLT

M, C

Increment HL reg. to
point next memory
Location.
Move carry to memory
Stop the program

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

4
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

8 BIT DATA SUBTRACTION


ALGORITHM:
IFETCE/
EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

1.
2.
3.
4.

Initialize memory pointer to data location.


Get the first number from memory in accumulator.
Get the second number and subtract from the accumulator.
If the result yields a borrow, the content of the acc. is complemented and 01H is added
to it (2s complement). A register is cleared and the content of that reg. is incremented
in case there is a borrow. If there is no borrow the content of the acc. is directly taken as
the result.
5. Store the answer at next memory location.

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

5
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

FLOW CHART:

START

[C]

00H

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[HL]

4500H

[A]

[M]

[HL]

[HL]+1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[A]

[A]-[M]

NO
Is there a
Borrow ?

YES
Complement [A]
Add 01H to [A]
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[C]

[C]+1

[HL]

[HL]+1

[M]

[A]

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[HL]

[HL]+1

[M]

[C]

STOP

6
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

PROGRAM:
ADDRESS OPCODE LABEL
MNEMONICS OPERAND
COMMENT
4100
START
MVI
C,
00
Clear
C reg. VER 1.1
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/
MANUAL/

4101
4102
4103
4104
4105

LXI

H, 4500

MOV

A, M

Initialize HL reg. to
4500

Transfer first data to


accumulator
4106
INX
H
Increment HL reg. to
point next mem.
Location.
4107
SUB
M
Subtract first number
from
acc. Content.
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/
MANUAL/
VER 1.1

4108
4109
410A

JNC

L1

Jump to location if
result does not yield
borrow.

410B
410C

INR
CMA

410D
410E

ADI

01H

Increment C reg.
Complement the Acc.
content
Add 01H to content of
acc.

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

410F

L1

INX

4110

MOV

M, A

4111

INX

4112
4113

MOV
HLT

M, C

Increment HL reg. to
point next mem.
Location.
Transfer the result from
acc. to memory.
Increment HL reg. to
point next mem.
Location.
Move carry to mem.
Stop the program

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1 7

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

8 BIT DATA MULTIPLICATION:


ALGORITHM:
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

LOGIC: Multiplication can be done by repeated addition.


1.
2.
3.
4.
5.
6.
7.
8.

Initialize memory pointer to data location.


Move multiplicand to a register.
Move the multiplier to another register.
Clear the accumulator.
Add multiplicand to accumulator
Decrement multiplier
Repeat step 5 till multiplier comes to zero.
The result, which is in the accumulator, is stored in a memory location.

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

8
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

FLOW CHART:
START

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[HL] 4500

B M

[HL] [HL]+1

SEM/
00 EE2356/ MP&MC LAB/ MANUAL/ VER 1.1
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/AVI

C 00

[A] [A] +[M]

Is there

NO

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

any carry
YES
C C+1

B B-1
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

NO

IS B=0
YES
A

9
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

A
[HL]
[HL]+1
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[M]

[HL]

[M]

[A]

[HL]+1

[C]

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

STOP

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

10
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

PROGRAM:
ADDRESS OPCODE LABEL
MNEMONICS OPERAND COMMENT
4100
START
4500 LAB/
Initialize
HL reg.
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VILXI
SEM/ EE2356/H,
MP&MC
MANUAL/
VERto1.1

4101
4102
4103

MOV

B, M

4104

INX

4105
4106
4107

MVI

A, 00H

Transfer first data to


reg. B
Increment HL reg. to
point next mem.
Location.
Clear the acc.

MVI

C, 00H

Clear C reg for carry

4500

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

4108
4109
410A

L1

ADD

JNC

NEXT

Add multiplicand
multiplier times.
Jump to NEXT if there
is no carry

410B
410C
410D
INR
C
Increment C reg
410E
NEXT
DCR
B
Decrement B reg
410F
JNZ
L1
Jump
to L1 if VER
B is not
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/
MANUAL/
1.1

4110
4111
4112

INX

4113

MOV

M, A

4114

INX

zero.
Increment HL reg. to
point next mem.
Location.
Transfer the result from
acc. to memory.
Increment HL reg. to
point next mem.
Location.

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

4115

MOV

4116

HLT

M, C

Transfer the result from


C reg. to memory.
Stop the program

11

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

8 BIT DIVISION:
ALGORITHM:
LOGIC:EEE
Division
is done using the
methodVIRepeated
subtraction.
IFETCE/
/T.ILANSEZHIAN/
III YEAR/
SEM/ EE2356/
MP&MC LAB/ MANUAL/ VER 1.1

1.
2.
3.
4.

Load Divisor and Dividend


Subtract divisor from dividend
Count the number of times of subtraction which equals the quotient
Stop subtraction when the dividend is less than the divisor .The dividend now becomes
the remainder. Otherwise go to step 2.
5. stop the program execution.

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

12
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

[HL] 4500
FLOWCHART:

START

B 00

A M

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

YES

[HL] [HL]+1

[M]

[A]

A A+ M
M A-M

[HL]

[HL]+1

B B-1
[B] [B] +1

[M]
[HL]

IS A<0

[B]

[HL]+1

STOP
IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

NO

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

13

IFETCE/ EEE /T.ILANSEZHIAN/ III YEAR/ VI SEM/ EE2356/ MP&MC LAB/ MANUAL/ VER 1.1

PROGRAM:
ADDRESS OPCODE LABEL
4100
4101

MNEMONICS
MVI

OPERAND
B,00

COMMENTS
Clear B reg for quotient

4102
4103
4104
4105

LXI

H,4500

Initialize HL reg. to
4500H

MOV

A,M

4106

INX

SUB

INR

Transfer dividend to
acc.
Increment HL reg. to
point next mem.
Location.
Subtract divisor from
dividend
Increment B reg

4107
4108

LOOP

4109
410A
410B
410C
410D
410E

JNC

LOOP

ADD
DCR
INX

M
B
H

410F

MOV

M,A

Jump to LOOP if
result does not yield
borrow
Add divisor to acc.
Decrement B reg
Increment HL reg. to
point next mem.
Location.
Transfer the remainder
from acc. to memory.

4110

INX

4111

MOV

M,B

4112

HLT

Increment HL reg. to
point next mem.
Location.
Transfer the quotient
from B reg. to memory.
Stop the program

OBSERVATION:
14

ADDITION:
S.NO

INPUT
ADDRESS
DATA

OUTPUT
ADDRESS
DATA

1
2

4500
4501
4500
4501

4502
4503
4502
4503

INPUT
ADDRESS
DATA
4500

OUTPUT
ADDRESS
DATA
4502

SUBTRACTION:
S.NO
1

4501
4500
4501

4503
4502
4503

INPUT
ADDRESS
DATA
4500
4501

OUTPUT
ADDRESS
DATA
4502
4503

MULTIPLICATION:
S.NO
1

4500
4501

4502
4503

INPUT
ADDRESS
DATA
4500
4501
4500

OUTPUT
ADDRESS
DATA
4502
4503
4502

DIVISION:
S.NO
1
2

4501

4503

15

RESULT:
Thus the addition, subtraction, multiplication and division of two numbers was
performed using the 8085 microprocessor.
16

Ex.No: 2

AIM:

SORTING OF AN ARRAY

To write an assembly language program to arrange an array of data in ascending and


descending order and to find the smallest and largest data among the array.

ASCENDING ORDER
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first number is larger than second then I
interchange the number.
3. If the first number is smaller, go to step 4

4. Repeat steps 2 and 3 until the numbers are in required order

17

FLOWCHART:

YES

START
[B] 04H
[HL] [8100H]

IS
[C] 04H

[A] < [HL]?


NO

[A] [HL]
[HL] [HL] + 1

[D] [HL]

[HL] [A]

[C] [C] - 01 H
[HL] [HL] - 1
A
[HL] [D]
[HL] [HL] + 1
18

IS
[C] = 0?
YES
[B] [B]-1

NO

IS
[B] = 0?
YES
STOP

NO

19

PROGRAM:
ADDRESS OPC
ODE
4100

LABEL

MNEMONICS
MVI

OPERA
ND
B,04

COMMENTS
Initialize B reg with

4101
4102
4103
4104
4105
4106
4107

LOOP 3

LOOP2

LXI

H,4200

MVI

C,04

MOV

A,M

number of comparisons
(n-1)
Initialize HL reg. to
4200H
Initialize C reg with no.
of comparisons(n-1)
Transfer first data to
acc.

4108

INX

4109
410A
410B
410C
410D

CMP
JC

M
LOOP1

MOV

D,M

410E

MOV

M,A

Increment HL reg. to
point next memory
location
Compare M & A
If A is less than M then
go to loop1
Transfer data from M to
D reg
Transfer data from acc
to M

410F
4110

DCX
MOV

H
M,D

4111
4112
4113
4114
4115
4116
4117
4118

INX
DCR
JNZ

H
C
LOOP2

DCR
JNZ

B
LOOP3

LOOP1

Decrement HL pair
Transfer data from D to
M
Increment HL pair
Decrement C reg
If C is not zero go to
loop2
Decrement B reg
If B is not Zero go to
loop3

4119
411A

HLT

Stop the program

20

DESCENDING ORDER

ALGORITHM:

1. Get the numbers to be sorted from the memory locations.


2. Compare the first two numbers and if the first number is smaller than second then I
interchange the number.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order

21

FLOWCHART:

NO

START
[B] 04H

[HL] [8100H]
IS
[C] 04H
[A] [HL]

[A] < [HL]?


YES
[D] [HL]

[HL [HL] + 1
[HL] [A]

[HL] [HL] - 1

[HL] [D]
[HL] [HL] + 1

[C] [C] - 01 H
A

22

IS
[C] = 0?
YES
[B] [B]-1

NO

IS
[B] = 0?
YES
STOP

NO

23

PROGRAM:
ADDRE
SS
4100

OPCO
DE

LABEL

MNEM
ONICS
MVI

OPER
AND
B,04

COMMENTS
Initialize B reg with number

4101
4102
4103
4104
4105
4106
4107
4108
4109
410A

LOOP 3

LOOP2

LXI

H,4200

MVI

C,04

MOV
INX

A,M
H

CMP
JNC

M
LOOP1

of comparisons (n-1)
Initialize HL reg. to
4200H
Initialize C reg with no. of
comparisons(n-1)
Transfer first data to acc.
Increment HL reg. to point
next memory location
Compare M & A
If A is greater than M then go

410B
410C
410D
410E
410F
4110
4111
4112
4113
4114
4115

to loop1

LOOP1

MOV
MOV
DCX
MOV
INX
DCR
JNZ

D,M
M,A
H
M,D
H
C
LOOP2

Transfer data from M to D reg


Transfer data from acc to M
Decrement HL pair
Transfer data from D to M
Increment HL pair
Decrement C reg
If C is not zero go to loop2

4116
4117
4118
4119
411A

DCR
JNZ
HLT

B
LOOP3

Decrement B reg
If B is not Zero go to loop3
Stop the program

24

LARGEST ELEMENT IN AN ARRAY


ALGORITHM:

1. Place all the elements of an array in the consecutive memory locations.


2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next
element).

7. If the accumulator content is smaller, then move the memory content


(largest element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.

25

FLOW CHART:
START
[HL] [8100H]

[B] 04H
[A] [HL]
[HL [HL] + 1

NO

IS
[A] < [HL]?
YES
[A] [HL]
[B] [B]-1

IS
[B] = 0?
YES
[8105] [A]
STOP

NO

26

PROGRAM:
ADDRE
SS
4101
4102

OPCO
DE

LABEL

MNEM
ONICS
LXI

OPER
AND
H,4200

COMMENTS
Initialize HL reg. to
4200H

4103
4104
4105
4106
4107
4108
4109
410A
410B
410C

LOOP1

MVI

B,04

MOV
INX

A,M
H

CMP
JNC

M
LOOP

MOV

A,M

Initialize B reg with no. of


comparisons(n-1)
Transfer first data to acc.
Increment HL reg. to point
next memory location
Compare M & A
If A is greater than M then go
to loop
Transfer data from M to A reg

410D
410E
410F
4110
4111
4112
4113
4114

LOOP

DCR
JNZ

B
LOOP1

Decrement B reg
If B is not Zero go to loop1

STA

4205

Store the result in a memory


location.

HLT

Stop the program

27

SMALLEST ELEMENT IN AN ARRAY


ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.

2. Fetch the first element from the memory location and load it in the accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next
element).

7. If the accumulator content is smaller, then move the memory content


(largest element) to the accumulator. Else continue.
8. Decrement the counter by 1.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.

28

FLOW CHART:
START
[HL] [8100H]

[B] 04H
[A] [HL]
[HL [HL] + 1

YES

IS
[A] < [HL]?
NO
[A] [HL]
[B] [B]-1

IS
[B] = 0?
YES
[8105] [A]
STOP

NO

29

PROGRAM:
ADDRE
SS

OPCO
DE

LABEL

MNEM
ONICS

OPER
AND

COMMENTS

4101
4102
4103
4104
4105
4106
4107
4108
4109
410A

LOOP1

LXI

H,4200

MVI

B,04

MOV
INX

A,M
H

CMP
JC

M
LOOP

Initialize HL reg. to
4200H
Initialize B reg with no. of
comparisons(n-1)
Transfer first data to acc.
Increment HL reg. to point
next memory location
Compare M & A
If A is lesser than M then go
to loop

410B
410C
410D
410E
410F
4110
4111
4112
4113
4114

LOOP

MOV
DCR
JNZ

A,M
B
LOOP1

STA

4205

HLT

Transfer data from M to A reg


Decrement B reg
If B is not Zero go to loop1
Store the result in a memory
location.
Stop the program

30

OBSERVATION:
A. ASCENDING ORDER
INPUT

OUTPUT

MEMORY
LOCATION
4200
4201
4202
4203
4204

DATA

MEMORY
LOCATION
4200
4201
4202
4203
4204

B. DESCENDING ORDER
INPUT

OUTPUT

DATA

MEMORY
LOCATION
4200
4201
4202
4203
4204

DATA

MEMORY
LOCATION
4200
4201
4202
4203
4204

C. SMALLEST ELEMENT
INPUT

OUTPUT

DATA

MEMORY
LOCATION
4200
4201
4202
4203
4204

DATA

MEMORY
LOCATION
4205

D. LARGEST ELEMENT
INPUT

OUTPUT

DATA

MEMORY
LOCATION
4200
4201
4202
4203
4204

DATA

MEMORY
LOCATION

DATA

4205

31

RESULT:
Thus the sorting operations of arranging an array in ascending, descending order and
the largest and smallest element were found using the 8085 microprocessor.

32

Ex.No: 3
AIM:

CODE CONVERSIONS

To write an assembly language program to perform the conversions of ASCII to


hexadecimal number, hexadecimal to ASCII, hexadecimal to decimal number, binary to
hexadecimal number and hexadecimal to binary number.

ASCII TO HEXADECIMAL
ALGORITHM:
1. Start the program
2. Load the data from address 4200 to A
3. Move data from accumulator to C

4.
5.
6.
7.
8.
9.

Move data from M to HL pair to accumulator


Subtract the data 30 from A
Decrement content of register
Stop the program if C is zero
Jump to Step 5
End the program

33

FLOWCHART:
Start

Set the ASCII value

Subtract 30 from A

Decrement the register content

Check
for
Carry?

Store the hex value

Stop
NO
Subtract 07 from A

YES

34

PROGRAM:
ADDRE
SS
4100

OPCO
DE

LABEL

MNEM
ONICS
LDA

OPER
AND
H,4200

COMMENTS
Load data 4200 to A

4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B

LOOP 1

MOV C,A
LXI

4F
H,4201

Move data from A to C


Load address 4201 in HL

LXI

D,4301

Load address 4301 in DF

MOV A,M
SUI

30

Move data from M to A


Subtract 30 from A

410C
410D

STAX D

410E

DCR C

410F
4110
4111
4112

JZ
INX H

LOOP

Store data from


accumulator to DE
Decrement from C
register
Stop program if C is 0
Increment HL register
pair

4113

INX D

4114
4115
4116
4117

JMP
LOOP

HLT

LOOP 1

Increment DE register
pair
Jump to 410A
Stop

35

HEXADECIMAL TO ASCII
ALGORITHM:

1.
2.
3.
4.
5.
6.
7.
8.
9.

Start the program


Load the data from address 4200 to A
Move data from accumulator to C
Move data from M to HL pair to accumulator
Add the data 30 to A
Decrement content of register
Stop the program if C is zero
Jump to Step 5
End the program

36

FLOWCHART:

Start

Set the ASCII value

Add 30 to A

Decrement the register content

Check
for
Carry?

NO

YES

Store the decimal value

Stop

37

PROGRAM:
ADDRE
SS
4100

OPCO
DE

LABEL

MNEM
ONICS
LDA

OPER
AND
H,4200

COMMENTS
Load data 4200 to A

4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B

LOOP 1

MOV C,A
LXI

4F
H,4201

Move data from A to C


Load address 4201 in HL

LXI

D,4301

Load address 4301 in DF

MOV A,M
ADI

30

Move data from M to A


Subtract 30 from A

410C
410D

STAX D

410E

DCR C

410F
4110
4111
4112

JZ
INX H

LOOP

Store data from


accumulator to DE
Decrement from C
register
Stop program if C is 0
Increment HL register
pair

4113

INX D

4114
4115
4116
4117

JMP
LOOP

HLT

LOOP 1

Increment DE register
pair
Jump to 410A
Stop

38

HEXADECIMAL TO BINARY
ALGORITHM:

1. Start the program


2. Move the content of memory to accumulator
3. Move data 0B o register B
4. Increment the content of HL register pair
5. Rotate the accumulator right
6. Jump to the specified address if carry generated
7. Move 00 to memory
8. Jump to specified address if there is no zero
9. Move 01 to memory
10. Jump to specified address if there is no zero
11. End the program

39

FLOWCHART:
Start
Load address in HL pair

Move data from M to A

Initialize counter B to 08

Increment HL register pair

Rotate accumulator right


Move data from 00 to M

Check for
Carry?
NO

Move data from 01 to M


Decrement B register

NO
If B=0?
YES
Stop

YES

40

PROGRAM:
ADDRE
SS
4100
4101

OPCO
DE

LABEL

MNEM
ONICS
LXI

OPERAND
H,4200

COMMENTS
Load address in HL pair

4102
4103
4104
4105
4106
4107
4108
4109
410A

MOV A,M
MVI B
L3

08

INX H
RRC
JC

L1

Move content of M to A
Move 0B to register pair
Increment the content of
HL pair
Rotate accumulator right
Jump to specified address
if carry

410B
410C
410D
410E
410F
4110
4111
4112
4113
4114

MVI M
JMP

00
L2

Move 00 to M
Decrement B register

L1

MVI M

01

Move 01 to M

L2

DCR B
JNZ

L3

Decrement B by 1
Jump to the specified
address if no zero

4115

HLT

Stop the program

41

BINARY TO HEXADECIMAL
ALGORITHM:
1. Start the program
2. Load the address in HL pair

3. Move the content of memory to accumulator


4. Add the content of accumulator with previous content of accumulator
5. Move the content of B to accumulator
6. Add the content of accumulator with previous content of accumulator
7. Repeat step 6
8. Add B with accumulator content
9. Increment H by 1
10. Move content of M to A
11. End the program

42

FLOWCHART:
Start
Load address in HL pair

Move data from M to A

Add content of A to register B

Add content of A with itself

Add content of A to register B

Increment HL reg pair


Add content of M with accumulator

Increment HL reg pair content

Move content of M to accumulator

Stop

43

PROGRAM:
ADDRE
SS
4100
4101

OPCO
DE

LABEL

MNEM
ONICS
LXI

OPERAND
H,4150

COMMENTS
Load address in HL pair

4102
4103
4104

MOV M,A
ADD A

4105

MOV B,A

4106

ADD A

4107
4108
4109

ADD B
INX H
ADD M

Move content of A to M
Add A content with
previous content of A
Move the content from
A to B
Add A content with
previous content of A
Add B content with A
Increment H by 1
Add M content with A

410A
410B
410C

INX H
MOV M,A
HLT

Increment H by 1
Move content of A to M
Stop the program

44

HEXADECIMAL TO DECIMAL
ALGORITHM:
1. Start the program
2. Load the address in HL pair

3. Move the content from HL to A


4. Subtract 64 from A
5. Increment BC pair
6. Jump to address 4207
7. Subtract 0A from A
8. Increment HL pair
9. Rotate accumulator left
10. Increment HL pair
11. End the program

45

FLOWCHART:
Start

Load address in HL pair


Initialize D register
Clear accumulator

Move HL to C register
Add 01 with A
Adjust A to BCD
NO
Check
Carry?

Increment D register

Increment C register
NO

Move D to accumulator
Store A in 4150 H

Check
Carry?
YES
Store A in 4151 H

Stop

YES

46

PROGRAM:
ADDRE
SS
4100

OPCO
DE

LABEL

MNEM
ONICS
LXI H

OPER
AND
4150

COMMENTS
Load data from 4150 to HL pair

4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B

L4

LXI B

0000

Load data from address to BC

MOV A,M
SUI

64

Move the content from HL to A


Subtract 64 from A

JC

L1

Stop if A has carry

410C
410D
410E
410F
4110
4111
4112
4113
4114
4115
4116

INR B
JMP

L4

Increment BC
Jump to specified address

L1

ADI

64

Add 64 to A

L3

SUI

0A

Subtract 0A from A

JC

L2

Stop if A has carry

4117
4118
4119
411A
411B
411D
411E
411F
4120
4121
4122

L2

INR C
JNC
ADI
INX H
MOV M,B
MOV B,A
MOV A,B
RLC
RLC

L3
0A

Increment HL
Stop if A has no carry
Add 0A to A
Increment HL
Move B to M
Move A to B
Move B to A
Rotate accumulator
Rotate accumulator

4123
4124
4125
4126
4127
4128

RLC
RLC
ADD B
INX H
MOV M,A
HLT

Rotate accumulator
Rotate accumulator
Add B to A
Increment H by 1
Move content of A to M
Stop the program
47

OBSERVATION:
A. ASCII TO HEXADECIMAL
INPUT

OUTPUT

MEMORY
LOCATION
4201

DATA

MEMORY
LOCATION
4301

DATA

B. HEXADECIMAL TO ASCII
INPUT
MEMORY
DATA
LOCATION
4201

OUTPUT
MEMORY
DATA
LOCATION
4301

C. HEXADECIMAL TO BINARY
INPUT
MEMORY
DATA
LOCATION
4200

MEMORY
LOCATION
4200
4201
4202
4203

OUTPUT
DATA
MEMORY
LOCATION
4204
4205
4206
4207

DATA

D. BINARY TO HEXADECIMAL
INPUT
MEMORY
DATA
LOCATION
4150
4151
E. HEXADECIMAL TO DECIMAL

OUTPUT
MEMORY
DATA
LOCATION
4152

INPUT
MEMORY
DATA
LOCATION
4150
4151

OUTPUT
MEMORY
DATA
LOCATION
4152

48

RESULT:
Thus the assembly language programs for various code conversions are executed using
8085 microprocessor.

49

EX.No:4
AIM:

INTERFACING A/D AND D/A CONVERTER WITH 8085

To write an assembly language program to convert an analog signal into a digital signal
and a digital signal into an analog signal using an ADC interfacing and DAC interfacing
respectively.
A. ADC INTERFACING WITH 8085
APPARATUS REQUIRED:
SL.NO
1
2

ITEM
Microprocessor kit
Power supply

SPECIFICATION
8085,Vi Microsystems
+5 V dc

QUANTITY
1
1

ADC Interface board

Vi Microsystems

PROBLEM STATEMENT:
To program starts from memory location 4100H. The program is executed for various
values of analog voltage which are set with the help of a potentiometer. The LED display is
verified with the digital value that is stored in the memory location 4150H.
THEORY:
An ADC usually has two additional control lines: the SOC input to tell the ADC when
to start the conversion and the EOC output to announce when the conversion is complete. The

following program initiates the conversion process, checks the EOC pin of ADC 0419 as to
whether the conversion is over and then inputs the data to the processor. It also instructs the
processor to store the converted digital data at RAM 4200H.
ALGORITHM:
1.
2.
3.
4.
5.
6.

Select the channel and latch the address.


Send the start conversion pulse.
Read EOC signal.
If EOC =1 continue else go to step (3)
Read the digital output.
Store it in a memory location.

50

PROGRAM:
ADDRESS LABEL
4100

MNEMON ICS
MVI A

OPCO
DE

OPERA
ND
10

COMMENTS
Select channel 0 and to
make accumulator low

4101
4102
4103
4104
4105
4106
4107
4108
4109
410A
410B

OUT

C8

Output the data

MVI A

18

Make accumulator high

OUT

C8

Display the data

MVI A

01

Make 01 to accumulator

OUT

D0

Display the data

410C
410D
410E
410F
4110
4111
4112
4113
4114
4115

LOOP

XRA
XRA
XRA
MVI A

00

XOR with accumulator


XOR with accumulator
XOR with accumulator
Make 00 to accumulator

OUT

D0

Load D0 in output port

IN

D8

ANI

01

Do and operation directly

4116
4117
4118
4119
411A
411B
411C
411D
411E
411F
4120

CPI

01

Compare with accumulator

JNZ

LOOP

Jump to specified address

IN

C0

STA

4150

Store the data

4121

HLT

End the program

51

ADC- CIRCUIT:

SOC JUMPER SELECTION:

J2 : SOC Jumper selection


J5 : Channel selection
52

OBSERVATION
ANALOG VOLTAGE

DIGITAL DATA
LED DISPLAY

ON

HEX
CODE
LOCATION 4150

IN

53

DAC INTERFACING WITH 8085


APPARATUS REQUIRED:
SL.NO

ITEM

SPECIFICATION

QUANTITY

1
2
3

Microprocessor kit
Power supply
DAC Interface board

8085,Vi Microsystems
+5 V dc
Vi Microsystems

1
1
1

SOFTWARE EXAMPLES
The following examples illustrate how to control the DAC using 8085 and generate
sine wave, saw tooth wave by means of software.
(a) SQUARE WAVE GENERATION:

The basic idea behind the generation of waveforms is the continuous generation of
Analog output of DAC. With 00(HEX) as input to DAC2, the analog output is -5V.
Similarly, with FF (Hex) as input, the output is +5V. Outputting digital data 00 and FF at
regular intervals, to DAC2, results in a square wave of amplitude I5 Volts
ALGORITHM:
1. Load the initial value (00) to Accumulator and move it to DAC.
2. Call the delay program
3. Load the final value (FF) to accumulator and move it to DAC.

4. Call the delay program.


5. Repeat steps 2 to 5.
PROGRAM:
ADDRESS LABEL

MNEMON ICS

4100
4101
4102
4103

START

OPC
ODE

OPERAND

COMMENT

MVI A

00

Move 00 to A register

OUT

C8

Load C8 to output port

4104
4107
4109
410B
410E
4112
4114

DELAY
L1

CALL DELAY
MVI A
OUT
CALL DELAY
JMP START
MVI B
MVI C

DELAY
FF
C8
DELAY
START
05
FF

Call delay program


Load FF to B register
Jump to start of address
Move 05 to B register
Move FF to C register
54

4116
4117
411A
411B
411E

L2

DCR C
JNZ L2
DCR B
JNZ L1
RET

L2
L1

Decrement C
Jump to L2 if no zero
Decrement B register
Jump to L1 if no zero

Execute the program and using a CRO, verify that the waveform at the DAC2 output is a
square-wave. Modify the frequency of the square-wave, by varying the time delay.
(b) SAW TOOTH GENERATION:
ALGORITHM:
1. Load the initial value (00) to Accumulator
2. Move the accumulator content to DAC.
3. Increment the accumulator content by 1.
4. Repeat steps 3 and 4.

Output digital data from 00 to FF constant steps of 01 to DAC1 repeat this sequence again and
again. As a result a saw - tooth wave will be generated at DAC1 output.
PROGRAM:
ADDRESS LABEL

MNEMON ICS

4100
4102
4104
4105

MVI A
OUT
INR A
JNZ L1

START
L1

OPCO OPERAN
DE
D
00
C0
L1

COMMENT
Load 00 to accumulator
Load CO in output port
Increment A register
Jump to L1 if no zero

4108

JMP START

START

Go
to
START
unconditionally

(c) TRIANGULAR WAVE GENERATION:


ALGORITHM:
1. Load the initial value (00) to Accumulator.
2. Move the accumulator content to DAC
3. Increment the accumulator content by 1.
4. If accumulator content is zero proceed to next step. Else go to step 3.

5. Load value (FF) to accumulator.


6. Move the accumulator content to DAC.
7. Decrement the accumulator content by 1.
8. If accumulator content is zero go to step 2. Else go to step 2.
The following program will generate a triangular wave at DAC2 output.
55

PROGRAM:
ADDRESS LABEL
START
L1

MNEMON ICS
MVI L
MOV A,L

OPC
ODE

OPERA
ND
00

COMMENT
Move 00 to L register
Load L to a register

L2

OUT
INR L
JNZ L1
MVI L
MOV A,L
OUT
DCR L
JNZ L2
JMP START

C8
L1
FF
C8
L2
START

Load c8 to output port


Increment L register
Jump to L1 if no zero
Load FF to L register
Move L to a register
Load C8 to output port
Decrement L register
Jump to L2 if no zero
Go to START unconditionally

56

DAC - CIRCUIT:

WAEFORMS:

57

OBSERVATION:
WAVE FORMS
Square waveform
Saw tooth waveform
Triangular waveform

AMPLITUDE

TIME PERIOD

Result:
Thus the conversion of an analog signal into a digital signal and a digital signal into an
analog signal was done using interfacing of ADC and DAC respectively with 8085.

58

EX.No:5

TRAFFIC LIGHT CONTROLLER WITH 8085

AIM
To write an assembly language program to simulate the traffic light at an intersection
using a traffic light interface.

APPARATUS REQUIRED:
SL.NO
1
2
3

ITEM
Microprocessor kit
Power supply
Traffic light interface kit

SPECIFICATION
4185,Vi Microsystems
+5 V dc
Vi Microsystems

QUANTITY
1
1
1

ALGORITHM:
1. Initialize the ports.
2. Initialize the memory content, with some address to the data.
3. Read data for each sequence from the memory and display it through the ports.

4. After completing all the sequences, repeat from step2.


A SAMPLE SEQUENCE:
1. (a) Vehicles from south can go to straight or left.
(b) Vehicles from west can cross the road.
(c) Each pedestrian can cross the road.
(d) Vehicles from east no movement.
(e) Vehicles from north, can go only straight.
2. All ambers are ON, indicating the change of sequence.

3. (a) Vehicles from east can go straight and left.


(b) Vehicles from south, can go only left.
(c) North pedestrian can cross the road.
(d) Vehicles from north, no movement.
(e) Vehicles from west, can go only straight.
4. All ambers are ON, indicating the change of sequence.
5. (a) Vehicles from north can go straight and left.
(b) Vehicles from east, can go only left.
(c) West pedestrian can cross the road.

(d) Vehicles from west, no movement.


(e) Vehicles from south, can go only straight.
6. All ambers are ON, indicating the change of sequence.

59

7. (a) Vehicles from west can go straight and left.


(b) Vehicles from north, can go only left.
(c) South pedestrian can cross the road.
(d) Vehicles from south, no movement.
(e) Vehicles from east, can go only straight.

8. All ambers are ON, indicating the change of sequence.


9. (a) All vehicles from all directions no movement.
(b) All pedestrian can cross the road.
BIT ALLOCATION:
BIT

LED

BIT

LED

BIT

LED

PA0
PA1

SOUTH LEFT
SOUTH RIGHT

PB0
PB1

NORTH LEFT
NORTH RIGHT

PC0
PC1

WEST STRAIGHT
NORTH STRAIGHT

PA2
PA3
PA4
PA5
PA6
PA7

SOUTH AMBER
SOUTH RED
EAST LEFT
EAST RIGHT
EAST AMBER
EAST RED

PB2
PB3
PB4
PB5
PB6
PB7

NORTH AMBER
NORTH RED
WEST LEFT
WEST RIGHT
WEST AMBER
WEST RED

PC2
PC3
PC4
PC5
PC6
PC7

EAST STRAIGHT
SOUTH STRAIGHT
NORTH PD
WEST PD
SOUTH PD
EAST PD

60

PATH REPRESENTATION:

CONTROL ----- 0F ( FOR 8255 PPI )


PORT A
----- 0C
PORT B
----- 0D
PORT C
----- 0E

61

PROGRAM :

ADDRESS LABEL

MNEMON ICS

COMMENT

MVI A, 41

OPCO OPER
DE
AND
3E
41

4100
4102

OUT CONTROL

D3

4104

LXI H,DATA_SQ

Output
contents
of
accumulator to OF port
Load address 417B to HL
register

0F

Move 80 immediately to
accumulator

4107

LXI D,DATA_E

11

41,87

410A
410D

CALL OUT
XCHG

CD
EB

42,41

410E

MOV A,M

7E

410F
4111
4114

OUT PORT A
CALL DELAY1
XCHG

D3
CD
EB

0C
66,41

Load address 4187 to DE


register
Call out address
Exchange contents of HL
with DE pair
Move M content to
accumulator
Load port A into output port
Call delay address
Exchange content of HL
with DE pair

4115
4116
4117
411A

INX D
INX H
CALL OUT
XCHG

13
23
CD
EB

411B

MOV A,M

7E

411C
411E

OUT PORT B
CALL DELAY1

D3
CD

42,41

0D
66,41

Increment the content of D


Increment the content of H
Call out the address
Exchange content of HL
with DE pair
Move M content to
accumulator
Load port B into output port
Call DELAY address

4121

XCHG

EB

4122
4123
4124
4127

INX D
INX H
CALL OUT
XCHG

13
23
CD
EB

4128

MOV A,M

7E

42,41

Exchange content of HL
with DE pair
Increment D register
Increment H register
Call specified address
Exchange content of HL
with DE pair
Move M content to
accumulator
62

4129
412B
412E

OUT PORT C
CALL DELAY1
XCHG

D3
CD
EB

412F
4130

INX D
INX H

13
23

0E
66,41

Load port C into output port


Call DELAY address
Exchange content of HL
with DE pair
Increment D register
Increment H register

4131
4134

CALL OUT
XCHG

CD
EB

42,41

4135

MOV A,M

7E

4136
4138
4139

OUT PORT C
INX H
MOV A,M

D3
23
7E

0E

413A
413C

OUT PORT A
CALL DELAY1

D3
CD

0C
66,41

Call specified address


Exchange content of HL
with DE pair
Move M content to
accumulator
Load port C into output port
Increment H register
Move M content to
accumulator
Load port A into output port
Call DELAY address

413F
4142

JMP REPEAT
MOV A,M

C3
7E

04,41

4143
4145
4146

OUT PORT C
INX H
MOV A,M

D3
23
7E

0E

4147
4149
414A

OUT PORT B
INX H
MOV A,M

D3
23
7E

0D

Jump to specified address


Move M content to
accumulator
Load port C into output port
Increment H register
Move M content to
accumulator
Load port B into output port
Increment H register
Move M content to
accumulator

414B
414D
4150
4151
4152

OUT PORT A
CALL DELAY
RET
PUSH H
LXI H,001F

D3
CD
C9
E5
21

0C
51,41

4155

LXI B,FFFF

01

FF,FF

4158
4159

DCX B
MOV A,B

0B
78

1F,00

Load port A into output port


Call DELAY address
Return to accumulator
Push the register H
Load 00 1F in HL register
pair
Load FF FF in DE register
pair
Decrement B register
Move B content to
accumulator

415A

ORA C

B1

415B
415E
415F

JNZ LOOP
DCX H
MOV A,L

C2
2B
7D

58,41

OR content of C with
accumulator
Jump to LOOP if no zero
Decrement H register
Move L content to
accumulator
63

4160

ORA H

B4

4161
4164
4165

JNZ L1
POP H
RET

C2
E1
C9

55,41

OR content of H with
accumulator
Jump to L1 if no zero
Pop the register H
Return from subroutine

4166
4167

PUSH H
LXI H,001F

E5
21

1F,00

416A

LXI B,FFFF

01

FF,FF

416D
416E

DCX B
MOV A,B

0B
78

416F

ORA C

B1

4170

JNZ LOOP2

C2

6D,41

Push the register H


Load 00 1F in HL register
pair
Load FF FF in DE register
pair
Decrement B register
Move B content to
accumulator
OR content of C with
accumulator
Jump to LOOP2 if no zero

4173
4174

DCX H
MOV A,L

2B
7D

4175

ORA H

B4

4176
4179
417A

JNZ L2
POP H
RET

C2
E1
C9

6A,41

Decrement H register
Move L content to
accumulator
OR content of H with
accumulator
Jump to L2 if no zero
Pop the register H
Return to subroutine

417B

DATA
12 27 44 10 2B
SEQ DB 92 10 9D 84 48
2E 84
48 4B 20 49 04

RESULT:
Thus an assembly language program to simulate the traffic light at an intersection using a
traffic light interfaces was written and implemented.

64

EX.No:6

INTERFACING 8251 WITH 8085

AIM:
To write a program to initiate 8251 and to check the transmission and reception
of character.

APPARATUS REQUIRED:
1. 8085 Microprocessor kit
2. 8251 Interface board
3. DC regulated power supply
THEORY:
The 8251 is used as a peripheral device for serial communication and is
programmed by the CPU to operate using virtually any serial data transmission technique.
The USART accepts data characters from the CPU in parallel format and the converts them
in a continuous serial data stream of transmission. Simultaneously, it can receive serial data

streams and convert them into parallel data characters for the CPU. The CPU can read the
status of USART at any time. These include data transmissions errors and control signals.
Prior to starting data transmission or reception ,the 8251 must be loaded with a
set of control words generated by the CPU.These control signals define the complete
functional definition of the 8251 and must immediately follow a RESET operation. Control
words should be written in to the control register of 8251. words should be written in to the
control register of 8251.words should be written in to the control register of
8251.Thesecontrol words are split into two formats.
1. MODE INSTRUCTION WORD
2. COMMAND INSTRUCTION WORD.

1. MODE INSTRUCTION WORD


This format defines the BAUD rate, character length, parity and stop bits required to
work with asynchronous data communication. by selecting the appropriate BAUD
factor synchronous mode, the 8251 can be operated in synchronous mode.
Initializing 8251 using the Mode instructions to the following conditions.
8 bit data
No parity

Baud rate factor(16X)


1 stop bit
Gives a mode command word of 01001110=4E(X)

65

ALGORITHM
1. Initialize timer (8253) IC
2. Move the Mode command word (4EH) to A reg.
3. Output it port address C2
4. Move the command instruction word (37H) to A reg.
5. Output it to port address C2

6. Move the data to be transfer to A reg.


7. Output it to port address C0.
8. Reset the system
9. Get the data through input port address C0.
10. Store the value in memory
11. Reset the system
PROGRAM:

ADDRES
S

LA
BE
L

MNEMON
ICS

OPC OPE
ODE RAN
D
36
CE

4100
4102

MVI A
OUT

4104
4106

MVI A
OUT

0A
C8

4108

MVI A

00

COMMENT
Move 36 to A
Output contents of accumulator to CE
port
Move 0A to accumulator
Output contents of accumulator to C8
port
Move 00 to accumulator

410A

OUT

C8

410C
410F
4111

LXI H
MVI A
OUT

4200
4E
C2

4113
4115

MVI A
OUT

37
C2

4117

MVI A

41

Output contents of accumulator to C8


port
Store 4200 address in HL register pair
Move 4E to accumulator
Output contents of accumulator to C2
port
Move 37 to accumulator
Output contents of accumulator to C2
port
Move 41 to accumulator

4119

OUT

C0

Output contents of accumulator to C0


port

411B
4200

RST1
IN

C0

4202

STA

4150

Input the contents from port C0 to


accumulator
Store the output from accumulator to
4150

4205

RST1

66

SYNCHRONOUS MODE:

S2

S1

EP

PEN

5
BIT

6
BIT

7
BIT

8
BIT

L2

L1

B2

B1

PARITY ENABLE
1-Enable

0-Disable
EVEN PARITY GENERATION
0-Odd
1-Even
EXTERNAL SYNC DETECT
1-Sysdetect is an input
0- Sysdetect is an output

SINGLE CHARACTER SYNC


1-Single sync character
0- Double sync character

67

ASYNCHRONOUS MODE:
S2

S1

EP

PEN

L2

L1

B2

B1

Synch
mode

(1 X)

(16 X) (64 X)

5
BIT

6
BIT

7
BIT

8
BIT

PARITY ENABLE
1-Enable
0-Disable

EVEN PARITY GENERATION


0-Odd
1-Even

Invalid

61BIT

1.5BIT

2 BIT

68

OBSERVATION:

MEMORY LOCATION

INPUT DATA

OUTPUT DATA

RESULT:
Thus the program to initiate 8251 was written and the transmission and reception of
character was checked by interfacing 8251 with 8085.

69

EXPT.NO.7
AIM:

7. INTERFACING 8253 TIMER WITH 8085

To interface 8253 Interface board to 8085 microprocessor to demonstrate the generation of


square wave.
APPARATUS REQUIRED:
1. 8085 microprocessor kit
2. 8253 Interface board
3. DC regulated power supply
4. CRO.

PROGRAM:
Addres
4100
4102
4104
4106
4108
410A

Opcodes Label
3E 36
START:
D3 CE
3E 0A
D3 C8
3E 00
D3 C8

Mnemoni
MVI
OUT
MVI
OUT
MVI
OUT

Operands
A, 36
CE
A, 0A
C8
A, 00
C8

Comments
Channel 0 in mode 3
Send Mode Control word
LSB of count
Write count to register
MSB of count
Write count to register

410C

76

HLT

Set the jumper, so that the clock 0 of 8253 is given a square wave of frequency 1.5
MHz. This program divides this PCLK by 10 and thus the output at channel 0 is 150 KHz.
Vary the frequency by varying the count. Here the maximum count is FFFF H. So, the
square wave will remain high for 7FFF H counts and remain low for 7FFF H counts. Thus
with the input clock frequency of 1.5 MHz, which corresponds to a period of 0.067
microseconds, the resulting square wave has an ON time of 0.02184 microseconds and an OFF
time of 0.02184 microseconds.

To increase the time period of square wave, set the jumpers such that CLK2 of 8253 is
connected to OUT 0. Using the above-mentioned program, output a square wave of frequency
150 KHz at channel 0. Now this is the clock to channel 2.

70

CONTROL WORD:
SC1

SC2

RW1 RW0

M2

M1

M0

BCD

SC-SELECT COUNTER:
SC1

SC0

SELECT COUNTER

Select counter 0

Select counter 1

Select counter 2

Read back command

M-MODE:
M2
0
0
X
X
1
1
READ/WRITE:

M1
0
0
1
1
0
0

M0
0
1
0
1
0
1

MODE
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5

RW1

RW0

Counter latch command

R/W least significant bit only

R/W most significant bit only

R/W least sig first and most sig byte

BCD:
0

Binary counter 16-bit

Binary coded decimal counter

71

Result:
Thus the 8253 has been interfaced to 4185 p and six different modes of 8253 have
been studied.

72

EXPT. NO 8
AIM:

INTERFACING 8279 WITH 8085

To interface 8279 Programmable Keyboard Display Controller to 8085 Microprocessor.


APPARATUS REQUIRED:
1. 8085 Microprocessor toolkit.
2. 8279 Interface board
3. Regulated D.C. power supply.
PROGRAM:

ADDRESS LABEL

MNEMON ICS

4100

OPERA
ND

COMMENT

LXI H

4130

4103

MVI D

0F

Store the 16 bit address


in HL pair
Move 0F to D register

4105

MVI A

10

Move 10 to A

4107

OUT

C2

Output the contents of


A to C2 output port

START

OPCO
DE

4109

MVI A

CC

Move CC to A

410B

OUT

C2

410D

MVI A

90

Output the contents of


A to C2 output port
Move 90 to A

410F

OUT

C2

4111
4112

LOOP

MOV A, M
OUT

C0

Output the contents of


A to C2 output port
Move content of M to
A
Output the contents of
M to A

4114

CALL DELAY

DELAY

Call the delay address

4117

INX H

Increment H register

4118

DCR D

Decrement D register

73

4119

JNZ LOOP

LOOP

411C

JMP START

START

MVI B

A0

411F

DELAY

Jump to specified
address
Jump to START
address
Move a to B register

4121

LOOP1

MVI C

4123

LOOP2

DCR C

4124

JNZ LOOP 1

4127

DCR B

4128

JNZ LOOP 2

FF

Move FF to C register
Decrement C register

LOOP 1

Jump to LOOP 1 if no
zero
Decrement B register

LOOP 2

Jump to LOOP 2 if no
zero

412B

RET

Pointer equal to 4130 .FF repeated eight times


4130
4131
4132
4133
4134
4135

FF
FF
FF
FF
FF
FF

4136
4137
4138
4139
413
413B
413C
413D
413E
413F

FF
FF
98
68
7C
C8
1C
29
FF
FF

74

SEGMENT DEFINITION:

DATA BUS

D7 D6 D5 D4 D3 D2 D1 D0

SEGMETS

dp g

OBSERVATION:
LETTER

7
SEGMENT

DATA BUS
D7 D6 D5 D4 D3 D2 D1 D0

HEXADECIMAL

RESULT:
Thus 8279 controller was interfaced with 8085 and program for rolling display was executed
successfully.

75

MICROCONTROLLER

76

Ex.No:9
AIM:

9. 8051 - SUM OF ELEMENTS IN AN ARRAY

To find the sum of elements in an array.


ALGORITHM:
1.

Load the array in the consecutive memory location and initialize the
memory pointer with the starting address.

2.

Load the total number of elements in a separate register as a counter.

3.

Clear the accumulator.

4.

Load the other register with the value of the memory pointer.

5.

Add the register with the accumulator.

6.

Check for carry, if exist, increment the carry register by 1. otherwise,


continue

7.

Decrement the counter and if it reaches 0, stop. Otherwise increment the


memory pointer by 1 and go to step 4.

77

PROGRAM:
ADDRESS OPCODE LABEL

MNEMONICS

OPERAND

COMMENT

4100

MOV

DPTR, #4200

4103

MOVX

A, @DPTR

4104

MOV

R0, A

4105

MOV

B, #00

4108

MOV

R1, B

CLR C

C3

INC DPTR

A3

410A
410B

ADD

410C

MOVX

A, @DPTR

410D

ADD

A, B

410F

MOV

B, A

4111

JNC

NC

4113

INC

R1

INC

DPTR

MOV

DPTR, #4500

4114
4116

NC

4119

MOV

A, R1

411A

MOVX

@DPTR, A

411B

INC

DPTR

411C

MOV

A, B

411E

MOVX

@DPTR, A

411F

SJMP

HLT

78

OBSERVATION:

INPUT
4200

OUTPUT
4500

4201
4202
4203

4501

RESULT:
The sum of elements in an array is calculated.

79

EXPT.NO.10.

10. 8051 - SUM USING STACK

AIM:
To find the sum of elements in an array using stack.
ALGORITHM:
1. Start
2. Move the data to stack pointer
3. Move the data to accumulator
4. Move the data to reg B

5. Move the data to DPL


6. Push the value of A to stack
7. Push the value of B to stack
8. Push the value of DPL to stack
9. Halt

80

PROGRAM:
ADDRESS OPCODE LABEL

MNEMONICS

OPERAND

COMMENT

4100

MOV SP, #67

67

4103

MOV A, #88

88

4105

MOV B, #66

66

4108

MOV DPL, #43

43

410B

PUSH A

410D

PUSH B

410F

PUSH DPL

4111

SJMP

RESULT:
The sum of elements in an array is calculated.
81

EXPT.NO.11
AIM:

11. 8051 - SUM USING CALL OPTION

To find the sum of elements in an array using call option.


ALGORITHM:
1. Start
2. Move the data to DPTR
3. Move the data to accumulator
4. Adjacent call 4200
5. Add A & R0

6. Move the 16 bit data from A to DPTR


7. Move the data to accumulator
8. Move the data to R 0
9. Return to 4107

82

PROGRAM:

ADDRESS OPC
ODE
4100

LABEL

MNEMONICS

OPERAND

MOV DPTR,# 4300

43,00

4103

MOV A, # 00

00

4105

ACALL 4200

42,00

4108

ADD A, R0

410B

MOVX @DPTR,A

410D

SJMP

80

COMMENT

410F

MOVA,#02

02

4111

MOV R0, #01

01

RET

OBSERVATION:
INPUT

OUTPUT

4200

4300

4202

RESULT:
The sum of elements in an array using call option is calculated is calculated.

83

Ex.No:12

12 STEPPER MOTOR INTERFACING WITH 8051

AIM:
To interface a stepper motor with 8051 microcontroller and operate it.

THEORY:
A motor in which the rotor is able to assume only discrete stationary angular position is a
stepper motor. The rotary motion occurs in a step-wise manner from one equilibrium position to
the next. Stepper Motors are used very wisely in position control systems like printers, disk
drives, process control machine tools, etc.
The basic two-phase stepper motor consists of two pairs of stator poles. Each of the
four poles has its own winding. The excitation of any one winding generates a North Pole. A
South Pole gets induced at the diametrically opposite side. The rotor magnetic system has two
end faces. It is a permanent magnet with one face as South Pole and the other as North Pole.

The Stepper Motor windings A1, A2, B1, B2 are cyclically excited with a DC current
to run the motor in clockwise direction. By reversing the phase sequence as A1, B2, A2, B1,
anticlockwise stepping can be obtained.
2-PHASE SWITCHING SCHEME:
In this scheme, any two adjacent stator windings are energized. The switching scheme
is shown in the table given below. This scheme produces more torque.
ANTICLOCKWISE
STEP A1
A2

B1

B2

DATA

CLOCKWISE
STEP A1 A2

B1

B2

DATA

1
2
3
4

1
0
0
1

0
1
1
0

0
0
1
1

1
1
0
0

9h
5h
6h
Ah

1
2
3
4

1
0
0
1

0
1
1
0

1
1
0
0

0
0
1
1

Ah
6h
5h
9h

ADDRESS DECODING LOGIC:


The 74138 chip is used for generating the address decoding logic to generate the device
select pulses, CS1 & CS2 for selecting the IC 74175.The 74175 latches the data bus to the
stepper motor driving circuitry.
Stepper Motor requires logic signals of relatively high power. Therefore, the interface
circuitry that generates the driving pulses use silicon darlington pair transistors. The inputs for

the interface circuit are TTL pulses generated under software control using the Microcontroller
Kit. The TTL levels of pulse sequence from the data bus is translated to high voltage output
pulses using a buffer 7407 with open collector.

84

BLOCK DIAGRAM:

8051
MICROCONTROLLER

REPRESENTATION:

8255

DRIVER CIRCUIT
STEPPER MOTOR

85

PROGRAM :
Addres OPCODES
s

Label

MNEM
ONICS
ORG

OPERAND
4100h

Comments

4100

START

MOV

DPTR, #TABLE

4103
4105

LOOP:

MOV
MOVX

R0, #04
A, @DPTR

PUSH
PUSH
MOV

DPH
DPL
DPTR, #0FFC0h

4106
4108
410A

Load the start address


of switching scheme
data TABLE into Data
Pointer (DPTR)
Load the count in R0
Load the number in
TABLE into A
Push DPTR value to
Stack
Load the Motor port
address into DPTR

410D

MOVX

@DPTR, A

410E
4110

MOV
MOV

R4, #0FFh
R5, #0FFh

DJNZ

R5, DELAY1

DJNZ
POP
POP

R4, DELAY
DPL
DPH

4112
4114
4116
4118

DELA
Y:
DELA
Y1:

Send the value in A to


stepper Motor port
address
Delay loop to cause a
specific amount of
time delay before next
data item is sent to the
Motor
POP back DPTR value
from Stack

411A

INC

DPTR

411B

DJNZ

R0, LOOP

411D

SJMP

START

Increment DPTR to
point to next item in
the table
Decrement R0, if not
zero repeat the loop
Short jump to Start of
the program to make
the motor rotate
continuously

411F

TABLE DB
:

09 05 06 0Ah

Values as per twophase switching


scheme

86

PROCEDURE:
1. Enter the above program starting from location 4100.and execute the same.
2. The stepper motor rotates.
3. Varying the count at R4 and R5 can vary the speed.

4. Entering the data in the look-up TABLE in the reverse order can vary direction of
rotation.

RESULT:
Thus a stepper motor was interfaced with 8051 and run in forward and reverse
directions at various speeds.

87

EX.NO 13.
AIM:

INTERFACING D/A CONVERTER WITH 8051

To interface DAC with 8051 to demonstrate the generation of square, saw tooth and
triangular wave.
APPARATUS REQUIRED:
SL.NO
1
2
3
THEORY:

ITEM
Microprocessor kit
Power supply
DAC Interface board

SPECIFICATION
4185,Vi Microsystems
+5 V dc
Vi Microsystems

QUANTITY
1
1
1

SOFTWARE EXAMPLES
After going through the software examples you can learn how to control the
DAC using 8051 and generate sine wave, saw tooth wave etc by means of software.
ALGORITHM:
(a) SQUARE WAVE GENERATION:
1. Load the initial value (00) to Accumulator and move it to DAC.
2. Call the delay program

3. Load the final value (FF) to accumulator and move it to DAC.


4. Call the delay program.
5. Repeat steps 2 to 5.

88

DAC - CIRCUIT:

WAVEFORMS:

89

OBSERVATION:

WAVE FORMS
Square waveform
Saw tooth waveform
Triangular waveform

AMPLITUDE

TIME PERIOD

PROGRAM:
The basic idea behind the generation of waveforms is the continuous generation of
Analog output of DAC.
With 00(HEX) as input to DAC2, the analog output is -5V. Similarly, with FF (Hex) as
input, the output is +5V. Outputting digital data 00 and FF at regular intervals, to DAC2,
results in a square wave of amplitude I5 Volts.

ADDRESS LABEL
START

DELAY

MNEMON ICS
MOV DPTR,#FFC8
MOV A,#00
MOVX @DPTR,A
LCALL DELAY
MOV A,# FF
MOVX @DPTR,A
LCALL DELAY
LJMP START
MOV R1,#05

OPCODE

OPERAND

COMMENT

LOO[P

MOV R2,#FF
DJNZ R2,HERE
DJNZ R1,LOOP
RET
SJMP START
Execute the program and using a CRO, verify that the waveform at the DAC2 output is a
square-wave. Modify the frequency of the square-wave, by varying the time delay.
(b) SAW TOOTH GENERATION
1. Load the initial value (00) to Accumulator
2. Move the accumulator content to DAC.

3. Increment the accumulator content by 1.


4. Repeat steps 3 and 4.
Output digital data from 00 to FF constant steps of 01 to DAC1 repeat this sequence again and
again. As a result a saw - tooth wave will be generated at DAC1 output.

90

PROGRAM:
ADDRESS LABEL

MNEMON ICS
MOV DPTR,#FFC0

OPCODE OPERAND

COMMENT

LOOP

MOV A,#00
MOVX @DPTR,A
INC A
SJMP LOOP

(c) TRIANGULAR WAVE GENERATION


1. Load the initial value (00) to Accumulator.
2. Move the accumulator content to DAC
3. Increment the accumulator content by 1.
4. If accumulator content is zero proceed to next step. Else go to step 3.
5. Load value (FF) to accumulator.

6. Move the accumulator content to DAC.


7. Decrement the accumulator content by 1.
8. If accumulator content is zero go to step 2. Else go to step 2.
The following program will generate a triangular wave at DAC2 output. The program is
self explanatory.
ADDRESS LABEL
START
LOOP1

MNEMON ICS
MOV DPTR,#FFC8
MOV A,#00
MOVX @DPTR,A

OPCODE OPERAND

COMMENT

LOOP2

INC A
JNZ LOOP1
MOV A,#FF
MOVX @DPTR,A
DEC A
JNZ LOOP2
LJMP START

OBSERVATION:
WAVE FORMS

AMPLITUDE

TIME PERIOD

91

Result:
Thus the square, triangular and saw tooth wave form were generated by interfacing
DAC with 8051 trainer kit.

92

Ex. No: 14
AIM:

STUDY OF BASIC DIGITAL ICS

To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-OR
gates.
APPARATUS REQUIRED:
S.No

Name of the Apparatus

Range

Quantity

1.

Digital IC trainer kit

2.

AND gate

IC 7408

3.

OR gate

IC 7432

4.

NOT gate

IC 7404

5.

NAND gate

IC 7400

6.

NOR gate

IC 7402

1
1

7.

EX-OR gate

IC 7486

8.

Connecting wires

As required

THEORY:

a. AND gate:
An AND gate is the physical realization of logical multiplication operation. It is
an electronic circuit which generates an output signal of 1 only if all the input signals
are 1.
b. OR gate:
An OR gate is the physical realization of the logical addition operation. It is an
electronic circuit which generates an output signal of 1 if any of the input signal is 1.

c. NOT gate:
A NOT gate is the physical realization of the complementation operation. It is
an electronic circuit which generates an output signal which is the reverse of the input
signal. A NOT gate is also known as an inverter because it inverts the input.

93

d. NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate
will be 0 if all the input signals are 1 and will be 1 if any one of the input signal is
0.

e. NOR gate:
A NOR gate is a complemented OR gate. The output of the OR gate will be 1 if
all the inputs are 0 and will be 0 if any one of the input signal is 1.
f. EX-OR gate:
An Ex-OR gate performs the following Boolean function,
A B = ( A . B ) + ( A . B )

It is similar to OR gate but excludes the combination of both A and B being


equal to one. The exclusive OR is a function that give an output signal 0 when the
two input signals are equal either 0 or 1.
PROCEDURE:
1. Connections are given as per the circuit diagram
1. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
2. Apply the inputs and verify the truth table for all gates.

AND GATE
LOGIC DIAGRAM:

94

PIN DIAGRAM OF IC 7408:

CIRCUIT DIAGRAM:

TRUTH TABLE:
S.No

INPUT
A

OUTPUT
Y= A. B

1.
2.
3.
4.

0
0
1
1

0
1
0
1
OR GATE

LOGIC DIAGRAM:

0
0
0
1

95

PIN DIAGRAM OF IC 7432 :

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No
1.
2.
3.
4.

INPUT
A
0
0
1
1

B
0
1
0
1
NOT GATE

OUTPUT
Y= A+ B
0
1
1
1

LOGIC DIAGRAM:

96

PIN DIAGRAM OF IC 7404 :

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No
1.
2.

INPUT
A
0
1

OUTPUT
Y = A
1
0

NAND GATE

LOGIC DIAGRAM:

97

PIN DIAGRAM OF IC 7400 :

CIRCUIT DIARAM:

TRUTH TABLE:

S.No
1.
2.
3.
4.

INPUT
A
0
0
1
1

B
0
1
0
1

OUTPUT
Y = (A. B)
1
1
1
0

98

NOR GATE
LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7402 :

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No
1.
2.
3.
4.

INPUT
A
0
0
1
1

B
0
1
0
1

OUTPUT
Y = (A + B)
1
0
0
0
99

EX-OR GATE
LOGIC DIAGRAM

PIN DIAGRAM OF IC 7486:

CIRCUIT DIAGRAM:

TRUTH TABLE:
S.No
1.

INPUT
A
0

B
0

OUTPUT
Y=A B
0

2.
3.
4.

0
1
1

1
0
1

1
1
0

100

RESULT:
The truth tables of all the basic digital ICs were verified.

101

EX.NO.15
AIM:

DESIGN AND IMPLEMENTATION OF ADDER/SUBTRACTOR

To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.
APPARATUS REQUIRED:
S. No

Name

1.

IC

2.

Digital IC Trainer Kit

Specification
7432, 7408, 7486, 7483

Quantity
1
1

3.

Patch chords

THEORY:
The most basic arithmetic operation is the addition of two binary digits. There are four
possible elementary operations, namely,
0+0=0
0+1=1
1+0=1

1 + 1 = 102
The first three operations produce a sum of whose length is one digit, but when the last
operation is performed the sum is two digits. The higher significant bit of this result is called a
carry and lower significant bit is called the sum.
HALF ADDER:
A combinational circuit which performs the addition of two bits is called half adder.
The input variables designate the augend and the addend bit, whereas the output variables
produce the sum and carry bits.

FULL ADDER:
A combinational circuit which performs the arithmetic sum of three input bits is called
full adder. The three input bits include two significant bits and a previous carry bit. A full
adder circuit can be implemented with two half adders and one OR gate.

102

HALF ADDER
TRUTH TABLE:
S.No

INPUT
A

OUTPUT
B

1.
2.
3.
4.

0
0
1
1

0
1
0
1

0
1
1
0

0
0
0
1

DESIGN:
From the truth table the expression for sum and carry bits of the output can be
obtained as, Sum, S = A
B ; Carry, C = A . B

CIRCUIT DIAGRAM:

FULL ADDER
TRUTH TABLE:
S.No
1.
2.
3.

A
0
0
0

INPUT
B
0
0
1

C
0
1
0

OUTPUT
SUM
CARRY
0
0
1
0
1
0

4.
5.
6.
7.
8.

0
1
1
1
1

1
0
0
1
1

1
0
1
0
1

0
1
0
0
1

1
0
1
1
1

103

DESIGN:
From the truth table the expression for sum and carry bits of the output can be obtained
as,SUM = ABC + ABC + ABC + ABC;CARRY = ABC + ABC + ABC +ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as,

SUM

SUM = ABC + ABC + ABC + ABC = A B


CARRY

CARRY = AB + AC + BC
CIRCUIT DIAGRAM:

104

HALF SUBTRACTOR:
A combinational circuit which performs the subtraction of two bits is called half
subtractor. The input variables designate the minuend and the subtrahend bit, whereas the
output variables produce the difference and borrow bits.

FULL SUBTRACTOR:
A combinational circuit which performs the subtraction of three input bits is called full
subtractor. The three input bits include two significant bits and a previous borrow bit. A full
subtractor circuit can be implemented with two half subtractors and one OR gate.
HALF SUBTRACTOR
TRUTH TABLE:

S.No
1.
2.
3.
4.

INPUT
A
0
0
1
1

B
0
1
0
1

OUTPUT
DIFF
BORR
0
0
1
1
1
0
0
0

DESIGN:
From the truth table the expression for difference and borrow bits of the output can be
obtained as, Difference, DIFF = A B; Borrow, BORR = A . B

CIRCUIT DIAGRAM:

105

FULL SUBTRACTOR
TRUTH TABLE:
S.No

INPUT
B

OUTPUT
DIFF
BORR

1.
2.
3.
4.
5.
6.
7.
8.
DESIGN:

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

0
1
1
1
0
0
0
1

From the truth table the expression for difference and borrow bits of the output can be
obtained as,
Difference, DIFF= ABC + ABC + ABC + ABC
Borrow, BORR = ABC + ABC + ABC +ABC
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
DIFFERENCE

DIFF = ABC + ABC + ABC + ABC = A B


BORROW

BORR = AB + AC + BC

106

CIRCUIT DIAGRAM:

PROCEDURE:
The connections are given as per the circuit diagram.

Two 4 - bit numbers added or subtracted depend upon the control input and the
output is obtained.
Apply the inputs and verify the truth table for thehalf adder or s subtractor and
full adder or subtractor circuits.

RESULT:
Thus the half adder, full adder, half subtractor and full subtractor circuits were designed
and their truth table were verified.

107

EX.NO.16

CODE CONVERTER

AIM:
To construct and verify the performance of binary to gray and gray to binary.

APPARATUS REQUIRED:

S. No

Name

1.

IC

2.

Digital IC Trainer Kit

Specification
7404, 7486

Quantity
1
1

3.

Patch chords

THEORY:
BINARY TO GRAY:
The MSB of the binary code alone remains unchanged in the Gray code. The remaining
bits in the gray are obtained by EX-OR ing the corresponding gray code bit and previous bit in

the binary code. The gray code is often used in digital systems because it has the advantage
that only one bit in the numerical representation changes between successive numbers.
GRAY TO BINARY:
The MSB of the Gray code remains unchanged in the binary code the remaining bits are
obtained by EX - OR ing the corresponding gray code bit and the previous output binary bit.

PROCEDURE:
Connections are given as per the logic diagram.
The given truth tables are verified.

108

BINARY TO GRAY:

GRAY TO BINARY

109

TRUTH TABLE
Decimal
0

Binary code
C B A
D
0
0
0
0

G3
0

Gray code
G2 G1
0
0

GO
0

1
2
3
4
5
6
7
8
9

0
0
0
0
0
0
0
1
1

0
0
0
1
1
1
1
0
0

0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1
1

0
0
0
1
1
1
1
1
1

0
1
1
1
1
0
0
0
0

1
1
0
0
1
1
0
0
1

10
11
12
13
14
15

1
1
1
1
1
1

0
0
1
1
1
1

1
1
0
0
1
1

0
1
0
1
0
1

1
1
1
1
1
1

1
1
0
0
0
0

1
1
1
1
0
0

1
0
0
1
1
0

RESULT:

The design of the three bit Binary to Gray code converter & Gray to Binary code
converter circuits was done and its truth table was verified.

110

EX.NO.17

ENCODER

AIM:
To design and implement encoder using IC 74148 (8-3 encoder)

APPARATUS REQUIRED:
S. No

Name

Specification

1.

IC

2.

Digital IC Trainer Kit

3.

Patch chords

THEORY:

74148

Quantity
1

An encoder is digital circuit that has 2n input lines and n output lines. The output lines
generate a binary code corresponding to the input values 8 - 3 encoder circuit has 8 inputs, one
for each of the octal digits and three outputs that generate the corresponding binary number.
Enable inputs E1 should be connected to ground and Eo should be connected to VCC

PROCEDURE:

Connections are given as per the logic diagram.


The truth table is verified by varying the inputs.

PIN DIAGRAM
2

N-1

2N
1
2N INPUT

ENCODER

N OUTPUT
N

111

TRUTH TABLE

E1
0
0
0
0
0
0
0
0
1

A0
0
1
1
1
1
1
1
1
1

A1
1
0
1
1
1
1
1
1
1

A2
1
1
0
1
1
1
1
1
1

INPUTS
A3
A4
1
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1

A5
1
1
1
1
1
0
1
1
1

A6
1
1
1
1
1
1
0
1
1

A7
1
1
1
1
1
1
1
0
1

OUTPUTS
D2
D1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1

D0
0
1
0
1
0
1
0
1
1

112

EX.NO.18

DECODER

AIM:
To design and implement decoder using IC 74155 (3-8 decoder).

APPARATUS REQUIRED:

S. No
1.
2.
3.
THEORY:

Name
IC
Digital IC Trainer Kit
Patch chords

Specification
74155

Quantity
1
1
-

A decoder is a combinational circuit that converts binary information from n input lines
to 2n unique output lines.
In 3-8 line decoder the three inputs are decoded into right outputs in which each output
representing one of the minterm of 3 input variables. IC 74155 can be connected as a dual 2*4
decoder or a single 3*8 decoder desired input in C 1 and C2 must be connected together and used
as the C input. G1 and G2 should be connected and used as the G (enable) input. G is the
enable input and must be equal to 0 for proper operation.

PROCEDURE:
Connections are given as per the logic diagram.
The truth table is verified by varying the inputs.
CIRCUIT DIAGRAM:

1
N INPUT

DECODER

2N
1
2

N OUTPUT
-1

2N

113

TRUTH TABLE

G
1
0
0
0
0
0

INPUTS
C
B
X
X
0
0
0
0
0
1
0
1
1
0

A
X
0
1
0
1
0

2Y0
1
0
1
1
1
1

2Y1
1
1
0
1
1
1

2Y2
1
1
1
0
1
1

OUTPUTS
2Y3
1Y0
1
1
1
1
1
1
1
1
0
1
1
0

1Y1
1
1
1
1
1
1

1Y2
1
1
1
1
1
1

1Y3
1
1
1
1
1
1

0
0
0

1
1
1

0
1
1

1
0
1

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

0
1
1

1
0
1

1
1
0

RESULT:
Thus the encoder and decoder circuits were designed and implemented.

114

EX.NO.19

STUDY OF FLIP FLOPS

AIM:
To verify the characteristic table of RS, D, JK, and T Flip flops .

APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.

Name of the Apparatus


Digital IC trainer kit
NOR gate
NOT gate
AND gate ( three input )
NAND gate
Connecting wires

THEORY:

Range

Quantity
1

IC 7402
IC 7404
IC 7411
IC 7400
As required

A Flip Flop is a sequential device that samples its input signals and changes its output
states only at times determined by clocking signal. Flip Flops may vary in the number of
inputs they possess and the manner in which the inputs affect the binary states.
RS FLIP FLOP:
The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form. The Flip Flop is

reset when the R input high and S input is low. The Flip Flop is set when the S input is high
and R input is low. When both the inputs are high the output is in an indeterminate state.
D FLIP FLOP:
To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when
both inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the
same time. This is obtained by making the two inputs complement of each other.
JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs
behave like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input
and the clock pulse, similarly the output Q is ANDed with J input and the Clock pulse.
When the clock pulse is zero both the AND gates are disabled and the Q and Q output retain
their previous values. When the clock pulse is high, the J and K inputs reach the NOR gates.
When both the inputs are high the output toggles continuously. This is called Race around
condition and this must be avoided.
T FLIP FLOP:
115

This is a modification of JK Flip Flop, obtained by connecting both inputs J and K


inputs together. T Flip Flop is also called Toggle Flip Flop.
RS FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:
CLOCK
PULSE
1
2
3
4

INPUT
S
0
0
0
0

R
0
0
1
1

PRESENT
STATE (Q)
0
1
0
1

NEXT
STATE(Q+1)
0
1
0
0

STATUS

5
6
7
8

1
1
1
1

0
0
1
1

0
1
0
1
D FLIP FLOP

1
1
X
X

116

LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:
CLOCK
PULSE

INPUT
D

PRESENT
STATE (Q)

NEXT
STATE(Q+1)

1
2

0
0

0
1

0
0

STATUS

3
4

1
1

0
1

1
1

117

JK FLIP FLOP
LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:
CLOCK
PULSE
1
2

INPUT
J
0
0

K
0
0

PRESENT
STATE (Q)
0
1

NEXT
STATE(Q+1)
0
1

STATUS

3
4
5
6
7
8

0
0
1
1
1
1

1
1
0
0
1
1

0
1
0
1
0
1

0
0
1
1
1
0

118

T FLIP FLOP
LOGIC SYMBOL:

CIRCUIT DIAGRAM:

CHARACTERISTIC TABLE:

CLOCK
PULSE
1
2
3
4

INPUT
T
0
0
1
1

PRESENT
STATE (Q)
0
1
0
1

NEXT
STATE(Q+1)
0
0
1
0

STATUS

119

PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and observe the status of all the flip flops.

RESULT:
The Characteristic tables of RS, D, JK, T flip flops were verified.

120

EX.NO.20

ASYNCHRONOUS COUNTER

AIM:
To implement and verify the truth table of an asynchronous decade counter.

APPARATUS REQUIRED:
S.No
1.
2.
4.
5.

Name of the Apparatus


Digital IC trainer kit
JK Flip Flop
NAND gate
Connecting wires

THEORY:

Range
IC 7473
IC 7400

Quantity
1
2
1
As required

Asynchronous decade counter is also called as ripple counter. In a ripple counter the
flip flop output transition serves as a source for triggering other flip flops. In other words the
clock pulse inputs of all the flip flops are triggered not by the incoming pulses but rather by the
transition that occurs in other flip flops. The term asynchronous refers to the events that do not
occur at the same time. With respect to the counter operation, asynchronous means that the
flip flop within the counter are not made to change states at exactly the same time, they do not
because the clock pulses are not connected directly to the clock input of each flip flop in the
counter.
PIN DIAGRAM OF IC 7473:

121

CIRCUIT DIAGRAM:

TRUTH TABLE:
OUTPUT

S.No
1
2
3
4
5
6
7
8
9

CLOCK
PULSE
1
2
3
4
5
6
7
8

D(MSB)
0
0
0
0
0
0
0
0
1

C
0
0
0
0
1
1
1
1
0

B
0
0
1
1
0
0
1
1
0

A(LSB)
0
1
0
1
0
1
0
1
0

10
11

9
10

1
0

0
0

1
0

0
0

PROCEDURE:
1. Connections are given as per the circuit diagrams.
2. Apply the input and verify the truth table of the counter.
122

RESULT:
The truth table of the Asynchronous counter was hence verified.

123

EX.NO.21

SHIFT REGISTERS

AIM:
To implement the following shift register using flip flop

(i)

SIPO

(ii)

SISO

(iii)

PISO

(iv)

PIPO

APPARATUS REQUIRED:
S. No
1.

Name
IC

Specification
7474

Quantity
1

2.

Digital IC Trainer Kit

3.
Patch chords
THEORY:

1
-

A register is used to move digital data. A shift register is a memory in which


information is shifted from one position in to another position at a line when one clock pulse is
applied. The data can be shifted either left or right direction towards right or towards left.

A shift register can be used in four ways depending upon the input in which the data are
entered in to and takes out of it. The four configuration are given as
Serial input - Serial output
Parallel input - Serial output
Serial input - Parallel output
Parallel input - Parallel output

RS or JK flip flop are used to construct shift register have D flip flop is used for
constructing shift register.
PROCEDURE:
Give the connections as per the circuit
Set or Reset at the pin 2 which its the MSB of serial data.
Apply a single clock Set or Reset second digital input at pin 2.
Repeat step 2 until all 4-bit data are taken away.

124

SHIFT REGISTER:
+5VCC CLR2

_
D2

CLK

PR2

Q2

Q2

14

13

12

11

10

IC 7474
1

CLR1

SIPO LEFT SHIFT


Q3

D1

CLK

PR1

_
1

Q1

GND

+5VCC
Q2

Q1

10
9

12
IC 7474
13

Q0

11

10

4
12

3
13

D IN

IC 7474

IC 7474

IC 7474
1

11

+5VCC
CLK

SIPO RIGHT SHIFT

125

SISO
DOUT

+5VCC

10
9

12

IC 7474
11
13

10

12

DIN
Q2

PIPO

SISO
Data
input =
1100

IC 7474

IC 7474

13

Q1

IC 7474

11

+5VCC
CLK

Q0

Clock
0
4
8
12
16

Serial input
0
1
1
0
0

Serial output
0
1
1
0
0

126

PIPO
Clock

Parallel input
A

Parallel output
D

QA

QB

QC

QD

SIPO
Left shift
No of clk pulse

Serial input Din

Parallel output
Q3 Q2 Q1 Q0

0
1
2
3

0
1
1
0

0
0
0
0

0
0
0
1

0
0
1
1

0
1
1
0

4
5
6
7

1
0
0
0

1
1
0
1

1
0
1
0

0
1
0
0

1
0
0
0

Right Shift
No of clock pulse

Serial input Din

0
1
2

0
1
1

Parallel output
Q3 Q2 Q1 Q0
0
0
0
0
1
0
0
0
0
1
0
0

4
5
6
7
8

1
0
0
0
0

1
0
0
0
0

1
1
0
0
0

0
1
1
0
0

1
0
1
1
0

127

RESULT:

Thus the SISO, SIPO, PISO, PIPO shift registers were designed and implemented.

128

EX.NO.22
AIM:

DIFFERENTIATOR

To design a Differentiator circuit for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.

Name of the Apparatus


Function Generator
CRO
Dual RPS
Op-Amp
Bread Board
Resistors

Range
3 MHz
30 MHz
0 - 30 V
IC 741

Quantity
1
1
1
1
1

7.
8.

Capacitors
Connecting wires and probes

As required

THEORY:
The differentiator circuit performs the mathematical operation of differentiation; that is,
the output waveform is the derivative of the input waveform. The differentiator may be
constructed from a basic inverting amplifier if an input resistor R 1 is replaced by a capacitor C 1.
The expression for the output voltage is given as, Vo = - Rf C1 (dVi /dt)
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input terminal of

the op-amp to compensate for the input bias current. A workable differentiator can be
designed by implementing the following steps:
1. Select fa equal to the highest frequency of the input signal to be differentiated. Then,
assuming a value of C1 < 1 F, calculate the value of Rf.
2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 = Rf Cf.
3. The differentiator is most commonly used in waveshaping circuits to detect high
frequency components in an input signal and also as a rate-of-change detector in FM
modulators.
PIN DIAGRAM:

129

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

DESIGN:
Given fa = --------------We know the frequency at which the gain is 0 dB, f a = 1 / (2 Rf C1)
Let us assume C1 = 0.1 F; then

Rf = _________
Since fb = 20 fa, fb = --------------We know that the gain limiting frequency fb = 1 / (2 R1 C1)
Hence R1 = _________
Also since R1C1 = Rf Cf ; Cf = _________
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.

4. The output voltage is obtained in the CRO and the input and output voltage waveforms
are plotted in a graph sheet.

130

OBSERVATIONS:
Input - Sine wave
S.No.
Amplitude
( No. of div x Volts per div )
Input
Output

Time period
( No. of div x Time per div )

S.No.

Input - Square wave


Amplitude
( No. of div x Volts per div )

Input
Output
DIFFERENTIATOR:
INPUT SIGNAL:

Time period
( No. of div x Time per div )

Time Period
OUTPUT SIGNAL:

Time Period

131

Amplitude

Amplitude

RESULT:

The design of the Differentiator circuit was done and the input and output waveforms
were obtained.

132

EX.NO.23

INTEGRATOR

AIM:
To design an Integrator circuit for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:
S.No
Name of the Apparatus
1.
Function Generator
2.
CRO
3.
Dual RPS
4.
Op-Amp
5.
Bread Board
6.
Resistors
7.
Capacitors
8.
Connecting wires and probes

Range
3 MHz
30 MHz
0 - 30 V
IC 741

As required

Quantity
1
1
1
1
1

THEORY:
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor R f is replaced by a capacitor C f . The expression for the
output voltage is given as,
Vo = - (1/Rf C1) Vi dt
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
input signal. Normally between f a and fb the circuit acts as an integrator. Generally, the value of
fa < fb . The input signal will be integrated properly if the Time period T of the signal is larger
than or equal to Rf Cf. That is,

T R f Cf
The integrator is most commonly used in analog computers and ADC and signal-wave
shaping circuits.
PIN DIAGRAM:

133

CIRCUIT DIAGRAM OF INTEGRATOR:

DESIGN:
We know the frequency at which the gain is 0 dB, f b = 1 / (2 R1 Cf)
Therefore fb = _____
Since fb = 10 fa, and also the gain limiting frequency f a = 1 / (2 Rf Cf)
We get, Rf = _______ and hence R1 = __________

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-Amp IC.
3. By adjusting the amplitude and frequency knobs of the function generator, appropriate
input voltage is applied to the inverting input terminal of the Op-Amp.

134

4. The output voltage is obtained in the CRO and the input and output voltage waveforms
are plotted in a graph sheet.
OBSERVATIONS:

S.No.
Input
Output
MODEL GRAPH:
INTEGRATOR:
INPUT SIGNAL:

Amplitude
( No. of div x Volts per div )

Time period
( No. of div x Time per div )

OUTPUT SIGNAL:

Time Period

Amplitude
Amplitude
RESULT:
The design of the Integrator circuit was done and the input and output waveforms were
obtained.

135

EX.NO. 24
AIM:

TIMER IC APPLICATIONS - I
(ASTABLE MULTIVIBRATOR)

To design an astable multivibrator circuit for the given specifications using 555 Timer

IC.
APPARATUS REQUIRED:
S. No
1.
2.
3.
4.
5.
6.

Name of the Apparatus


Function Generator
CRO
Dual RPS
Timer IC
Bread Board
Resistors

Range
3 MHz
30 MHz
0 - 30 V
IC 555

Quantity
1
1
1
1
1

7.
8.

Capacitors
Connecting wires and probes

As required

THEORY:
An astable multivibrator, often called a free-running multivibrator, is a rectangularwave-generating circuit. This circuit do not require an external trigger to change the state of
the output. The time during which the output is either high or low is determined by two
resistors and a capacitor, which are connected externally to the 555 timer. The time during
which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the output is high and is
given by,

tc = 0.69 (R1 + R2) C


Similarly the time during which the capacitor discharges from 2/3 V cc to 1/3 Vcc is
equal to the time the output is low and is given by,
td = 0.69 (R2) C
Thus the total time period of the output waveform is,
T = tc + td = 0.69 (R1 + 2 R2) C

The term duty cycle is often used in conjunction with the astable multivibrator. The
duty cycle is the ratio of the time t c during which the output is high to the total time period T. It
is generally expressed in percentage. In equation form,
% duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100

136

PIN DIAGRAM:

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

137

DESIGN:
Given f= 4 KHz,
Therefore, Total time period, T = 1/f = ____________

We know, duty cycle = tc / T


Therefore,
tc=-----------------------and td = ____________
We also know for an astable multivibrator td
= 0.69 (R2) C
Therefore, R2 = _____________
tc = 0.69 (R1 + R2) C
Therefore, R1 = _____________

PROCEDURE:
1.
2.
3.
4.

Connections are given as per the circuit diagram.


+ 5V supply is given to the + Vcc terminal of the timer IC.
At pin 3 the output waveform is observed with the help of a CRO
At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage
waveforms are plotted in a graph sheet.

OBSERVATIONS:

S.No

Waveforms

Amplitude
( No. of div x
Volts per div )

Time period
( No. of div x
Time per div )
tc

1.

Output Voltage , Vo

td

2.

Capacitor voltage , Vc

138

MODEL GRAPH:

Vcc

T (ms)
2/3 Vcc

1/3 Vcc
TON

TOFF

O/p
voltage
Capacitor
voltage
RESULT:
The design of the Astable multivibrator circuit was done and the output voltage and
capacitor voltage waveforms were obtained.

139

TIMER IC APPLICATIONS -II


(MONOSTABLE MULTIVIBRATOR)
AIM:

To design a monostable multivibrator for the given specifications using 555 Timer IC.
APPARATUS REQUIRED:
S.No
1.
2.
3.
4.
5.
6.

Name of the Apparatus


Function Generator
CRO
Dual RPS
Timer IC
Bread Board
Resistors

Range
3 MHz, Analog
30 MHz
0 - 30 V
IC 555

Quantity
1
1
1
1
1

7.
8.

Capacitors
Connecting wires and probes

As required

THEORY:
A monostable multivibrator often called a one-shot multivibrator is a pulse generating
circuit in which the duration of the pulse is determined by the RC network connected
externally to the 555 timer. In a stable or stand-by state the output of the circuit is
approximately zero or at logic low level. When an external trigger pulse is applied, the output
is forced to go high (approx. Vcc). The time during which the output remains high is given by,
tp = 1.1 R1 C

At the end of the timing interval, the output automatically reverts back to its logic low
state. The output stays low until a trigger pulse is applied again. Then the cycle repeats.
Thus the monostable state has only one stable state hence the name monostable.
PIN DIAGRAM:

140

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

DESIGN:

Given tp = 0.616 ms = 1.1 R1 C


Therefore, R1 = _____________
PROCEDURE:
1.
2.
3.
4.

Connections are given as per the circuit diagram.


+ 5V supply is given to the + Vcc terminal of the timer IC.
A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC
At pin 3 the output waveform is observed with the help of a CRO

5. At pin 6 the capacitor voltage is obtained in the CRO and the V 0 and Vc voltage
waveforms are plotted in a graph sheet.
OBSERVATIONS:

S.No

Amplitude
( No. of div x
Volts per div )

Time period
( No. of div x
Time per div )
ton

toff

1.

Trigger input

2.

Output Voltage , Vo

3.

Capacitor voltage , Vc
141

MODEL GRAPH:

RESULT:
The design of the Monostable multivibrator circuit was done and the input and output
waveforms were obtained.

142