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An Improved High Speed Charge Pump

in 90 nm CMOS Technology
1, 2

1, 2

1, 2

Sheng Chen , Zhiqun Li , Qin Li


Institute of RF & OE ICs, Southeast University, Nanjing 210096, China
2
School of Integrated Circuits, Southeast University, Nanjing 210096, China
1

AbstractThis paper proposes an improved current steering


charge pump in high speed application in IBM 90 nm technology.
By using the current compensation circuit and accelerating
acquisition circuit, the output voltage range with current
matching is obviously enlarged. Simulation result shows that the
charge pump can be applied for 500MHz frequency, with 1.4mW
power consumption. Moreover, the current mismatch ratio of
charge pump is less than 0.01% with output voltage swinging
from 0.1 to 1.1V, very suitable for high speed PLL application.

In this paper, an improved current steering charge pump


with high performance in high speed application is proposed.
Section II covers the traditional current steering charge pump
designed with charge sharing, current variation and a long
locked time. Section III shows the complete schematic of the
improved charge pump with system-level, and discusses the
techniques used to improve the performance, such as reducing
the transient glitches and so on. Section IV displays the
simulation result of the proposed charge pump circuit. Section
V draws conclusions from this work [2].

Index termsHigh speed, current compensation, accelerating


acquisition, 500MHz, 0.01%.

I.

II. CONVENTIONAL CHARGE PUMP

INTRODUCTION

As shown in Fig.2, for the switchers (UP+ and UP-,DN+


and DN-) are on or not alternately, the mirror current of M2
and M10 is always effective[3].
The operation speed of charging and discharging current
will only depend on the switcher(UP+,UP-,DN+,DN-) size,
which makes the current steering charge pump has an
excellent performance in high speed application. In order to
expand the effective range of current match, in Fig.2,
MOSFET of current mirror is used for one layer (such as from
M1 to M2, and from M9 to M10), instead of cascade
architecture. What more, a high gain error amplifier added
with a large load capacitance is used to improve the precision
of the mirror current. Fig.3 shows the output currents
comparison, the output voltage with and without an error
[4]
amplifier .

With the development of society, more and more


communication systems, such as millimeter-wave radar, radio
telescope and so on, need high speed PLL, which requires a
high speed charge pump with the excellent performance.
Conventional charge pump has lots of defects for high speed
application, for example, big size of mirror MOSFET, large
parasitic capacitance and other non-ideal factors. However,
the charge pump circuit in this paper depending on the
improved current steering technique has an excellent high
speed performance.
As shown in Fig.1, The simple model of charge pump is
introduced the function of CP. When UP signal is high, the
switcher connects to S1 and V is charged by Iup. When DN
signal is high, the switcher connects to S2 and V is discharged
by Idn. While UP and DN are high at the same time, both Iup
and Idn are available, and VC holds the original voltage [1].
C

Fig.1 The simple model of charge pump

Fig.2 A conventional current steering charge pump

Project supported by the National Basic Research Program of China (No. 2010CB327404)
___________________________________
978-1-61284-307-0/11/$26.00 2011 IEEE



(a)

The techniques used to improve the performance are listed


in detail as follows.
B. Current compensation circuit
It has been shown in Fig.5 that discharging current will
decrease rapidly when the output voltage gradually drops
without other additional circuit, which is due to the mirror
MOSFET channel modulation. As a result, the matching line
of the charging current and discharging current amplitude will
decrease by 20%.
Unfortunately, the variation of charge pump output current
will result in variation of the PLL loop bandwidth. Such a big
variation may bring the PLL from a stable region to an
unstable region. However, if we have the compensation
current circuit, the current will be increased. As shown in
Fig.5, the smaller the output voltage is, the larger the
compensation current is [3].
As shown in Fig.6, the current compensation circuit is with
two PMOS. M1 is selfbias, and M2 is controlled by point
Vout. Applied by this architecture, the bias voltage VBN will be
dynamically adjusted. When the output voltage is higher than
the common-mode level, M1 and M2 of the compensation
circuit cut off and have no effect on bias voltages VBN.
However, on the other hand, when the Vout decreases toward
zero, the Vgs of the M2 increasing, M2 turns on [5].
Thus the compensation circuit of M1 and M2 starts to
conduct and inject current into M3. This results in an increase
of the bias current for the charge pump as an effective
compensation with enhancing the VBN voltage. The
consequence can be shown that the lower the Vout voltage
becomes, and the higher the compensation current has.

(b)

Fig.3 The charging and discharging current. (a) Without an error amplifier.
(b)With an error amplifier

In Fig. 3(a), without the error amplifier, the charging


current and discharging current are close to each other only
when the output voltage is near the common-mode voltage
(0.6V). When the output voltage goes farther away from the
common-mode level, the difference between the charging and
discharging current becomes larger. If the desired output
swing is 0.2V below 0.6V, the current mismatch can be as
high as 15%, which will cause unacceptable phase offset in
many applications. However, after the introduction of an error
amplifier circuit, in Fig. 3(b), the charging current and
discharging current match is very well for a large output
[3]
voltage swing .
III. DESIGN OF THE PROPOSED CHARGE PUMP CIRCUIT
A. The Proposed Current Steering Charge Pump
In order to improve the conventional current steering charge
pump performance, the proposed charge pump consisting of
current compensation circuit, clock feed through reduction
circuit, accelerating acquisition circuit, and rail to rail voltage
follower is shown in Fig.4.
The proposed circuit has two amplifies, AMP1 and AMP2.
Both of the amplifiers are designed by rail to rail. AMP1 is
used to improve the matching precision between charging
current and discharging current. Similarly, AMP2 is added to
reduce the effect of charge sharing, which makes Voltage of
point Vout1 follow the voltage of point Vout.

Fig.5 Output current with and without compensation circuit

Fig.6 The schematic of current compensation circuit


Fig.4 The architecture of the proposed current steering charge pump

As a result, in Fig.5, the current compensation technique



D. Suppression of clock feed through

extends significantly the flat range of the output voltage. The


output current variation can be controlled within 2% when the
output voltage is higher than 0.1V [3].
C. Accelerating acquisition circuit
As shown in Fig.7, the circuit of accelerating acquisition is
implemented by adding two other MOSFET (M1, M2). Thus,
the charging current has two branches to be coped. I1 is
implemented by (M1, M2), and I2 is implemented by (M3,
M4). If the voltage of point Vout is high and AMP1 has a high
amplifier, both of two branches current will be copied
accurately due to the voltage of Vref following the the voltage
of Vout . However, during point Vout voltage toward zero, the
MOSFET (M8, M10) is gradually into the linear area. As a
result, the current of (M8, M10) will become small. However,
the current of (M7, M9) will be kept large due to the large
current I1 with VBN maintaining constant and playing the main
role in the current mirror. Obviously, the current of (M7, M9)
is different from (M8, M10). Thus, the AMP1 cant make the
voltage of Vref follow the the voltage of Vout. As a result, the
charging current with adding accelerating acquisition circuit
in Fig. 8(b) is large than that without adding accelerating
acquisition circuit in Fig. 8 (a), which will help PLL to
accelerate acquisition and reduce the acquisition time.

Fig.9 Suppression of clock feed through

The clock feed through glitch is generated by the gate to


drain capacitance of the output node. Let us assume that the
input voltage has a transition time of T to switch from VL to
VH. The generated glitch current is expressed as [3]
(1)
Iglitch=Cgs(VH-VL)T =CgsK
K represents the slew rate of the input voltage during
transition. The glitch magnitude is proportional to the input
voltage slew rate and gate to drain capacitance. The amplitude
of the clock feed glitch can be large than the output current
itself if the frequency is extremely fast.
In order to reduce the current of the clock feed glitch, M2
and M4 is provided in Fig.9. The source and drain terminals
of M2 and M4 are merged together respectively. The sizes
of transistors M2 and M4 are half of the transistors M2 and
M4. Because M2 has two ports attached to output, the
equivalent parasitic capacitance for output voltage between
M2 and M2 is same. Thus, in Fig.9, if the gate voltage of M2
and M2 is opposite, the dynamic current of M2 and M2
clock feed glitch will be offset.
IV. SIMULATE RESULT
In Fig.10, the result shows the current matching relation of
the conventional charge pump shown in Fig.2, the current
drops fast when output voltage is toward zero due to the
MOSFET channel modulation phenomenon, which will affect
the stability of the PLL.

Fig.7 The schematic of accelerating acquisition circuit

120

Id n
Iu p

Current(A)

100
80
60
40
20
0

(a)

0 .0

(b)

Fig.8 The charging and discharging current. (a) Without an accelerating


acquisition circuit. (b) With an accelerating acquisition circuit.

0 .2

0 .4
0 .6
0 .8
O u tp u t vo lta g e(V )

1 .0

1 .2

Fig.10 The conventional charge pump simulation result of charging and


discharging current



In contrast, in Fig.11, the circuit with the improved


techniques displays a perfect performance. Output currents
mismatch ratio is less than 0.01%, during the period the output
was varied from 0.1V to 1.1V. Moreover, in this match range,
charging current and discharging current fluctuation is from
99.3A to 101.2A, which is controlled within 2%. Beside,
when output voltage toward zero, the current of charge is
larger than 50A, which makes the acquisition time reduce.
The proposed circuit not only has a good performance in
static match, but also has the excellent performance of
dynamic characteristics. Fig.12 shows the variation of
transient Iup current as well as Fig.13 shows the variation of
transient Idn current. We can find that the dynamic mismatch
of current is less than 0.5%. The condition of simulation is
1.2V supply voltage and the 500MHz operational frequency [6].

Fig.14 Layout of PFD and the proposed charge pump

The power consumption for the proposed charge pump is


1.4mW for a 1.2V supply, including the 100A current source.
The layout including PFD and charge pump is shown in
Fig.14, and the charge pump effective size is 250*180 m2.
V. CONCLUSION

Id n
Iu p

120

The characteristics of the proposed charge pump and other


recently published charge pumps are summarized in TABLE 1.

100
Current(A)

80

TABLE1
Performance of the proposed and recently published charge pumps

60
40

Ref

Technology

20

Current
mismatch rate

Voltage swing

Frequency(MHz)

Operation

100

5%

0.2-1.0V

0
0 .0

0 .2

0 .4

0 .6

0 .8

1 .0

[1]

1 .2

O u tp u t v o lta g e (V )

Fig.11The proposed charge pumps simulation result of charging and


discharging current

0.35m

(flat current
variation )

[2]

0.13m

50

<3.2%

[3]

0.35m

312.5

<1%

this

IBM 90nm

500

<0.01%

0.1-1.1V

ACKNOWLEDGMENT
The author wishes to thank the group members such as
Geliang Yang, Zhu Li, Faen Liu, Jing tu and Ting Guo for
valuable discussions. This research is sponsored by National
Basic Research Program of china.
REFERENCES
[1]
[2]

Fig.12 Output current (Iup) variation of time transient effect

[3]

[4]
[5]
[6]

Fig.13 Output current (Idn) variation of time transient effect



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