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Observations Made While Testing FPGA LOADER in Serial Protocol Board

1. Without Encryption: Able to program the parallel FLASH through FPGA


LOADER
Following procedure must be strictly followed.
a) First Program the MachXO with the FPGA LOADER Bit stream by
using Flash Erase, program and verify option.
b) Choose the Advanced Flash Programming (FPGA LOADER) option,
and keep the MachXO in SRAM Bypass mode.
c) Program the Parallel flash with the ECP3 Configuration information.
Note: This procedure in lattice Diamond 2.1
2. With Encryption: Was not able to test the FPGA LOADER. Since flash data
size will be around 92Mb with encryption, but our serial protocol board
supports only 64Mb flash.
Following table captures the time it takes to perform erase, program and
verification of the parallel flash with different programming tools
SLNO
1

SOFTWARE
Diamond 2.1

ispVM 18.01

OPERATION

TIME IN MINUTES

Erase, Program, verify

17 (Approximately)

Program + Verify

NA
25 Minutes
(Approximately)
21 Minutes 10
seconds + 4 Minutes
32 Seconds = 26
(Approximately)

Erase, Program, verify

Program + Verify

NA-->In lattice diamond we cannot choose


program and verify options separately. Even if we
choose program Only or verify only options, it
automatically reverts back to Erase, Program and
verify option, before proceeding with
programming.
NOTE:
Board: Serial Protocol Board.
FPGA LOADER: MachXO (LCMXO1200C-5M132C).
FLASH: 64Mb (S29GL064A).

16 minutes 53
Seconds
16 minutes 53
Seconds
24 Minutes 26
Seconds

25 Minutes 42
Seconds

FPGA: ECP3 (LFE3-95E-7FN1156C)

Question
What is the maximum allowable project path length in lattice diamond?
Answer
This length is same as the allowable path size of windows operating system
which is 260 characters. This is derived as follows
Maximum allowable path name: path_length (till the implementation
folder) + {project_name} _ {implementation name}
Example: Assumptions project is located in the C directory and the
implementation folder name is diamond_project and project name is
counter4bit
path_length (till the implementation folder) = C:\diamond_project +
counter4bit_counter4bit_synpflify
In this case path length is 55 Character and it is with in the allowable
range. But this size shouldnt exceed the allowable length of 260 characters,
if this happens diamond throws an error in the synthesis stage itself.

ECP3 FPGA PLL CHARACTERIZATION


Following were the PLL setting for generation of 100 MHz clock from 40
MHz
MODE: Divider
CLKOP_DIV = 8
CLKFB_DIV = 5
CLKI_DIV = 2
With this divider setting allowable i/p frequency range (10Mhz - 61
Mhz) to maintain pll in the lock state (PLL wont get locked to Some
SL
NO
1
2
3
4
5

I/P FREQUECNY
CHANGE In MHz
10 -->20
20-->30
20-->40
20-->50
20-->61

TIME(unlock_to_lock) in
micro-seconds
8.6
12
15
20
33

combination of i/p frequency with in this range).


Note : TIME(unlock_to_lock) is the time taken by the PLL to come
back from unlock state to the lock state if there is any variation in
the input frequency. From the table we can conclude that
maximum time taken by the PLL to get to lock is 33uS (this is the
maximum time delay of the ECP3 PLL), this happens when i/p
changes at a faster rate (in our case it is from 20 MHz to 61 MHz)

1. CPLD Power Supply Design : Ponits which are marked in red colour
are not optimum values, we can ask customer to have look into
these parameters.
Value which is
there in
schematic /
getting
generated
from the
power supply
12.875 V
3.328 V

SLNO
1
2

PARAMETER
Vin (i/p voltage)
Vout (o/p voltage)

Value
Requirement/
Recommeded
3.5 V - 42 V
3.3 V

Fsw(Switching
frequecny)

100Khz - 2.5
MHz

596 Khz

Lo (minimu
required inductor
value)

9.78uH

22uH

Iripple (Inductor
ripple current which
is nothing but o/p
ripple current)

should be very
less

188.20mV

Cout (o/p capacitor)

> 16.80uF

100uF

Remarks
Okay
Okay
This is set
through resistor,
by adjusting this
parameter we
can adjust the
output ripple
current which is
huge in our case
(188.20mV)
Inductor value
depends on the
i/p voltage, o/p
voltage,switchin
g frequency, o/p
ripple current
requirement
This value
seems to be
huge, by
considering
LVDS input since
LVDS difference
voltage itself will
be arround
175mV
This value is
okay

2. Compensation capacitor (C1082) in non working board its value is


4.7nf, whereas in working board it is 22pf. The value of this
capacitor is very significant; if this value is not proper sometimes
there will be oscillation at the output of the power supply. This
oscillation could interfere with our data.

3. In nonworking board there are some decoupling capacitors are


missing (VCCIO3/4/5 has three 100nf & one 10nf capacitors)
compared to working board in working board three 100nf & three
10nf capacitors are connected to the VCCIO3/4/5.

4. I am not able to see any transient suppression circuit at the input of


the power supply, this is the place from where transients can enter
the system. We can ask customer to connect bidirectional TVS
(Transients Voltage Suppresser) at the input of the power supply.

5. In working board (KALA) they are following conventional termination


technique (They are putting 100 Ohm resistor b/w the differential
line to match the characteristic impedance of the line). In non
working board they are following some unconventional termination
technique, where they are connecting 100 ohm resistor between
differential line and 100 Ohm resistor in series with the lines which
forms the differential line.

POWER SUPPLY DE-CAP


2.
Customer has sent us only one page schematics that is power supply design,
where is the PLD Design? And also capacitor you are referring (C1017) is a
power supply capacitor as per mine understanding it should be near to power
supply not to PLD. The 100uF (C1017) capacitor is more than sufficient (as
per calculation by considering o/p voltage ripple, switching frequency and
variation in load current it is 16.80uF).
Hi Sungkyu,
Reference design of 802.3ae (10Gb Phy) is available for ECP3, for this you have to have Lattice
ECP3 Serial Protocol Board.