Beruflich Dokumente
Kultur Dokumente
Data Sheet
With its unique array of configurable blocks, PSoC 3 is a true system level solution providing microcontroller unit (MCU), memory,
analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal
processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples
(near DC voltages) to ultrasonic signals. The CY8C38 family can handle dozens of data acquisition channels and analog inputs on
every general-purpose input/output (GPIO) pin. The CY8C38 family is also a high-performance configurable digital system with some
part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In
addition to communication interfaces, the CY8C38 family has an easy to configure logic array, flexible routing to all I/O pins, and a
high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt
components and boolean primitives using PSoC Creator, a hierarchical schematic design entry tool. The CY8C38 family provides
unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes
through simple firmware updates.
Features
DC to 67 MHz operation
Multiply and divide instructions
Flash program memory, up to 64 KB, 100,000 write cycles,
20 years retention, and multiple security features
512-byte flash cache
Up to 8-KB flash error correcting code (ECC) or configuration
storage
Up to 8 KB SRAM
Up to 2 KB electrically erasable programmable read-only
memory (EEPROM), 1 M cycles, and 20 years retention
24-channel direct memory access (DMA) with multilayer
AHB[1] bus access
Programmable chained descriptors and priorities
High bandwidth 32-bit transfer support
Low voltage, ultra low-power
Wide operating voltage range: 0.5 V to 5.5 V
High efficiency boost regulator from 0.5-V input through 1.8-V
to 5.0-V output
0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 48 MHz
Low-power modes including:
1-A sleep mode with real time clock and low-voltage
detect (LVD) interrupt
200-nA hibernate mode with RAM retention
Versatile I/O system
28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),
two USBIOs[2])
Any GPIO to any digital or analog peripheral routability
[2]
LCD direct drive from any GPIO, up to 46 16 segments
[3]
CapSense support from any GPIO
1.2-V to 5.5-V I/O interface voltages, up to four domains
Maskable, independent IRQ on any pin or port
Schmitt-trigger transistor-transistor logic (TTL) inputs
All GPIO configurable as open drain high/low,
pull-up/pull-down, High Z, or strong output
Configurable GPIO pin state at power-on reset (POR)
25 mA sink on SIO
Digital peripherals
20 to 24 programmable logic device (PLD) based universal
digital blocks (UDB)
[2]
Full CAN 2.0b 16 Rx, 8 Tx buffers
[2]
Full-speed (FS) USB 2.0 12 Mbps using internal oscillator
Up to four 16-bit configurable timer, counter, and PWM blocks
Notes
1. AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus
2. This feature on select devices only. See Ordering Information on page 122 for details.
3. GPIOs with opamp outputs are not recommended for use with CapSense.
408-943-2600
Revised June 18, 2012
Page 2 of 137
8-bit
Timer
Quadrature Decoder
UDB
Sequencer
IMO
UDB
UDB
16-bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22
UDB
UDB
UDB
UDB
UDB
FS USB
2.0
4x
Timer
Counter
PWM
12-bit SPI
UDB
Master/
Slave
UDB
UDB
8-bit
Timer
Logic
UDB
8-bit SPI
I 2C Slave
UDB
I2C
CAN
2.0
16-bit PRS
Logic
UDB
UART
UDB
USB
PHY
GPIOs
GPIOs
Clock Tree
32.768 KHz
( Optional)
Digital System
System Wide
Resources
Xtal
Osc
SIO
4 to 25 MHz
(Optional)
GPIOs
Digital Interconnect
RTC
Timer
System Bus
EEPROM
SRAM
CPU System
8051 or
Cortex M3CPU
Interrupt
Controller
Program &
Debug
GPIOs
Memory System
WDT
and
Wake
Program
GPIOs
Debug &
Trace
EMIF
PHUB
DMA
FLASH
ILO
Boundary
Scan
Power Management
System
LCD Direct
Drive
Digital
Filter
Block
POR and
LVD
1.8V LDO
SMP
Analog System
ADC
+
4x
Opamp
-
3 per
Opamp
4 x SC/CT Blocks
(TIA, PGA, Mixer etc)
Temperature
Sensor
4 x DAC
1x
Del Sig
ADC
+
4x
CMP
-
GPIOs
1.71 V to
5.5 V
Sleep
Power
GPIOs
SIOs
Clocking System
CapSense
0 .5 V to 5.5 V
( Optional)
Notes
4. This feature on select devices only. See Ordering Information on page 122 for details.
5. GPIOs with opamp outputs are not recommended for use with CapSense.
Page 4 of 137
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in Figure 2-3 through Figure 2-6 show the pins that are
powered by each VDDIO.
Each VDDIO may source up to 100 mA total to its associated I/O
pins, as shown in Figure 2-1.
Figure 2-1. VDDIO Current Limit
IDDIO X = 100 mA
VDDIO X
I/O Pins
PSoC
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA total, as
shown in Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins = 100 mA
VDDIO X
I/O Pins
PSoC
VSSD
For the 48-pin devices, the set of I/O pins associated with
VDDIO0 plus VDDIO2 may sink up to 100 mA total. The set of
I/O pins associated with VDDIO1 plus VDDIO3 may sink up to a
total of 100 mA.
Page 5 of 137
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
Lines show 46
VDDIO to I/O
45
supply
association 44
43
42
41
40
39
38
37
SSOP
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
VDDIO3
P15[1] (GPIO, MHZ XTAL: XI)
P15[0] (GPIO, MHZ XTAL: XO)
VCCD
VSSD
VDDD
[6]
P15[7] (USBIO, D-, SWDCK)
[6]
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
VDDIO1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, Configurable XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
[8]
VDDIO1
13
14
(Top View)
(GPIO) P1[6]
VDDIO0
38
37
VCCD
P0[7] (IDAC2, GPIO)
42
41
40
39
VDDD
VSSD
43
P2[4] (GPIO)
P2[3] (GPIO)
QFN
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
17
18
19
20
21
22
23
24
3
4
5
6
15
16
VSSB
IND
VB
VBAT
(GPIO, TMS, SWDIO) P1[0]
(GPIO, TCK, SWDCK) P1[1]
(GPIO, Configurable XRES) P1[2]
(GPIO, TDO, SWV) P1[3]
(GPIO, TDI) P1[4]
(GPIO, nTRST) P1[5]
Lines show
VDDIO to I/O
supply association
(GPIO) P1[7]
1
2
(GPIO) P2[6]
(GPIO) P2[7]
46
45
44
48 P2[5] (GPIO)
47 VDDIO2
Note
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Page 6 of 137
P15[5] (GPOI)
P15[4] (GPIO)
VDDD
VSSD
VCCD
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO, Opamp2-)
P0[4] (GPIO, Opamp2+)
VDDIO0
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
P2[5] (GPIO)
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
LINES SHOW
VDDIO TO I/O
SUPPLY
ASSOCIATION
QFN
(TOP VIEW)
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
[10]
(USBIO, D+, SWDIO) P15[6]
[10] (USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
(MHZ XTAL: XO, GPIO) P15[0]
(MHZ XTAL: XI, GPIO) P15[1]
(IDAC1, GPIO) P3[0]
(IDAC3, GPIO) P3[1]
(OpAmp3-/Extref1, GPIO) P3[2]
(Opamp3+, GPIO) P3[3]
Opamp(1-, GPIO) P3[4]
(Opamp1+, GPIO) P3[5]
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(Configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
VDDIO1
Notes
7. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
8. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
9. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
10. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Page 7 of 137
TQFP
77
76
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO, Opamp2-)
P0[4] (GPIO, Opamp2+)
87
86
85
84
83
82
81
80
79
78
90
89
88
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
VDDD
VSSD
VCCD
P4[7] (GPIO)
P4[6] (GPIO)
98
97
96
95
94
93
92
91
Lines show VDDIO
to I/O supply
association
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
VCCA
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO, Opamp3OUT)
P3[6] (GPIO, Opamp1OUT)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDIO0
P0[3] (GPIO, Opamp0-/Extref0)
P0[2] (GPIO, Opamp0+)
P0[1] (GPIO, Opamp0OUT)
P0[0] (GPIO, Opamp2OUT)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
[11]
[11]
54
53
52
51
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDIO1
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P5[5]
(GPIO) P5[6]
(GPIO) P5[7]
(USBIO, D+, SWDIO) P15[6]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(Configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(nTRST, GPIO) P1[5]
100
99
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
Figure 2-7 and Figure 2-8 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
performance on a two-layer board.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-7 and Power System on
page 30. The trace between the two VCCD pins should be as short as possible.
For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC 3 and PSoC 5.
Note
11. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Page 8 of 137
VDDD
C1
1 UF
VDDD
C2
0.1 UF
VSSD
C8
0.1 UF
VSSD
VSSD
VDDA
VSSA
VCCA
VSSD
C17
1 UF
VSSA
VDDA
C9
1 UF
C10
0.1 UF
VSSA
VDDIO3
VDDD
VDDD
VSSD
C11
0.1 UF
C12
0.1 UF
VCCD
VDDD
VDDA
VDDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P3[5], OA1+
VDDIO0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
OA1OUT, P3[6]
VDDIO1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
USB D+, P15[6]
USB D-, P15[7]
VDDD
VSSD
VCCD
NC
NC
P15[0], MHZXOUT
P15[1], MHZXIN
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1-
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWDIO, TMS
P1[1], SWDCK, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSD
1
2
3
4
5
6
7
8
9
10
11
12
13
VSSD 14
15
16
17
18
19
20
21
22
23
24
25
VSSD
VSSD
VDDIO2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
VDDD
VSSD
VCCD
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+, P0[4]
VSSD
VDDD
100
99
98
97
96
95
94
93
92
91
90
89
88 VDDD
VSSD
87
86
85
84
83
82
81
80
79
78
77
76
VCCD
C6
0.1 UF
C15
1 UF
C16
0.1 UF
VSSD
VSSD
Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-8 on page 10.
Page 9 of 137
VSSD
VDDA
VSSA
Plane
VSSD
Plane
3. Pin Descriptions
IDAC0, IDAC1, IDAC2, IDAC3
Low resistance output pin for high current DACs (IDAC).
Opamp0OUT, Opamp1OUT, Opamp2OUT, Opamp3OUT
High current output of uncommitted opamp[12].
Extref0, Extref1
SIO
SWDCK
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense[12].
I2C0: SCL, I2C1: SCL
I2C SCL line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SCL if wake from sleep is not
required.
TCK
I2C
TDI
JTAG test data in programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
Note
12. GPIOs with opamp outputs are not recommended for use with CapSense.
Page 10 of 137
Supply for I/O pins. Each VDDIO must be tied to a valid operating
voltage (1.71 V to 5.5 V), and must be less than or equal to
VDDA.
USBIO, D+
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin; it is powered from VDDD instead of from a
VDDIO. Pins are Do Not Use (DNU) on devices without USB.
USBIO, D
4. CPU
VBOOST
The CY8C38 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C38 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 33 MIPS with an average of 2 cycles per
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
VBAT
Battery supply to boost pump.
VCCA.
Output of the analog core regulator or the input to the
analog core. Requires a 1uF capacitor to VSSA. The regulator
output is not designed to drive external circuits. Note that if you
use the device with an external core regulator (externally
regulated mode), the voltage applied to this pin must not
exceed the allowable range of 1.71 V to 1.89 V. When using
the internal core regulator, (internally regulated mode, the
default), do not tie any power to this pin. For details see Power
System on page 30.
to 8 KB of SRAM
VCCD.
DMA controller
VDDA
Supply for all analog peripherals and analog core regulator.
VDDA must be the highest voltage present on the device. All
other supply pins must be less than or equal to VDDA.
VDDD
Supply for all digital peripherals and digital core regulator. VDDD
must be less than or equal to VDDA.
VSSA
Ground for all analog peripherals.
VSSB
Ground connection for boost pump.
VSSD
Ground for all digital logic and I/O pins.
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
for a read of the program memory. This mode uses the Data
Pointer as the base and the accumulator value as an offset to
read a program memory.
Page 11 of 137
Arithmetic instructions
Logical instructions
Cycles
ADD
A,Rn
Mnemonic
Description
ADD
A,Direct
ADD
A,@Ri
ADD
A,#data
ADDC A,Rn
ADDC A,Direct
ADDC A,@Ri
ADDC A,#data
SUBB A,Rn
SUBB A,Direct
SUBB A,@Ri
SUBB A,#data
INC
Increment accumulator
INC
Rn
Increment register
INC
Direct
INC
@Ri
DEC
Decrement accumulator
DEC
Rn
Decrement register
DEC
Direct
DEC
@Ri
INC
DPTR
MUL
DIV
Divide accumulator by B
DAA
Page 12 of 137
Description
Bytes
Cycles
ANL
A,Rn
ANL
A,Direct
ANL
A,@Ri
ANL
A,#data
ANL
Direct, A
ANL
Direct, #data
ORL
A,Rn
OR register to accumulator
ORL
A,Direct
ORL
A,@Ri
ORL
A,#data
ORL
Direct, A
ORL
Direct, #data
XRL
A,Rn
XRL
A,Direct
XRL
A,@Ri
XRL
A,#data
XRL
Direct, A
XRL
Direct, #data
CLR
Clear accumulator
CPL
Complement accumulator
RL
RLC
RR
RRC A
SWAP A
A,Rn
Description
Move register to accumulator
Bytes
Cycles
Page 13 of 137
Cycles
MOV
A,Direct
Mnemonic
Description
MOV
A,@Ri
MOV
A,#data
MOV
Rn,A
MOV
Rn,Direct
MOV
Rn, #data
MOV
Direct, A
MOV
Direct, Rn
MOV
Direct, Direct
MOV
Direct, @Ri
MOV
Direct, #data
MOV
@Ri, A
MOV
@Ri, Direct
MOV
@Ri, #data
MOV
DPTR, #data16
MOVC A, @A+DPTR
MOVC A, @A + PC
MOVX A,@Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
PUSH Direct
POP
Direct
XCH
A, Rn
XCH
A, Direct
XCH
A, @Ri
Bytes
Cycles
XCHD A, @Ri
Description
CLR
Clear carry
CLR
bit
SETB C
Set carry
SETB bit
CPL
Complement carry
CPL
bit
ANL
C, bit
ANL
C, /bit
ORL C, bit
Page 14 of 137
Cycles
ORL C, /bit
Mnemonic
MOV C, bit
MOV bit, C
JC
rel
Description
JNC rel
JB
bit, rel
Page 15 of 137
Description
Bytes
Cycles
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
Absolute jump
LJMP addr16
Long jump
SJMP rel
JMP @A + DPTR
JZ rel
JNZ rel
DJNZ Rn,rel
NOP
No operation
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
CPU and DMA controller are both bus masters to the PHUB
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
router
peripherals
peripheral access
different spokes
on different spokes
Peripherals
SRAM
DFB
UDBs group 1
UDBs group 2
Page 16 of 137
% Bus Bandwidth
100.0
100.0
50.0
25.0
12.5
6.2
3.1
1.5
DATA Phase
ADDRESS Phase
CLK
ADDR 16/32
DATA Phase
CLK
ADDR 16/32
WRITE
WRITE
DATA (A)
DATA
READY
DATA
DATA (A)
READY
Basic DMA Read Transfer without wait states
Page 17 of 137
vector addresses
priorities
Page 18 of 137
10
11
S
CLK
Arrival of new Interrupt
INT_INPUT
S
Pend bit is set on next clock active edge
PEND
S
Interrupt request sent to core for processing
IRQ
ACTIVE_INT_NUM
(#10)
NA
NA
INT_VECT_ADDR
0x0010
S
S
0x0000
S
S
NA
IRA
IRC
Interrupt generation and posting to CPU
CPU Response
Int. State
Clear
S
Completing current instruction and branching to vector address
TIME
Notes
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
= 12 cycles
Page 19 of 137
Highest Priority
Interrupt Enable/
Disable, PEND and
POST logic
Interrupts 0 to 31
from UDBs
Interrupts 0 to 31
from Fixed
Function Blocks
IRQ
8 Level
Priority
decoder
for all
interrupts
Polling sequence
Interrupt
routing logic
to select 32
sources
Interrupt 2 to 30
Interrupts 0 to
31 from DMA
Individual
Enable Disable
bits
0 to 31
ACTIVE_INT_NUM
[15:0]
INT_VECT_ADDR
IRA
IRC
31
Global Enable
disable bit
Lowest Priority
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source.
Fixed function interrupts and all interrupt sources may be routed
to any interrupt vector using the UDB interrupt source
connections.
Page 20 of 137
Fixed Function
DMA
UDB
LVD
phub_termout0[0]
udb_intr[0]
Cache/ECC
phub_termout0[1]
udb_intr[1]
Reserved
phub_termout0[2]
udb_intr[2]
phub_termout0[3]
udb_intr[3]
PICU[0]
phub_termout0[4]
udb_intr[4]
PICU[1]
phub_termout0[5]
udb_intr[5]
PICU[2]
phub_termout0[6]
udb_intr[6]
PICU[3]
phub_termout0[7]
udb_intr[7]
PICU[4]
phub_termout0[8]
udb_intr[8]
PICU[5]
phub_termout0[9]
udb_intr[9]
10
PICU[6]
phub_termout0[10]
udb_intr[10]
11
PICU[12]
phub_termout0[11]
udb_intr[11]
12
PICU[15]
phub_termout0[12]
udb_intr[12]
13
Comparators Combined
phub_termout0[13]
udb_intr[13]
14
phub_termout0[14]
udb_intr[14]
phub_termout0[15]
udb_intr[15]
15
I C
16
CAN
phub_termout1[0]
udb_intr[16]
17
Timer/Counter0
phub_termout1[1]
udb_intr[17]
18
Timer/Counter1
phub_termout1[2]
udb_intr[18]
19
Timer/Counter2
phub_termout1[3]
udb_intr[19]
20
Timer/Counter3
phub_termout1[4]
udb_intr[20]
21
phub_termout1[5]
udb_intr[21]
22
phub_termout1[6]
udb_intr[22]
23
phub_termout1[7]
udb_intr[23]
24
USB Endpoint[0]
phub_termout1[8]
udb_intr[24]
25
phub_termout1[9]
udb_intr[25]
26
Reserved
phub_termout1[10]
udb_intr[26]
27
LCD
phub_termout1[11]
udb_intr[27]
28
DFB Int
phub_termout1[12]
udb_intr[28]
29
Decimator Int
phub_termout1[13]
udb_intr[29]
30
phub_termout1[14]
udb_intr[30]
31
phub_termout1[15]
udb_intr[31]
Page 21 of 137
Allowed
Not Allowed
Unprotected
Factory
Upgrade
External read
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress data sheets. Cypress believes that its family
of products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as unbreakable. Cypress is willing to
work with the customer who is concerned about the integrity of
their code. Code protection is constantly evolving. We at Cypress
are committed to continuously improving the code protection
features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte-addressable nonvolatile
memory. The CY8C38 has up to 2 KB of EEPROM memory to
store user data. Reads from EEPROM are random access at the
byte level. Reads are done directly; writes are done by sending
write commands to an EEPROM programming interface. CPU
code execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into 128 rows of 16 bytes each. The CPU
can not execute out of EEPROM. There is no ECC hardware
associated with EEPROM. If ECC is required it must be handled
in firmware.
Page 22 of 137
0x00
PRT3RDM[1:0]
PRT2RDM[1:0]
PRT1RDM[1:0]
PRT0RDM[1:0]
0x01
PRT12RDM[1:0]
PRT6RDM[1:0]
PRT5RDM[1:0]
PRT4RDM[1:0]
0x02
XRESMEN
0x03
PRT15RDM[1:0]
DIG_PHS_DLY[3:0]
ECCEN
DPS[1:0]
CFGSPEED
The details for individual fields and their factory default settings are shown in Table 5-3:.
Table 5-3. Fields and Factory Default Settings
Field
Description
Settings
PRTxRDM[1:0]
Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog
See Reset Configuration on page 41. All pins of the port 01b - high impedance digital
are set to the same mode.
10b - resistive pull up
11b - resistive pull down
XRESMEN
CFGSPEED
DPS{1:0]
ECCEN
Controls whether ECC flash is used for ECC or for general 0 (default) - ECC disabled
configuration and data storage. See Flash Program
1 - ECC enabled
Memory on page 22.
DIG_PHS_DLY[3:0]
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited
see Nonvolatile Latches (NVL)) on page 110.
Page 23 of 137
Address Signals
Data Signals
Control Signals
I/O
PORTs
Data,
Address,
and Control
Signals
IO IF
PHUB
Data,
Address,
and Control
Signals
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
Page 24 of 137
0x00
0x1F
0x20
The CY8C38 8051 code space is 64 KB. Only main flash exists
in this space. See the Flash Program Memory on page 22.
0x2F
0x7F
0x80
Bit-Addressable Area
0x30
0xFF
SFR
Special Function Registers
(direct addressing)
0/8
SFRPRT15DR
1/9
SFRPRT15PS
2/A
SFRPRT15SEL
3/B
4/C
5/D
6/E
7/F
0F0
SFRPRT12SEL
0E8
SFRPRT12DR
SFRPRT12PS
MXAX
0E0
ACC
0D8
SFRPRT6DR
SFRPRT6PS
SFRPRT6SEL
0D0
PSW
0C8
SFRPRT5DR
SFRPRT5PS
SFRPRT5SEL
0C0
SFRPRT4DR
SFRPRT4PS
SFRPRT4SEL
0B8
0B0
SFRPRT3DR
SFRPRT3PS
SFRPRT3SEL
0A8
IE
0A0
P2AX
SFRPRT1SEL
098
SFRPRT2DR
SFRPRT2PS
SFRPRT2SEL
090
SFRPRT1DR
SFRPRT1PS
DPX0
DPX1
088
SFRPRT0PS
SFRPRT0SEL
080
SFRPRT0DR
SP
DPL0
DPH0
DPL1
DPH1
DPS
The CY8C38 family provides the standard set of registers found on industry standard 8051 devices. In addition, the CY8C38 devices
add SFRs to provide direct access to the I/O ports on the device. The following sections describe the SFRs added to the CY8C38
family.
Page 25 of 137
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A+DPTR
JMP @A+DPTR
INC DPTR
MOV DPTR, #data16
SRAM
Power management
Interrupt controller
Cache controller
I2C controller
Decimator
Fixed timer/counter/PWMs
USB controller
UDB configuration
PHUB configuration
EEPROM
CAN
DFB
Digital Interconnect
configuration
Debug controller
Purpose
Page 26 of 137
6. System Integration
Fmin
Tolerance at Fmin
Fmax
Tolerance at Fmax
Startup Time
IMO
3 MHz
62 MHz
7%
13 s max
MHzECO
4 MHz
Crystal dependent
25 MHz
Crystal dependent
DSI
0 MHz
Input dependent
66 MHz
Input dependent
Input dependent
PLL
24 MHz
Input dependent
67 MHz
Input dependent
250 s max
Doubler
48 MHz
Input dependent
48 MHz
Input dependent
1 s max
ILO
1 kHz
50%, +100%
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
Page 27 of 137
4-25 MHz
ECO
External IO
or DSI
0-66 MHz
32 kHz ECO
1,33,100 kHz
ILO
CPU
Clock
24-67 MHz
PLL
Master
Mux
Bus
Clock
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low-power modes.
6.1.1.4 Internal Low-Speed Oscillator
The ILO provides clock frequencies for low-power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz. The 1-kHz clock (CLK1K) is typically used for a
background heartbeat timer. This clock inherently lends itself to
low-power supervisory operations such as the watchdog timer
and long sleep intervals using the central timewheel (CTW).
The central timewheel is a 1-kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled,
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a
low-power mode. Firmware can reset the central timewheel.
Systems that require accurate timing should use the RTC
capability instead of the central timewheel.
The 100-kHz clock (CLK100K) can be used as a low power
master clock. It can also generate time intervals using the fast
timewheel.
The fast timewheel is a 5-bit counter, clocked by the 100-kHz
clock. It features programmable settings and automatically
resets when the terminal count is reached. An optional interrupt
can be generated each time the terminal count is reached. This
enables flexible, periodic interrupts of the CPU at a higher rate
than is allowed using the central timewheel.
The 33-kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768-kHz ECO clock with no need for a crystal.
Page 28 of 137
4 - 25 MHz
Crystal Osc
XCLK_MHZ
4 25 MHz
crystal
External
Components
Xo
(Pin P15[0])
Xi
(Pin P15[1])
Capacitors
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
designs requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
The master clock is used to select and supply the fastest clock
Bus clock 16-bit divider uses the master clock to generate the
32 kHz
Crystal Osc
Xi
(Pin P15[3])
External
Components
XCLK32K
Xo
(Pin P15[2])
32 kHz
crystal
Capacitors
bus clock used for data transfers. Bus clock is the source clock
for the CPU clock divider.
Four 16-bit clock dividers generate clocks for the analog system
1 F
VDDIO2
VDDD
I/O Supply
VSSD
VCCD
VDDIO 2
VDDIO0
0.1 F
0.1 F
I/O Supply
VDDIO0
0.1 F
I2C
Regulator
Sleep
Regulator
Digital
Domain
VDDA
VDDA
VCCA
Analog
Regulator
Digital
Regulators
VSSB
0.1 F
1 F
VSSA
Analog
Domain
0.1 F
I/O Supply
VDDIO3
VDDD
VSSD
I/O Supply
VCCD
VDDIO1
Hibernate
Regulator
0.1 F
0.1 F
VDDIO1
VDDD
VDDIO3
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-8 on page 10.
You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal
regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins to the VCCx
pins.
You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration,
the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in
this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be
disabled to reduce power consumption.
Page 30 of 137
Hibernate
Sleep
Manual register
All subsystems automatically
entry
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
Hibernate
Comparator,
ILO/kHzECO
PICU, I2C, RTC,
CTW, LVD
PICU
Wakeup
Time
Current
(typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup Sources
Reset
Sources
1.2 mA[13]
Yes
All
All
All
All
User
defined
All
All
All
All
<15 s
1 A
No
I2C
Comparator
ILO/kHzECO
Comparator,
PICU, I2C, RTC,
CTW, LVD
XRES, LVD,
WDR
200 nA
No
None
None
None
PICU
XRES
Hibernate <100 s
Note
13. Bus clock off. Execute from cache at 6 MHz. See Table 11-2 on page 71.
Page 31 of 137
Manual
Sleep
Hibernate
Alternate
Active
IND
PSoC
22 F 0.1 F
10 H
22 F
VBAT
VSSB
VSSA
VSSD
Page 32 of 137
6.3 Reset
CY8C38 has multiple internal and external reset sources
available. The reset sources are:
Power source monitoring The analog and digital power
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must
all have voltage applied before the part comes out of reset.
Power
Voltage
Level
Monitors
Reset
Pin
External
Reset
Processor
Interrupt
Reset
Controller
System
Reset
Watchdog
Timer
Software
Reset
Register
Interrupt Supply
DLVI
ALVI
AHVI
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wakeup
sequence. The interrupt is then recognized and may be
serviced.
Page 34 of 137
Note
14. GPIOs with opamp outputs are not recommended for use with CapSense.
Page 35 of 137
Naming Convention
x = Port Number
y = Pin Number
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Vddio Vddio
PRT[x]DR
In
Vddio
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Analog
Slew
Cntl
PIN
OE
0
1
0
1
CAPS[x]CFG1
Switches
PRT[x]AG
Analog Global
PRT[x]AMUX
Analog Mux
LCD
Display
Data
PRT[x]LCD_COM_SEG
PRT[x]LCD_EN
LCD Bias Bus
Page 36 of 137
Naming Convention
x = Port Number
y = Pin Number
Buffer
Thresholds
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Driver
Vhigh
In
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Slew
Cntl
PIN
OE
Naming Convention
y = Pin Number
Interrupt
Logic
USB or I/O
USBIO_CR1[2]
Vddd
In
Drive
Logic
D+ Open
Drain
PRT[15]DM0[7]
D- Open
Drain
PRT[15]DM1[7]
PRT[15]DM0[6]
PRT[15]DM1[6]
D+ pin only
D+ 1.5 k
Vddd
5k
Vddd Vddd
1.5 k
PIN
D+ 5 k
D- 5 k
Page 37 of 137
DR
PS
0.
Pin
High Impedance
Analog
DR
PS
Pin
1. High Impedance
Digital
DR
PS
Pin
2. Resistive
Pull-Up
Vddio
DR
PS
Pin
4. Open Drain,
Drives Low
DR
PS
Vddio
DR
PS
Pin
3. Resistive
Pull-Down
Vddio
Pin
5. Open Drain,
Drives High
DR
PS
Vddio
Pin
6. Strong Drive
DR
PS
Pin
7. Resistive
Pull-Up and Pull-Down
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
PRTxDR = 0
Drive Mode
High Z
High Z
High Z
High Z
Resistive pull-up[15]
Strong Low
Resistive pull-down[15]
Strong High
High Z
Strong Low
Strong High
High Z
Strong drive
Strong High
Strong Low
Note
15. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
Page 38 of 137
PRT15.DM0[7,6]
Drive Mode enable
High Z
Strong Low
Strong High
Strong Low
Strong Outputs
Strong Low
Strong High
Strong Low
Strong Outputs
PRT15.DR[7,6] = 1
PRT15.DR[7,6] = 0
Description
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/Os digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
The input buffer is enabled for digital signal input. This is the
standard high impedance (High Z) state recommended for
digital inputs.
Resistive pull-up or resistive pull-down
All I/O registers are available in the standard port form, where
each bit of the register corresponds to one of the port pins. This
register form is efficient for quickly reconfiguring multiple port
pins at the same time.
Page 39 of 137
6.4.9 CapSense
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders[16]. See the
CapSense section on page 63 for more information.
Note
16. GPIOs with opamp outputs are not recommended for use with CapSense.
Page 40 of 137
high impedance load to the external circuit where VDDIO < VIN <
5.5 V.
The GPIO pins must be limited to 100 A using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the VDDIO supply where VDDIO < VIN < VDDA.
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the VDDIO supply
voltage to which the GPIO belongs.
Input Path
Digital
Input
Vinref
Reference
Generator
SIO_Ref
PIN
Voutref
Output Path
Driver
Vhigh
Digital
Output
Drive
Logic
Page 41 of 137
I2C
UART
SPI
Functions
EMIF
PWMs
Timers
Counters
Logic
NOT
OR
XOR
AND
7.1.2 Example Analog Components
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB Array
Amplifiers
IO Port
UDB Array
IO Port
IO Port
IO Port
TIA
PGA
opamp
ADC
Delta-sigma
DACs
Current
Voltage
PWM
Comparators
Mixers
Page 42 of 137
LCD control
Filters
Page 43 of 137
Page 44 of 137
PLD
Chaining
Clock
and Reset
Control
Status and
Control
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
Datapath
Datapath
Chaining
Routing Channel
Page 45 of 137
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PLD blocks There are two small PLDs per UDB. These blocks
IN0
TC
TC
TC
TC
TC
TC
TC
TC
IN1
TC
TC
TC
TC
TC
TC
TC
TC
IN2
TC
TC
TC
TC
TC
TC
TC
TC
IN3
TC
TC
TC
TC
TC
TC
TC
TC
IN4
TC
TC
TC
TC
TC
TC
TC
TC
IN5
TC
TC
TC
TC
TC
TC
TC
TC
IN6
TC
TC
TC
TC
TC
TC
TC
TC
IN7
TC
TC
TC
TC
TC
TC
TC
TC
IN8
TC
TC
TC
TC
TC
TC
TC
TC
IN9
TC
TC
TC
TC
TC
TC
TC
TC
IN10
TC
TC
TC
TC
TC
TC
TC
TC
IN11
TC
TC
TC
TC
TC
TC
TC
TC
AND
Array
SELIN
(carry in)
Clock and reset module This block provides the UDB clocks
OUT0
MC0
OUT1
MC1
OUT2
MC2
OUT3
MC3
SELOUT
(carry out)
OR
Array
One 12C4 PLD block is shown in Figure 7-7. This PLD has 12
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
Page 46 of 137
F0
A0
A1
D0
D1
D1
Data Registers
D0
To/From
Previous
Datapath
A1
Conditions: 2 Compares,
2 Zero Detect, 2 Ones
Detect Overflow Detect
Datapath Control
Input from
Programmable
Routing
Input
Muxes
FIFOs
Chaining
Output
Muxes
6
Output to
Programmable
Routing
To/From
Next
Datapath
Accumulators
A0
PI
Parallel Input/Output
(To/From Programmable Routing)
PO
ALU
Shift
Mask
Function
Description
A0 and A1 Accumulators
ALU
F0 and F1 FIFOs
Increment
Page 47 of 137
7.2.2.7 Chaining
Shift left
Shift right
Nibble swap
Bitwise OR mask
7.2.2.3 Conditionals
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These
conditions are the primary datapath outputs, a selection of which
can be driven out to the UDB routing matrix. Conditional
computation can use the built in chaining to neighboring UDBs
to operate on wider data widths without the need to use routing
resources.
7.2.2.4 Variable MSB
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.5 Built in CRC/PRS
The datapath has built-in support for single cycle CRC
computation and PRS generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be
implemented in conjunction with PLD logic, or built in chaining
may be use to extend the function into neighboring UDBs.
System Bus
F0
D0/D1
A0/A1/ALU
A0/A1/ALU
A0/A1/ALU
F1
F0
F1
System Bus
System Bus
TX/RX
Dual Capture
F0
F1
D0
A0
D1
A1
Dual Buffer
Routing Channel
Page 48 of 137
An example of this is the 8-bit timer in the upper left corner of the
array. This function only requires one datapath in the UDB, and
therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
Figure 7-12. Function Mapping Example in a Bank of UDBs
8-Bit
Timer
Quadrature Decoder
UDB
UDB
HV
A
16-Bit
PWM
16-Bit PYRS
UDB
HV
B
UDB
HV
A
UDB
UDB
Sequencer
UDB
8-Bit
Timer Logic
UDB
8-Bit SPI
I2C Slave
System Connections
12-Bit SPI
UDB
HV
B
HV
A
HV
B
UDB
UDB
UDB
UDB
UDB
HV
A
HV
B
UDB
HV
B
HV
A
HV
B
HV
A
UDB
Logic
HV
A
HV
B
HV
A
HV
B
UDB
UDB
UART
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
12-Bit PWM
UDB
HV
A
UDB
HV
A
HV
B
UDB
HV
B
HV
A
HV
B
UDB
HV
A
System Connections
Page 49 of 137
CAN
Interrupt
Controller
I2C
DMA
Controller
IO Port
Pins
Global
Clocks
DO
UDB ARRAY
DI
Global
Clocks
IO Port
Pins
EMIF
Del-Sig
SC/CT
Blocks
DACs
Comparators
DO
PIN 0
DO
PIN1
DO
PIN2
0
1
IRQs
UDB Array
2
Edge
Detect
Interrupt
Controller
DO
PIN4
DO
PIN5
DO
PIN6
DO
PIN7
Port i
DO
PIN3
DRQs
DMA termout (IRQs)
1
Edge
Detect
DMA
Controller
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
Page 50 of 137
CAN Node 2
CAN Node n
PSoC
CAN
Drivers
CAN Controller
En
Tx Rx
CAN Transceiver
CAN_H
CAN_L
CAN_H
CAN_L
CAN_H
CAN_L
CAN Bus
Rx pin
Receive path
Transmit path
Page 51 of 137
TxMessage0
TxReq
TxAbort
Tx Buffer
Status
TxReq
Pending
TxMessage1
TxReq
TxAbort
Bit Timing
Priority
Arbiter
TxMessage6
TxReq
TxAbort
TxInterrupt
Request
(if enabled)
TxMessage7
TxReq
TxAbort
RxInterrupt
Request
(if enabled)
RxMessage0
Acceptance Code 0
Acceptance Mask 0
RxMessage1
Acceptance Code 1
Acceptance Mask 1
RxMessage
Handler
RxMessage14
Acceptance Code 14
Acceptance Mask 14
RxMessage15
Acceptance Code 15
Acceptance Mask 15
ErrInterrupt
Request
(if enabled)
Tx
CRC
Generator
Error Status
Error Active
Error Passive
Bus Off
Tx Error Counter
Rx Error Counter
RTR RxMessages
0-15
Rx Buffer
Status
RxMessage
Available
Tx
CAN
Framer
Rx
CAN
Framer
Rx
CRC Check
Error Detection
CRC
Form
ACK
Bit Stuffing
Bit Error
Overload
Arbitration
WakeUp
Request
Page 52 of 137
System Bus
Arbiter
512 X 8
SRAM
D+
SIE
(Serial Interface
Engine)
USB
I/O
Interrupts
48 MHz
IMO
External 22
Resistors
Clock
Reset
Enable
Capture
Kill
Timer / Counter /
PWM 16-bit
IRQ
TC / Compare!
Compare
Page 53 of 137
SDA
1-7
SCL
START
Condition
ADDRESS
R/W
ACK
1-7
DATA
ACK
1-7
DATA
ACK
STOP
Condition
Note
17. Fixed-block I2C does not support undefined bus conditions. These conditions should be avoided, or the UDB-based I2C component should be used instead.
Page 54 of 137
The typical use model is for data to be supplied to the DFB over
the system bus from another on-chip system data source such
as an ADC. The data typically passes through main memory or
is directly transferred from another chip resource through DMA.
The DFB processes this data and passes the result to another
on chip resource such as a DAC or main memory through DMA
on the system bus.
Data movement in or out of the DFB is typically controlled by the
system DMA controller but can be moved directly by the MCU.
8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
Flexible, configurable analog routing architecture provided by
output.
outputs.
read_data
Data
Source
(PHUB)
write_data
Digital
Routing
Digital Filter
Block
addr
System
Bus
Data
Dest
(PHUB)
DMA
Request
DMA
CTRL
Page 55 of 137
DAC
DelSig
ADC
DAC
DAC
SC/CT Block
SC/CT Block
SC/CT Block
Comparators
CMP
CMP
CMP
Op
Amp
SC/CT Block
Op
Amp
Op
Amp
R
O
U
T
I
N
G
Precision
Reference
DAC
Op
Amp
GPIO
Port
A
N
A
L
O
G
CMP
A
N
A
L
O
G
GPIO
Port
R
O
U
T
I
N
G
CapSense Subsystem
Config &
Status
Registers
Analog
Interface
DSI
Array
Clock
Distribution
PHUB
CPU
Decimator
8.1.1 Features
Flexible, configurable analog routing architecture
16 analog globals (AG) and two analog mux buses
mux bus
analog blocks
Page 56 of 137
ExVrefL2
opamp2
swinp
01 2 3 4 56 7 0123
3210 76543210
opamp1
swfol
swfol
GPIO
P3[5]
GPIO
swinp P3[4]
GPIO
swinn P3[3]
GPIO
P3[2]
GPIO
P3[1]
GPIO
P3[0]
GPXT
* P15[1]
GPXT
* P15[0]
swinn
swfol
swfol
opamp3
swinn
*
refbufl_
cmp
vref_cmp1
(0.256V)
+
- comp2
bg_vda_swabusl0
CAPSENSE
out
ref
in refbufl
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
refsel[1:0]
sc0
Vin
Vref
out
vssa
sc0_bgref
(1.024V)
sc2_bgref
(1.024V)
refbufr
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
refsel[1:0]
sc1
Vin
Vref
out
SC/CT
Vin
Vref
out
sc2
out
ref
in
Vssa
sc1_bgref
(1.024V)
sc3_bgref
(1.024V)
Vin
Vref
out
sc3
ABUSL0
ABUSL1
ABUSL2
ABUSL3
v0
DAC0
i0
DAC1
v1
i1
v2
DAC2
i2
DAC3
v3
i3
VIDAC
USB IO
USB IO
* P15[6]
+
DSM0
-
vssa
GPIO
P5[7]
GPIO
P5[6]
GPIO
P5[5]
GPIO
P5[4]
SIO
P12[7]
SIO
P12[6]
GPIO
* P1[7]
GPIO
* P1[6]
DSM
vcm
refs
qtz_ref
vref_vss_ext
dsm0_qtz_vref2 (1.2V)
dsm0_qtz_vref1 (1.024V)
Vdda/3
Vdda/4
ExVrefL
3210 76543210
01 23456 7 0123
*
Vbat
Vssd
Ind
Vssb
Vboost
Switch Resistance
Small ( ~870 Ohms )
GPIO
P5[0]
GPIO
P5[1]
GPIO
P5[2]
GPIO
P5[3]
GPIO
P1[0]
GPIO
P1[1]
GPIO
P1[2]
GPIO
P1[3]
GPIO
P1[4]
GPIO
P1[5]
GPIO
P2[5]
GPIO
P2[6]
GPIO
P2[7]
SIO
P12[4]
SIO
P12[5]
GPIO
P6[4]
GPIO
P6[5]
GPIO
P6[6]
GPIO
P6[7]
Connection
XRES
AMUXBUSL
AGR[3]
AGR[2]
AGR[1]
AGR[0]
AMUXBUSR
Notes:
* Denotes pins on all packages
LCD signals are not shown.
Vddio1
AGL[3]
AGL[2]
AGL[1]
AGL[0]
Mux Group
Switch Group
AGR[0]
LPF
AMUXBUSR
AGR[3]
AGR[2]
AGR[1]
VBE
Vss ref
TS
ADC
AMUXBUSR
ANALOG ANALOG
BUS
GLOBALS
AGL[1]
AGL[2]
AGL[3]
AMUXBUSL
AGL[0]
ANALOG ANALOG
GLOBALS
BUS
AMUXBUSL
ExVrefR
vssd
dsm0_vcm_vref1 (0.8V)
dsm0_vcm_vref2 (0.7V)
Vssd
Vddd
* P15[7]
dac_vref (0.256V)
vcmsel[1:0]
Vccd
ABUSR0
ABUSR1
ABUSR2
ABUSR3
Vddio2
i1
Vddd
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
P15[4]
GPIO
P15[5]
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3] *
GPIO
P2[4] *
+
-
i3
cmp0_vref
(1.024V)
AGR[4]
AMUXBUSR
Vdda
Vdda/2
Vssd
comp3
ExVrefR
cmp1_vref
bg_vda_res_en
Vccd
comp1 +
-
COMPARATOR
cmp_muxvn[1:0]
abuf_vref_int
(1.024V)
swin
AGR[7]
AGR[6]
AGR[5]
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
P4[7]
swout
out1
comp0
+
-
cmp1_vref
cmp0_vref
(1.024V)
in1
out0
swin
i2
LPF
in0
swout
abuf_vref_int
(1.024V)
refbufr_
cmp
i0
cmp1_vref
opamp0
AGL[6]
AGL[7]
AGR[4]
AGR[5]
AGR[6]
AGR[7]
AGL[4]
AGL[5]
ExVrefL
ExVrefL1
AMUXBUSR
AMUXBUSL
AGL[4]
AGL[5]
AGL[6]
AGL[7]
Vddio3
GPIO
P3[6]
GPIO
P3[7]
SIO
P12[0]
SIO
P12[1]
GPIO
P15[2]
GPIO
P15[3]
AMUXBUSL
Vssd
swinp
swinp
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
Vcca
Vssa
Vdda
SIO
P12[2]
SIO
P12[3]
GPIO
P4[0]
GPIO
P4[1]
GPIO
P0[0]
GPIO
P0[1]
GPIO
P0[2]
GPIO
P0[3]
Vddio0
swinn
Rev #60
10-Feb-2012
Page 57 of 137
Input
Buffer
Negative
Input Mux
Delta
Sigma
Modulator
Decimator
12 to 20 Bit
Result
EOC
SOC
Bits
SINAD (dB)
20
187
16
48 k
84
-10
12
192 k
66
-20
384 k
43
-30
100000
frequency Response. dB
-40
-50
-60
-70
-80
-90
-100
10000
100
1,000
10,000
100,000
1,000,000
Input Frequency, Hz
Input frequency, Hz
1000
Continuous
Multi-Sample
100
Multi-SampleTurbo
10
10
12
14
16
Resolution, bits
18
20
22
8.2.2.2 Continuous
8.3 Comparators
Page 59 of 137
From
Analog
Routing
ANAIF
+
comp0
_
+
comp1
+
_
comp3
+
_
From
Analog
Routing
From
Analog
Routing
comp2
LUT0
LUT1
LUT2
LUT3
UDBs
8.3.2 LUT
The CY8C38 family of devices contains four LUTs. The LUT is a
two input, one output lookup table that is driven by any one or
two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
control word is shown in Table 8-2.
Page 60 of 137
Opamp
Analog
Global Bus
VREF
Analog
Internal Bus
GPIO
GPIO
Analog Switch
a) Voltage Follower
Opamp
Vout to Pin
Vin
b) External Uncommitted
Opamp
Opamp
Vout to GPIO
Vp to GPIO
Vn to GPIO
c) Internal Uncommitted
Opamp
Opamp
Vout to Pin
Vp
GPIO Pin
The opamp has three speed modes, slow, medium, and fast. The
slow mode consumes the least amount of quiescent power and
the fast mode consumes the most power. The inputs are able to
swing rail-to-rail. The output swing is capable of rail-to-rail
operation at low current output, within 50 mV of the rails. When
driving high current loads (about 25 mA) the output voltage may
only get within 500 mV of the rails.
Vn
To Internal Signals
The Naked Opamp presents both inputs and the output for
connection to internal or external signals. The opamp has a unity
gain bandwidth greater than 6.0 MHz and output drive current up
to 650 A. This is sufficient for buffering internal signals (such as
DAC outputs) and driving external loads greater than 7.5 kohms.
Page 61 of 137
Bandwidth
6.0 MHz
24
340 kHz
48
220 kHz
50
215 kHz
R fb
I in
Vref
R1
R2
20 k or 40 k
20 k to 980 k
S
Vref
Vin
V out
V ref
The PGA is used in applications where the input signal may not
be large enough to achieve the desired resolution in the ADC, or
dynamic range of another SC/CT block such as a mixer. The gain
is adjustable at runtime, including changing the gain of the PGA
prior to each ADC sample.
8.5.4 TIA
The Transimpedance Amplifier (TIA) converts an internal or
external current to an output voltage. The TIA uses an internal
feedback resistor in a continuous time configuration to convert
input current to output voltage. For an input current Iin, the output
voltage is VREF - Iin x Rfb, where VREF is the value placed on the
non inverting input. The feedback resistor Rfb is programmable
between 20 K and 1 M through a configuration register.
Table 8-4 shows the possible values of Rfb and associated
configuration settings.
Table 8-4. Feedback Resistor Settings
Configuration Word
000b
20
001b
30
010b
40
011b
60
100b
120
101b
250
110b
500
111b
1000
panels
outputs
Page 62 of 137
Global
Clock
UDB
LCD Driver
Block
DMA
PIN
Display
RAM
8.9 DAC
The CY8C38 parts contain up to four Digital to Analog
Convertors (DACs). Each DAC is 8-bit and can be configured for
either voltage or current output. The DACs support CapSense,
power supply regulation, and waveform generation. Each DAC
has the following features:
Adjustable voltage or current output in 255 steps
Monotonic in nature
Page 63 of 137
Reference
Source
source Range
1x ,8x ,64x
Vout
Scaler
3R
Iout
I sink Range
1x ,8x ,64x
C2 = 1.7 pF
C1 = 850 fF
Rmix 0 20 k or 40 k
sc_clk
Rmix 0 20 k or 40 k
Vin
Vout
Vref
sc_clk
Vi
C1
C2
V ref
V out
1
2
V ref
2
C3
C4
Vref
Page 64 of 137
JTAG
4 or 5
SWD
SWV
SWD + SWV
Page 65 of 137
Host Programmer
PSoC 3
VDD
VDDD,VDDA,VDDIO0,VDDIO1,VDDIO2,VDDIO3 1, 2, 3, 4
TCK
TCK(P1[1]
TMS5
TMS(P1[0])5
TDO
TDI (P1[4])
TDI
TDO (P1[3])
nTRST6
nTRST (P1[5]) 6
XRES
XRESorP1[2]4,7
GND
VSSD,VSSA
GND
The voltage levels of Host Programmer and the PSoC 3 voltage domains involved in Programming should be same. The
Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by VDDIO1. So, VDDIO1 of PSoC 3 should be at same voltage
level as host VDD. Rest of PSoC 3 voltage domains (VDDD,VDDA,VDDIO0,VDDIO2,VDDIO3) need not be at the same voltage level as
host Programmer.
Vdda must be greater than or equal to all other power supplies (Vddd, Vddios) in PSoC 3.
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddios) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by
using the TMS,TCK,TDI, TDO pins of PSoC 3, and writing to a specific register. But this requires that the DPS setting in
NVL is not equal to Debug Ports Disabled.
By default, PSoC 3 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is
unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD
Protocol has to be used for acquiring the PSoC 3 device initially. After switching from SWD to JTAG mode, the TMS pin
will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.
nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 3 as
the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.
If XRES pin is used by host, P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES
pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-pin
devices, but use dedicated XRES pin for rest of devices.
Page 66 of 137
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 s (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined sequence of 1s and 0s.
SWD is used for debugging or for programming the flash
memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
Host Programmer
VDDD,VDDA,VDDIO0,VDDIO1,VDDIO2,VDDIO3 1, 2, 3
VDD
SWDCK
SWDCK(P1[1]orP15[7])
SWDIO
SWDIO(P1[0]orP15[6])
XRESorP1[2]3,4
XRES
GND
PSoC 3
GND
VSSD,VSSA
The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming
should be the same. XRES pin (XRES_N or P1[2]) is powered by VDDIO1. The USB SWD pins are
powered by VDDD. So for Programming using the USB SWD pins with XRES pin, the VDDD, VDDIO1of
PSoC 3 should be at the same voltage level as Host VDD. Rest of PSoC 3 voltage domains (VDDA,VDDIO0,
VDDIO2,VDDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are
powered by VDDIO1. So VDDIO1 of PSoC 3 should be at same voltage level as host VDD for Port 1 SWD
programming. Rest of PSoC 3 voltage domains (VDDD,VDDA,VDDIO0,VDDIO2,VDDIO3) need not be at the same
voltage level as host Programmer.
2
Vdda must be greater than or equal to all other power supplies (Vddd, Vddios) in PSoC 3.
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddios) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For
devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48pin devices, but use dedicated XRES pin for rest of devices.
Page 67 of 137
Page 68 of 137
10.1 Documentation
A suite of documentation, supports the CY8C38 family to ensure
that you can find answers to your questions quickly. This section
contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component data sheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
10.2 Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging
interfaces, the CY8C38 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Page 69 of 137
Description
Conditions
Min
Typ
Max
Units
55
25
100
0.5
VDDD
0.5
VDDIO
0.5
VCCA
0.5
1.95
VCCD
0.5
1.95
VSSA
VSSD 0.5
VSSD +
0.5
VGPIO[18]
VSSD 0.5
VDDIO +
0.5
VSIO
Output disabled
VSSD 0.5
Output enabled
VSSD 0.5
TSTG
Storage temperature
VDDA
VIND
VBAT
0.5
5.5
VSSD 0.5
5.5
IVDDIO
100
mA
IGPIO
GPIO current
30
41
mA
ISIO
SIO current
49
28
mA
IUSBIO
USBIO current
56
59
mA
VEXTREF
LU
Latch up current[19]
ESDHBM
ESDCDM
140
140
mA
2200
750
500
Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to
maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above
normal operating conditions the device may not operate to specification.
Notes
18. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin VDDIO VDDA.
19. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.
Page 70 of 137
[20][21]
Description
Conditions
Min
Typ[22] Max
Units
Active Mode
Only IMO and CPU clock enabled. CPU executing VDDX = 2.7 V 5.5 V; T = 40 C
simple loop from instruction buffer.
FCPU = 6 MHz
T = 25 C
1.2
2.9
1.2
3.1
T = 85 C
4.9
7.7
1.3
2.9
1.6
3.2
T = 85 C
4.8
7.5
2.1
3.7
2.3
3.9
T = 85 C
5.6
8.5
3.5
5.2
3.8
5.5
T = 85 C
7.1
9.8
6.3
8.1
6.6
8.3
T = 85 C
10
13
11.5
13.5
12
14
T = 85 C
15.5
18.5
16
18
16
18
T = 85 C
19.5
23
mA
Notes
20. Total current for all power domains: digital (IDDD), analog (IDDA), and I/Os (IDDIO0, 1, 2, 3). Boost not included. All I/Os floating.
21. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To estimate total current, find the CPU current at the frequency of interest and add peripheral currents for your
particular system from the device datasheet and component datasheets.
22. VDDX = 3.3 V.
Page 71 of 137
Description
Conditions
Min
Typ[22] Max
Units
[23]
Sleep Mode
CPU = OFF
RTC = ON (= ECO32K ON, in low-power mode)
Sleep timer = ON (= ILO ON at 1 kHz)[24]
WDT = OFF
I2C Wake = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated output
mode
VDD = VDDIO =
4.5 V - 5.5 V
1.1
2.3
T = 25 C
1.1
2.2
T = 85 C
15
30
T = 40 C
2.2
T = 25 C
2.1
T = 85 C
12
28
T = 25 C
2.2
4.2
VDD = VDDIO =
Comparator = ON
2.7 V 3.6 V
CPU = OFF
RTC = OFF
Sleep timer = OFF
WDT = OFF
I2C Wake = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated output
mode
T = 25 C
2.2
2.7
VDD = VDDIO =
I2C Wake = ON
CPU = OFF
2.7 V 3.6 V
RTC = OFF
Sleep timer = OFF
WDT = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated output
mode
T = 25 C
2.2
2.8
VDD = VDDIO =
4.5 V - 5.5 V
T = 40 C
0.2
0.6
T = 25 C
0.5
0.6
T = 85 C
4.1
5.3
VDD = VDDIO =
2.7 V 3.6 V
T = 40 C
0.2
0.6
T = 25 C
0.2
0.4
T = 85 C
3.2
4.2
T = 40 C
0.2
0.6
T = 25 C
0.3
0.4
T = 85 C
3.3
4.3
VDD = VDDIO =
2.7 V 3.6 V
VDD = VDDIO =
1.71 V 1.95 V[25]
T = 40 C
Hibernate Mode[23]
Hibernate mode current
All regulators and oscillators off
SRAM retention
GPIO interrupts are active
Boost = OFF
SIO pins in single ended input, unregulated output
mode
VDD = VDDIO =
1.71 V 1.95 V[25]
Notes
23. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV.
24. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
25. Externally regulated mode.
Page 72 of 137
Page 73 of 137
Description
Conditions
Min
Typ
Max
Units
FCPU
CPU frequency
DC
67.01
MHz
FBUSCLK
Bus frequency
DC
67.01
MHz
Svdd
0.066
V/s
TIO_INIT
10
TSTARTUP
33
66
15
THIBERNATE
100
Vdd Voltage
5.5 V
3.3 V
1.71 V
1 MHz
10 MHz
67 MHz
CPU Frequency
Note
26. Based on device characterization (Not production tested).
Page 74 of 137
Conditions
Min
1.8
Typ
1.80
1
Max
5.5
Units
V
V
F
Conditions
Min
1.8
Typ
1.80
1
Max
5.5
Units
V
V
F
Page 75 of 137
Description
Min
Typ
Max
Units
Input voltage
Includes startup
T=-35 C to +65 C
0.5
3.6
0.68
3.6
50
mA
75
mA
30
mA
20
mA
15
mA
700
mA
200
12
1.8 V
1.71
1.80
1.89
1.9 V
1.81
1.90
2.00
2.0 V
1.90
2.00
2.10
2.4 V
2.28
2.40
2.52
2.7 V
2.57
2.70
2.84
3.0 V
2.85
3.00
3.15
3.3 V
3.14
3.30
3.47
3.6 V
3.42
3.60
3.78
4.75
5.00
5.25
ILPK
IQ
Quiescent current
VOUT
Conditions
5.0 V
RegLOAD
Load regulation
3.8
RegLINE
Line regulation
4.1
Description
Ripple voltage
(peak-to-peak)
Conditions
0.5 V < VBAT < 1.7V, VOUT = 1.8 V,
FSW = 400 kHz, IOUT = 10 mA
Min
Typ
Max
100
Units
mV
Notes
27. For output voltages above 3.6 V, an external diode is required.
28. Maximum output current applies for output voltages 4x input voltage.
29. Based on device characterization (Not production tested).
30. At boost frequency of 400 kHz, VOUT is limited to 4 x VBAT..
Page 76 of 137
Description
Boost inductor
Filter capacitor[31]
External Schottky diode
average forward current
Conditions
VR
Min
10
1
Typ
10
22
Max
47
Units
H
F
A
20
Note
31. Based on device characterization (Not production tested).
Page 77 of 137
Description
Conditions
Min
Typ
Max
Units
0.7 VDDIO
VIH
VIL
0.3 VDDIO
VIH
0.7 VDDIO
VIH
2.0
VIL
0.3 VDDIO
VIL
0.8
VOH
VDDIO 0.6
VDDIO 0.5
0.6
VOL
Rpullup
Pull-up resistor
0.6
3.5
5.6
8.5
3.5
5.6
8.5
25 C, VDDIO = 3.0 V
nA
pF
pF
18
pF
CIN
Input capacitance[32]
value)[32]
VH
40
mV
Idiode
100
Rglobal
25 C, VDDIO = 3.0 V
320
Rmux
25 C, VDDIO = 3.0 V
220
Notes
32. Based on device characterization (Not production tested).
33. For information on designing with PSoC 3 oscillators, refer to the application note, AN54439 - PSoC 3 and PSoC 5 External Oscillator..
Page 78 of 137
Fgpioout
Fgpioin
Description
Rise time in Fast Strong Mode[34]
Fall time in Fast Strong Mode[34]
Rise time in Slow Strong Mode[34]
Fall time in Slow Strong Mode[34]
GPIO output operating frequency
2.7 V < VDDIO < 5.5 V, fast strong drive mode
1.71 V < VDDIO < 2.7 V, fast strong drive mode
3.3 V < VDDIO < 5.5 V, slow strong drive mode
1.71 V < VDDIO < 3.3 V, slow strong drive mode
GPIO input operating frequency
1.71 V < VDDIO < 5.5 V
Conditions
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
Min
Typ
Max
12
12
60
60
Units
ns
ns
ns
ns
33
20
7
3.5
MHz
MHz
MHz
MHz
90/10% VDDIO
66
MHz
Figure 11-14. GPIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-15. GPIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Note
34. Based on device characterization (Not production tested).
Page 79 of 137
Description
Conditions
Min
Typ
Max
Units
5.5
0.5
0.52 VDDIO
VDDIO 1
VDDIO 0.5
GPIO mode
CMOS input
0.7 VDDIO
Hysteresis disabled
SIO_ref + 0.2
Vinmax
Vinref
Voutref
Input voltage high threshold
VIH
GPIO mode
CMOS input
0.3 VDDIO
Hysteresis disabled
SIO_ref 0.2
VDDIO 0.4
IOH = 1 mA
SIO_ref 0.65
SIO_ref + 0.2
IOH = 0.1 mA
SIO_ref 0.3
SIO_ref + 0.2
0.8
Unregulated mode
Regulated
mode[35]
Regulated mode[35]
VOL
0.4
Pull-up resistor
3.5
5.6
8.5
Pull-down resistor
3.5
5.6
8.5
14
nA
CIN
Input Capacitance[36]
VH
Idiode
10
pF
40
mV
Differential mode
35
mV
100
Notes
35. See Figure 6-9 on page 37 and Figure 6-12 on page 41 for more information on SIO reference.
36. Based on device characterization (Not production tested).
Page 80 of 137
Figure 11-18. SIO Output High Voltage and Current, Regulated Mode
Description
Rise time in fast strong mode
(90/10%)[37]
Fall time in fast strong mode
(90/10%)[37]
Rise time in slow strong mode
(90/10%)[37]
Fall time in slow strong mode
(90/10%)[37]
Conditions
Cload = 25 pF, VDDIO = 3.3 V
Min
Typ
Max
12
Units
ns
12
ns
75
ns
60
ns
Note
37. Based on device characterization (Not production tested).
Page 81 of 137
Fsioout
Fsioin
Description
SIO output operating frequency
2.7 V < VDDIO < 5.5 V, Unregulated
output (GPIO) mode, fast strong
drive mode
1.71 V < VDDIO < 2.7 V,
Unregulated output (GPIO) mode,
fast strong drive mode
3.3 V < VDDIO < 5.5 V, Unregulated
output (GPIO) mode, slow strong
drive mode
1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow
strong drive mode
2.7 V < VDDIO < 5.5 V, Regulated
output mode, fast strong drive
mode
1.71 V < VDDIO < 2.7 V, Regulated
output mode, fast strong drive
mode
1.71 V < VDDIO < 5.5 V, Regulated
output mode, slow strong drive
mode
SIO input operating frequency
1.71 V < VDDIO < 5.5 V
Conditions
Min
Typ
Max
Units
33
MHz
16
MHz
MHz
MHz
20
MHz
10
MHz
2.5
MHz
90/10% VDDIO
66
MHz
Figure 11-19. SIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Figure 11-20. SIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Page 82 of 137
Min
Typ
Max
Units
0.900
1.575
Rusba
1.425
3.090
Vohusb
2.8
3.6
Volusb
0.3
Vihgpio
VDDD 3 V
0.8
2.4
Rusbi
Description
Conditions
Vilgpio
VDDD 3 V
Vohgpio
Volgpio
0.3
Vdi
|(D+) (D)|
0.2
Vcm
0.8
2.5
0.8
21.78
(1%)
22
22.22
(+1%)
Vse
Rps2
Zo
Including Rext
28
44
CIN
20
pF
IIL[38]
nA
Rext
Note
38. Based on device characterization (Not production tested).
Page 83 of 137
Tf_gpio
Conditions
3 V VDDD 5.5 V
VDDD = 1.71 V
VDDD > 3 V, 25 pF load
VDDD = 1.71 V, 25 pF load
VDDD > 3 V, 25 pF load
VDDD = 1.71 V, 25 pF load
Min
12 0.25%
8
Typ
12
Max
12 + 0.25%
8
Units
MHz
ns
ns
3.5
4
2
3.5
4
5
ns
ns
ns
160
82
175
14
ns
ns
ns
20
6
12
40
12
40
MHz
MHz
ns
ns
ns
ns
Min
90%
Typ
Max
20
20
111%
Units
ns
ns
1.3
Figure 11-23. USBIO Output Rise and Fall Times, GPIO Mode,
VDDD = 3.3 V, 25 pF Load
Conditions
Page 84 of 137
Description
Input voltage high threshold
Input voltage low threshold
Pull-up resistor
Input capacitance[39]
Input voltage hysteresis
(Schmitt-Trigger)[39]
Current through protection diode to VDDIO
and VSSIO
Conditions
Min
0.7 VDDIO
3.5
Typ
5.6
3
100
Max
0.3 VDDIO
8.5
Units
V
V
k
pF
mV
100
Min
1
Typ
Max
Units
s
Conditions
Description
Conditions
Min
Typ
Max
Units
VI
VSSA
VDDA
VOS
2.5
mV
Operating temperature 40 C
to 70 C
mV
TCVOS
30
V/C
Ge1
Rload = 1 k
0.1
CIN
Input capacitance
VO
IOUT
IDD
Quiescent current
CMRR
PSRR
18
pF
VSSA + 0.05
VDDA 0.05
25
mA
16
mA
200
270
uA
250
400
uA
330
950
uA
1000
2500
uA
80
dB
Vdda 2.7 V
85
dB
70
dB
Note
39. Based on device characterization (Not production tested).
Page 85 of 137
Page 86 of 137
SR
en
Description
Gain-bandwidth product
Conditions
Min
Typ
Max
Units
MHz
MHz
MHz
MHz
1.1
V/s
0.9
V/s
V/s
45
nV/sqrtHz
Page 87 of 137
Min
Typ
Max
Units
Resolution
Description
20
bits
No. of
GPIO
No. of
GPIO/2
Monotonic
Yes
Ge
Gain error
0.2
Gd
Gain drift
50
ppm/C
Vos
0.1
mV
TCVos
0.55
V/C
VSSA
VDDA
VSSA
VDDA
VSSA
VDDA 1
Conditions
PSRRb
90
dB
CMRRb
85
dB
INL20
32
LSB
DNL20
LSB
LSB
LSB
LSB
LSB
linearity[40]
INL16
Integral non
DNL16
INL12
Integral non
DNL12
INL8
Integral non
LSB
DNL8
LSB
Rin_Buff
10
74[41]
148[41]
Notes
40. Based on device characterization (not production tested).
41. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to
the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
Page 88 of 137
Description
Conditions
Min
Typ
Max
Units
0.9
1.3
Current Consumption
IDD_20
1.25
mA
IDD_16
48 ksps, unbuffered
1.2
mA
IDD_12
Current consumption, 12
bit[42]
IBUFF
Conditions
1.4
mA
2.5
mA
Min
Typ
Max
4
0.0032
Units
Samples
%
7.8
40
187
sps
Hz
81
11
48
ksps
kHz
dB
84
dB
66
44
192
ksps
kHz
dB
43
88
384
ksps
kHz
dB
Note
42. Based on device characterization (Not production tested).
Page 89 of 137
Multi-Sample
Multi-Sample Turbo
Resolution,
Bits
Min
Max
Min
Max
Min
Max
8000
384000
1911
91701
1829
87771
6400
307200
1543
74024
1489
71441
10
5566
267130
1348
64673
1307
62693
11
4741
227555
1154
55351
1123
53894
12
4000
192000
978
46900
956
45850
13
3283
157538
806
38641
791
37925
14
2783
133565
685
32855
674
32336
15
2371
113777
585
28054
577
27675
16
2000
48000
495
11861
489
11725
17
500
12000
124
2965
282
6766
18
125
3000
31
741
105
2513
19
16
375
93
15
357
20
187.5
46
183
Figure 11-32. Delta-sigma ADC IDD vs sps, Range = 1.024 V, Figure 11-33. Delta-sigma ADC Noise Histogram, 1000
Continuous Sample Mode, Input Buffer Bypassed
Samples, 20-Bit, 187 sps, Ext Ref, VIN = VREF/2, Range =
1.024 V
Page 90 of 137
Table 11-23. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Single Ended
Sample rate,
sps
0 to VREF
0 to VREF x 2
VSSA to VDDA
0 to VREF x 6
2000
1.21
1.02
1.14
0.99
3000
1.28
1.15
1.25
1.22
6000
1.36
1.22
1.38
1.22
12000
1.44
1.33
1.43
1.40
24000
1.67
1.50
1.43
1.53
48000
1.91
1.60
1.85
1.67
Table 11-24. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Differential
Sample rate,
sps
VREF
VREF / 2
VREF / 4
VREF / 8
VREF / 16
2000
0.56
0.65
0.74
1.02
1.77
4000
0.58
0.72
0.81
1.10
1.98
8000
0.53
0.72
0.82
1.12
2.18
15625
0.58
0.72
0.85
1.13
2.20
32000
0.60
0.76
43750
0.58
0.75
48000
0.59
Table 11-25. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Single Ended
Sample rate,
sps
0 to VREF
0 to VREF x 2
VSSA to VDDA
0 to VREF x 6
1.28
1.24
6.02
0.97
23
1.33
1.28
6.09
0.98
45
1.77
1.26
6.28
0.96
90
1.65
0.91
6.84
0.95
187
1.87
1.06
7.97
1.01
Table 11-26. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Differential
Sample rate, sps
8
VREF / 2
VREF / 4
VREF / 8
VREF / 16
0.70
0.84
1.02
1.40
2.65
11.3
0.69
0.86
0.96
1.40
2.69
22.5
0.73
0.82
1.25
1.77
2.67
45
0.76
0.94
1.02
1.76
2.75
61
0.75
1.01
1.13
1.65
2.98
170
0.75
0.98
187
0.73
Page 91 of 137
Conditions
Initial trimming
20 C to 80 C, packages
100-TQFP, 68-QFN, 48-QFN
20 C to 80 C, package
48-SSOP
40 C to 85 C, packages
100-TQFP, 68-QFN, 48-QFN
40 C to 85 C, package
48-SSOP
Min
1.023
(0.1%)
Typ
1.024
Max
1.025
(+0.1%)
20
25
25
30
100
100
Units
V
ppm/C
ppm/Khr
ppm
Notes
43. Based on device characterization (Not production tested).
44. After eight full cycles between 40 C and 100 C.
45. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog
mux bus under these conditions is not recommended.
46. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.
Page 92 of 137
Conditions
VDDA = 3 V
VDDA = 3 V
Min
Typ
1472
Max
2200
Units
706
1100
11.5.5 Comparator
Table 11-29. Comparator DC Specifications
Parameter
VOS
Description
Conditions
Min
Typ
Max
Units
10
mV
mV
mV
Custom trim
mV
VDDA 4.6 V
12
mV
VHYST
Hysteresis
10
32
mV
VICM
VSSA
VDDA
VSSA
VDDA
VSSA
VDDA
1.15
CMRR
50
dB
ICMP
400
100
Min
Typ
Max
Units
VDDA 4.6 V
TRESP
Description
Conditions
50 mV overdrive, measured
pin-to-pin
75
110
ns
50 mV overdrive, measured
pin-to-pin
155
200
ns
50 mV overdrive, measured
pin-to-pin, VDDA 4.6 V
55
Description
Resolution
Conditions
Min
Typ
Max
Units
bits
Note
47. Based on device characterization (Not production tested).
Page 93 of 137
Description
Output current at code = 255
Conditions
Min
Typ
Max
Units
2.04
mA
2.04
mA
255
31.875
Yes
Monotonicity
Ezs
Eg
Gain error
TC_Eg
INL
DNL
Vcompliance
Differential nonlinearity
LSB
2.5
Range = 255 A, 25 C
2.5
Range = 31.875 A, 25 C
3.5
Range = 2.04 mA
0.04
% / C
Range = 255 A
0.04
% / C
Range = 31.875 A
0.05
% / C
0.9
LSB
1.2
1.5
LSB
0.3
LSB
0.3
LSB
Page 94 of 137
Description
Operating current, code = 0
Conditions
Min
Typ
Max
Units
44
100
33
100
33
100
36
100
33
100
33
100
310
500
305
500
305
500
310
500
300
500
300
500
Page 95 of 137
Page 96 of 137
Page 97 of 137
Description
Conditions
Min
Typ
Max
Units
FDAC
Update rate
Msps
TSETTLE
125
ns
Current noise
340
pA/sqrtHz
Page 98 of 137
Description
Conditions
Resolution
Min
Typ
Max
Units
bits
1.02
VOUT
1 V scale
4 V scale, Vdda = 5 V
4.08
INL1
Integral nonlinearity
1 V scale
2.1
2.5
LSB
DNL1
Differential nonlinearity
1 V scale
0.3
LSB
Rout
Output resistance
1 V scale
4 V scale
16
Yes
Monotonicity
VOS
Eg
Gain error
TC_Eg
IDD
Operating current
0.9
LSB
1 V scale,
2.5
4 V scale
2.5
0.03
%FSR / C
4 V scale
0.03
%FSR / C
100
500
Page 99 of 137
Description
Update rate
Conditions
Min
Typ
Max
Units
1 V scale
1000
ksps
4 V scale
250
ksps
0.45
TsettleP
0.8
3.2
TsettleN
0.45
4 V scale, Cload = 15 pF
0.7
750
nV/sqrtHz
Voltage noise
Description
Conditions
Min
Typ
Max
Units
10
mV
Quiescent current
0.9
mA
Gain
dB
Min
Typ
Max
Units
Description
Conditions
fLO
MHz
fin
14
MHz
fLO
Up mixer mode
MHz
fin
Up mixer mode
MHz
SR
Slew rate
V/s
Description
VIOFF
Rconv
Conversion resistance[48]
Conditions
Min
Typ
Max
Units
10
mV
R = 20K; 40 pF load
25
+35
R = 30K; 40 pF load
25
+35
R = 40K; 40 pF load
25
+35
R = 80K; 40 pF load
25
+35
R = 120K; 40 pF load
25
+35
R = 250K; 40 pF load
25
+35
R= 500K; 40 pF load
25
+35
R = 1M; 40 pF load
25
+35
1.1
mA
Quiescent current
Table 11-38. Transimpedance Amplifier (TIA) AC Specifications
Parameter
BW
Description
Input bandwidth (3 dB)
Min
Typ
Max
Units
R = 20K; 40 pF load
Conditions
1500
kHz
R = 120K; 40 pF load
240
kHz
R = 1M; 40 pF load
25
kHz
Note
48. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component data sheets. External
precision resistors can also be used.
Description
Conditions
Min
Typ
Max
Units
Vssa
Vdda
Vin
Vos
10
mV
TCVos
30
V/C
Ge1
0.15
Ge16
2.5
Ge50
Vonl
DC output nonlinearity
0.01
% of
FSR
Cin
Input capacitance
pF
Voh
VDDA 0.15
Vol
VSSA + 0.15
Vsrc
300
mV
Idd
Operating current
1.5
1.65
mA
PSRR
48
dB
Gain = 1
Description
Conditions
Min
Typ
Max
Units
6.7
MHz
V/s
43
nV/sqrtHz
BW1
3 dB bandwidth
SR1
Slew rate
en
Description
Temp sensor accuracy
Conditions
Range: 40 C to +85 C
Min
Typ
Max
Units
Min
Typ
Max
Units
ICC
Parameter
Description
38
ICC_SEG
260
VBIAS
LCD bias range (VBIAS refers to the VDDA 3 V and VDDA VBIAS
main output voltage(V0) of LCD DAC)
9.1 VDDA
mV
500
5000
pF
20
mV
355
710
Description
Conditions
Min
Typ
Max
Units
10
50
150
Hz
Description
Block current consumption
Conditions
16-bit timer, at listed input clock
frequency
3 MHz
12 MHz
48 MHz
67 MHz
Min
Typ
Max
Units
A
15
60
260
350
A
A
A
A
Min
DC
15
30
15
15
30
15
30
Typ
Max
67.01
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Description
Operating frequency
Capture pulse width (Internal)
Capture pulse width (external)
Timer resolution
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Conditions
Description
Block current consumption
Conditions
16-bit counter, at listed input clock
frequency
3 MHz
12 MHz
48 MHz
67 MHz
Min
Typ
Max
Units
A
15
60
260
350
A
A
A
A
Min
DC
15
15
15
30
15
30
15
30
Typ
Max
67.01
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Description
Operating frequency
Capture pulse
Resolution
Pulse width
Pulse width (external)
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Conditions
Description
Block current consumption
Conditions
16-bit PWM, at listed input clock
frequency
Min
Typ
Max
Units
3 MHz
15
12 MHz
60
48 MHz
260
67 MHz
350
Min
Typ
Max
Units
DC
67.01
MHz
Pulse width
15
ns
30
ns
15
ns
30
ns
Description
Operating frequency
Conditions
15
ns
30
ns
15
ns
30
ns
Description
Block current consumption
Conditions
Enabled, configured for 100 kbps
Enabled, configured for 400 kbps
Wake from sleep mode
Min
Typ
Max
250
260
30
Units
A
A
A
Min
Typ
Max
Units
Mbps
Conditions
Min
Typ
Max
200
Units
A
Conditions
Minimum 8 MHz clock
Min
Typ
Max
1
Units
Mbit
Description
Conditions
Bit rate
11.6.5 Controller Area Network[49]
Table 11-52. CAN DC Specifications
Parameter
IDD
Description
Block current consumption
Description
Bit rate
Description
DFB operating current
Conditions
Min
Typ
Max
Units
0.03
0.05
mA
0.16
0.27
mA
0.33
0.53
mA
3.3
5.3
mA
15.7
25.5
mA
21.8
35.6
mA
Min
Typ
Max
Units
DC
67.01
MHz
Description
DFB operating frequency
Conditions
Note
49. Refer to ISO 11898 specification for details.
Description
Min
Typ
Max
Units
4.35
5.25
VUSB_3.3
3.15
3.6
VUSB_3
2.85
3.6
10
mA
mA
0.5
mA
0.3
mA
0.5
mA
0.3
mA
VUSB_5
IUSB_Configured
Conditions
Description
Conditions
Min
Typ
Max
Units
67.01
MHz
67.01
MHz
67.01
MHz
67.01
MHz
Datapath Performance
FMAX_CRC
PLD Performance
FMAX_PLD
20
25
ns
tCLK_OUT
55
ns
Note
50. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 84.
11.7 Memory
Specifications are valid for 40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.7.1 Flash
Table 11-58. Flash DC Specifications
Parameter
Description
Erase and program voltage
Conditions
VDDD pin
Min
Typ
Max
Units
1.71
5.5
Min
Typ
Max
Units
Description
Conditions
TWRITE
15
20
ms
TERASE
10
13
ms
ms
35
ms
TBULK
15
ms
1.5
seconds
20
years
10
No overhead[51]
Note
51. See application note AN62391 for a description of a low-overhead method of programming PSoC 3 flash.
Description
Conditions
Min
Typ
Max
Units
1.71
5.5
Min
Typ
Max
Units
Description
Conditions
20
ms
20
years
20
10
Conditions
Min
Typ
Max
Units
1.71
5.5
Min
Typ
Max
Units
Description
Erase and program voltage
VDDD pin
Description
NVL endurance
NVL data retention time
Conditions
Programmed at 25 C
1K
program/erase cycles
Programmed at 0 C to 70 C
100
program/erase cycles
Programmed at 25 C
20
years
Programmed at 0 C to 70 C
20
years
Min
Typ
Max
Units
1.2
Min
Typ
Max
Units
DC
67.01
MHz
11.7.4 SRAM
Table 11-64. SRAM DC Specifications
Parameter
VSRAM
Description
Conditions
Description
SRAM operating frequency
Conditions
EM_ CEn
Taddrv
EM_ Addr
Taddrh
Address
Toel
EM_ OEn
EM_ WEn
Tdoesu
Tdoeh
EM_ Data
Data
Description
period[52]
EMIF clock
Tcel
Conditions
Min
Vdda 3.3 V
Typ
Max
Units
30.3
nS
2T 5
2T+ 5
nS
Taddrv
nS
Taddrh
nS
Toel
2T 5
2T + 5
nS
Tdoesu
T + 15
nS
Tdoeh
nS
Min
Typ
Max
Units
30.3
nS
T5
T+5
nS
EM_ Addr
Address
Tcel
EM_ CEn
Twel
EM_ WEn
EM_ OEn
Tdweh
Tdcev
EM_ Data
Data
Description
period[52]
Conditions
Vdda 3.3 V
EMIF clock
Tcel
Taddrv
nS
Taddrh
nS
Twel
T5
T+5
nS
Tdcev
nS
Tdweh
nS
Note
52. Limited by GPIO output frequency, see Table 11-10 on page 79.
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Toeld
Toehd
EM_ OEn
Tds
Data
EM_ Data
Tadscld
Tadschd
EM_ ADSCn
Description
period[53]
Conditions
Vdda 3.3 V
Min
Typ
Max
Units
30.3
nS
EMIF clock
Tcp/2
T/2
nS
Tceld
nS
Tcehd
T/2 5
nS
Taddrv
nS
Taddriv
T/2 5
nS
Toeld
nS
Toehd
nS
Tds
T + 15
nS
Tadscld
nS
Tadschd
T/2 5
nS
Note
53. Limited by GPIO output frequency, see Table 11-10 on page 79.
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Tweld
Twehd
EM_ WEn
Tds
Tdh
Data
EM_ Data
Tadscld
Tadschd
EM_ ADSCn
Description
Min
Typ
Max
Units
30.3
nS
T/2
nS
nS
Tcehd
T/2 5
nS
Taddrv
nS
Taddriv
T/2 5
nS
Tweld
nS
Twehd
T/2 5
nS
Tds
nS
Tdh
nS
Tadscld
nS
Tadschd
T/2 5
nS
Tcp/2
Tceld
Conditions
Vdda 3.3 V
Note
54. Limited by GPIO output frequency, see Table 11-10 on page 79.
Description
PRESR
PRESF
Conditions
Factory trim
Min
Typ
Max
Units
1.64
1.68
1.62
1.66
Min
Typ
Max
Units
0.5
V/sec
Min
Typ
Max
Units
1.68
1.89
2.14
2.38
2.62
2.87
3.11
3.35
3.59
3.84
4.08
4.32
4.56
4.83
5.05
5.30
5.57
1.73
1.95
2.20
2.45
2.71
2.95
3.21
3.46
3.70
3.95
4.20
4.45
4.70
4.98
5.21
5.47
5.75
1.77
2.01
2.27
2.53
2.79
3.04
3.31
3.56
3.81
4.07
4.33
4.59
4.84
5.13
5.37
5.63
5.92
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Min
Typ
Max
Units
Description
Conditions
Sleep mode
Conditions
Description
Response
time[55]
Conditions
Note
55. Based on device characterization (Not production tested).
Description
Conditions
Delay from interrupt signal input to ISR Includes worse case completion of
code execution from ISR code
longest instruction DIV with 6
cycles
Min
Typ
Max
Units
25
Tcy CPU
TCK
T_TDI_setup
T_TDI_hold
TDI
T_TDO_valid
T_TDO_hold
TDO
T_TMS_setup
T_TMS_hold
TMS
Description
TCK frequency
Conditions
3.3 V VDDD 5 V
1.71 V VDDD < 3.3 V
T_TDI_setup
Min
Typ
Max
Units
14[57]
MHz
MHz
ns
7[57]
(T/10) 5
T/4
T/4
T_TMS_setup
T_TDI_hold
T = 1/f_TCK max
T_TDO_valid
T = 1/f_TCK max
2T/5
T_TDO_hold
T = 1/f_TCK max
T/4
Notes
56. Based on device characterization (Not production tested).
57. f_TCK must also be no more than 1/3 CPU clock frequency.
SW DCK
T _S W D I_setup T _S W D I_hold
S W D IO
(P S oC input)
T _S W D O _va lid
T _S W D O _hold
S W D IO
(P S oC output)
Description
Conditions
Min
Typ
Max
Units
MHz
3.3 V VDDD 5 V
14[59]
7[59]
MHz
5.5[59]
MHz
T/4
T_SWDI_hold
T = 1/f_SWDCK max
T/4
T = 1/f_SWDCK max
2T/5
Min
Typ
Max
Units
33
Mbit
f_SWDCK
SWDCLK frequency
Description
SWV mode SWV bit rate
Conditions
Notes
58. Based on device characterization (Not production tested).
59. f_SWDCK must also be no more than 1/3 CPU clock frequency.
Description
Conditions
Min
Typ
Max
Units
62.6 MHz
600
48 MHz
500
500
300
Supply current
12 MHz
200
6 MHz
180
3 MHz
150
Note
60. Based on device characterization (Not production tested).
Description
Conditions
Min
Typ
Max
Units
62.6 MHz
48 MHz
FIMO
0.25
0.25
12 MHz
6 MHz
3 MHz
13
F = 24 MHz
0.9
ns
F = 3 MHz
1.6
ns
F = 24 MHz
0.9
ns
F = 3 MHz
12
ns
Startup
time[61]
Note
61. Based on device characterization (Not production tested).
Description
Operating current
Conditions
Min
Typ
Max
Units
FOUT = 1 kHz
0.3
1.7
FOUT = 33 kHz
1.0
2.6
1.0
2.6
2.0
15
nA
Min
Typ
Max
Units
ms
100 kHz
45
100
200
kHz
1 kHz
0.5
kHz
100 kHz
30
100
300
kHz
1 kHz
0.3
3.5
kHz
ICC
Leakage current
Table 11-81. ILO AC Specifications
Parameter
Description
Startup time, all frequencies
Conditions
Turbo mode
FILO
Description
Conditions
Min
Typ
Max
Units
25
MHz
Min
Typ
Max
Units
0.25
1.0
Description
ICC
Operating current
DL
Drive level
Conditions
Low-power mode; CL = 6 pF
Note
62. Based on device characterization (Not production tested).
Description
Frequency
TON
Startup time
Conditions
High power mode
Min
Typ
Max
Units
32.768
kHz
Min
Typ
Max
Units
33
MHz
30
50
70
0.51
V/ns
Description
Conditions
Measured at VDDIO/2
VIL to VIH
Description
PLL operating current
Min
Typ
Max
Units
Conditions
400
200
Min
Typ
Max
Units
48
MHz
MHz
24
67
MHz
Description
PLL intermediate
Fpllout
Conditions
Output of prescaler
250
250
ps
Notes
63. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
64. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
65. Based on device characterization (Not production tested).
SRAM (KB)
EEPROM (KB)
ADC
DAC
Comparator
SC/CT
Analog Blocks[66]
Opamps
DFB
CapSense
UDBs[67]
16-bit Timer/PWM
FS USB
CAN 2.0b
Total I/O
GPIO
SIO
USBIO
Digital
Flash (KB)
Analog
MCU Core
CY8C3865PVI-060
67
32
20-bit Del-Sig
20
29
25
48-pin SSOP
CY8C3865AXI-019
67
32
20-bit Del-Sig
20
72
62
100-pin TQFP
01E013069
CY8C3865LTI-014
67
32
20-bit Del-Sig
20
48
38
68-pin QFN
01E00E069
CY8C3865LTI-062
67
32
20-bit Del-Sig
20
31
25
48-pin QFN
01E03E069
CY8C3865PVI-063
67
32
20-bit Del-Sig
20
31
25
48-pin SSOP
01E03F069
CY8C3866LTI-067
67
64
20-bit Del-Sig
24
31
25
48-pin QFN
01E043069
CY8C3866PVI-021
67
64
20-bit Del-Sig
24
31
25
48-pin SSOP
01E015069
Part Number
Package
JTAG ID[69]
01E03C069
32 KB Flash
64 KB Flash
CY8C3866AXI-039
67
64
20-bit Del-Sig
24
72
62
100-pin TQFP
01E027069
CY8C3866LTI-030
67
64
20-bit Del-Sig
24
48
38
68-pin QFN
01E01E069
01E044069
CY8C3866LTI-068
67
64
20-bit Del-Sig
24
31
25
48-pin QFN
CY8C3866AXI-040
67
64
20-bit Del-Sig
24
72
62
100-pin TQFP
01E028069
CY8C3866PVI-070
67
64
20-bit Del-Sig
24
29
25
48-pin SSOP
01E046069
CY8C3866AXI-035
67
64
20-bit Del-Sig
24
70
62
100-pin TQFP
01E023069
Notes
66. Analog blocks support a variety of functionality including TIA, PGA, and mixers. See the Example Peripherals on page 42 for more information on how analog blocks
can be used.
67. UDBs support a variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple
UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 42 for more information on how UDBs can be used.
68. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 35 for details on the functionality of each of
these types of I/O.
69. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
3: PSoC 3
5: PSoC 5
4: CY8C34 family
6: CY8C36 family
8: CY8C38 family
g: Temperature range
C: commercial
I: industrial
A: automotive
c: Speed grade
4: 48 MHz
6: 67 MHz
d: Flash capacity
4: 16 KB
5: 32 KB
6: 64 KB
Examples
CY8C
3 8 6 6 P V
x x x
Cypress Prefix
3: PSoC 3
8: CY8C38 Family
Architecture
Family Group within Architecture
6: 67 MHz
Speed Grade
6: 64 KB
Flash Capacity
PV: SSOP
Package Code
I: Industrial
Temperature Range
Peripheral Set
All devices in the PSoC 3 CY8C38 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free
products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress
uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high-level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration data sheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other end of
life requirements.
Description
Conditions
Min
Typ
Max
Units
TA
40
25.00
85
TJ
40
100
TJA
49
C/Watt
TJA
14
C/Watt
TJA
15
C/Watt
TJA
34
C/Watt
TJC
24
C/Watt
TJC
15
C/Watt
TJC
13
C/Watt
TJC
10
C/Watt
Maximum Peak
Temperature
48-pin SSOP
260 C
30 seconds
48-pin QFN
260 C
30 seconds
68-pin QFN
260 C
30 seconds
100-pin TQFP
260 C
30 seconds
MSL
48-pin SSOP
MSL 3
48-pin QFN
MSL 3
68-pin QFN
MSL 3
100-pin TQFP
MSL 3
51-85061 *E
001- 45616 *D
001-09618 *D
51-85048 *G
Description
Acronym
Description
FIR
FPB
FS
full-speed
GPIO
HVI
abus
ADC
analog-to-digital converter
AG
analog global
AHB
IC
integrated circuit
ALU
IDAC
AMUXBUS
IDE
I2C,
API
APSR
ARM
ATM
BW
bandwidth
CAN
CMRR
or IIC
IIR
ILO
IMO
INL
I/O
IPOR
CPU
IPSR
CRC
IRQ
interrupt request
DAC
ITM
DFB
LCD
DIO
LIN
DMA
LR
link register
DNL
LUT
lookup table
DNU
do not use
LVD
DR
LVI
DSI
LVTTL
DWT
MAC
multiply-accumulate
ECC
MCU
microcontroller unit
ECO
MISO
master-in slave-out
EEPROM
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
NVL
EMI
electromagnetic interference
EMIF
EOC
end of conversion
EOF
end of frame
EPSR
ESD
electrostatic discharge
ETM
opamp
operational amplifier
PAL
PC
program counter
PCB
PGA
Description
Description
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
PICU
TTL
transistor-transistor logic
PLA
TX
transmit
PLD
UART
PLL
phase-locked loop
PMDD
UDB
POR
power-on reset
USB
PRES
USBIO
PRS
PS
VDAC
PSoC
Programmable System-on-Chip
WDT
watchdog timer
PSRR
WOL
PWM
pulse-width modulator
WRES
RAM
random-access memory
XRES
RISC
reduced-instruction-set computing
XTAL
crystal
RMS
root-mean-square
RTC
real-time clock
RTL
RTR
RX
receive
SAR
SC/CT
SCL
SDA
degrees Celsius
S/H
dB
decibels
SINAD
fF
femtofarads
SIO
Hz
hertz
KB
1024 bytes
kbps
Khr
kilohours
kHz
kilohertz
kilohms
ksps
LSB
SOC
start of conversion
SOF
start of frame
SPI
SR
slew rate
SRAM
SRES
software reset
SWD
SWV
single-wire viewer
TD
THD
Symbol
Unit of Measure
Mbps
MHz
megahertz
megaohms
Msps
microamperes
Page 129 of 137
Unit of Measure
microfarads
microhenrys
microseconds
microvolts
microwatts
mA
milliamperes
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts
ohms
pF
picofarads
ppm
ps
picoseconds
seconds
sps
sqrtHz
volts
Products
PSoC Solutions
Automotive
Clocks & Buffers
Interface
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
Wireless/RF
cypress.com/go/wireless
Cypress Semiconductor Corporation, 2006-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
CapSense , PSoC 3, PSoC 5, and PSoC Creator are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced
herein are property of the respective corporations.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders..